JPH0422077B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is a cross recording method that converts a luminance signal into an FM signal, converts a chroma signal into a reduced signal, and records both signals on a tape using two heads with different azimuth angles. The present invention relates to an azimuth helical scan video tape recorder, and in particular to a recording/reproducing circuit for both NTSC/PAL chroma signals.

There is a β method as a chroma signal recording method used in NTSC cross-azimuth helical scan video tape recorders. The problems with this method are (1) it requires a large number of flip-flops (hereinafter referred to as FF) that operate at high speed, making it difficult to integrate into ICs, and (2) it is difficult to secure a bandwidth for chroma signals, especially when multiplexing pilot signals for tracking control. There are problems when recording: (3) the chroma signal IC that can be used for both the NTSC and PAL systems becomes extremely complex, and (4) the chroma signal recording circuit and pilot signal generation circuit cannot be used together. It was hot.

The conventional problems will be explained in detail below using the drawings. FIG. 1 is a block diagram showing the main parts of a chroma signal recording circuit of a β-system video tape recorder.

First, the method of recording NTSC chroma signals in a β-scheme video tape recorder will be explained. In the β method, the 3.58MHz chroma signal is converted to a frequency of (44-1/4) _H , ( _H is the horizontal synchronization frequency), and
The first track records the frequency-converted chroma signal as it is, and the second track inverts the phase of the frequency-converted chroma signal every horizontal period to change the chroma frequency to (44-1/4± 1/2) Converted to _H and recorded. As a result of the above, the recording chroma signal frequency has an offset of _H /4, which is a necessary and sufficient condition, and the frequency difference between tracks is
_H /2 is satisfied.

Next, the above operation will be explained using FIG.
1 is the chroma signal input terminal, 2 is a voltage-controlled oscillator (hereinafter referred to as VCO) that oscillates at a frequency of 175 _H , 3 is a 1/4 frequency divider, 4 is the first frequency converter, and 5 is the 4th frequency converter. A filter 6 extracts the sum frequency signal from the output; 6 is a circuit that does nothing on the first track, and inverts the phase every horizontal period on the second track; 40 is a circuit for inputting a signal indicating the track; 8 is a low-pass filter that extracts the difference frequency signal from the output of 7, 9 is a 1/175 frequency divider, 1/5 frequency divider 10, 1/5 frequency divider 11, 1/7 frequency divider It is composed of a frequency generator 12. A phase comparator 13 detects the phase difference between the output signal of the frequency divider 9 and the horizontal synchronizing signal applied to the terminal 17, and drives the VCO 2. 14 is a 3.58MHz X'tal VCO, and a phase comparator 15 detects the phase difference between the output signal of 14 and the output signal of the burst gate circuit 16. Therefore, a carrier whose frequency matches that of the chroma signal applied to terminal 1 is obtained at the output of VCO 14.
A (175/4 _H +3.58) MHz signal is taken out from the output of the filter 5, and the first signal is taken out from the output of the phase inversion circuit 6.
A signal of (175/4 _H +3.58) MHz is obtained on the first track, and a signal of {(175/4±1/2) _H +3.58} MHz is obtained on the second track. Therefore, the low frequency conversion chroma signal output terminal 19 has a signal for the first track.
A chroma signal converted to a frequency of 175/ _4H is output, and a chroma signal converted to a frequency of (175/4±1/2) _H is output for the second track.

Next, the above-mentioned problem (1) will be explained. In Figure 1, a 1/175 frequency divider 9 is required, and in order to design this frequency divider 9 to have the minimum chip size and minimum power consumption, a 1/5 frequency divider 9 is required as shown in Figure 1. The frequency divider 12 is divided into 0,111/7 frequency dividers 12, and in particular, the frequency divider 10 is composed of a high-speed flip-flop (hereinafter referred to as FF) so as to be able to divide 175 _H (2.75 MHz).

FIG. 2 is a circuit diagram showing a specific example of the frequency divider 10 of FIG. 1. To divide frequencies over 2MHz, a synchronous counter shown in Figure 2 is required, and FF22, 2
All of 3 and 24 must operate at _175H (=2.75MHz). FF operating at 2MHz or higher is 500KHz
The required chip size and power consumption are approximately 10 times larger than FFs that operate at the following speeds, so the key point is how to reduce the number of high-speed FFs. The frequency divider 9 of the system shown in FIG. 1 requires three high-speed FFs, which leads to an increase in chip size and power consumption. Next, the above-mentioned problem (2) will be explained. FIG. 3 shows a recording signal spectrum 26 in the chroma signal band, a pilot signal spectrum 27, and a frequency characteristic 25 of the tape head system.
As can be seen from the figure, the lower side wave of the chroma signal is close to the cutoff frequency of the tape head system, and in order to secure a sufficient bandwidth of the chroma signal, it is necessary to further increase the low frequency conversion frequency from 688KHz to 700KHz or more. be. Furthermore, when recording the tracking control pilot signal 27 multiplexed, it is necessary to further increase the recording frequency of the chroma signal. Set the pilot frequency as the pilot signal to _6.5H (102K
Hz), 7.5 _H , 9.5 _H , and 10.5 _H (165KHz). In this case, if the chroma frequency is set to 688 KHz, there is a problem that the frequencies are too close to each other and interference caused by the pilot signal cannot be sufficiently removed.

Next, the problem (3) mentioned above will be explained. β
The frequency of the PAL chroma signal of the video tape recorder is selected to be (44-1/8) _H for the first track and (44+1/8) _H for the second track. Therefore, if NTSC and PAL are shared in the configuration shown in Figure 1, VCO2 will be 175 _H for NTSC, 351 _H for PAL,
It is necessary to switch in three ways: 353 _H. Furthermore, the frequency divider 3 must be switched to 1/4 in NTSC and 1/8 in PAL, and the frequency divider 9 must be switched in three ways: 1/175 in NTSC, 1/351 and 1/353 in PAL. Among the above switching, the switching of 1/175, 1/351, and 1/353 of the frequency divider 9 is 175=5×5×7.
351 = 3 x 3 x 3 x 13, 353 = 353 (prime number), and as mentioned above, the frequency divider cannot be divided, so all FFs that make up the 1/353 frequency divider must operate at high speed, and in the end, It becomes impossible to use the frequency divider 9 for both NTSC and PAL.

Next, the aforementioned problem (4) will be explained. FIG. 4 shows a circuit in which a pilot signal generation frequency divider 28 is added to the chroma signal circuit of FIG. 1, and 29 is an output terminal for the pilot signal. At the input of the frequency divider 28,
Since a signal of 175 _H is applied, when the frequency divider 28 is switched to 1/17, 1/19, 1/24, and 1/28 for each track, the pilot signal output terminal 29 receives ₁ = 175/17 _H = 10.29 _H , ₂ = 175/19 _H = 9.21 _H , ₃ = 175/24
Signals of _H = 7.29 _H and ₄ = 175/28 _H = 6.25 _H are obtained, respectively. The ideal pilot frequency is (n+1/3) _H to (n+2/3) _H , n=6, 7, 9, 10. This is determined by the fact that it is less susceptible to high-frequency interference from flyback pulses from the television and that the pilot signal is less likely to interfere with chroma and luminance signals. Furthermore, the conditions for stabilizing tracking control are A = | ( ₁ − ₂ ) − ( ₃ − ₄ ) | and B = | ( ₁ −
₃ )−
( ₂ − ₄ ) | is as close to zero as possible. In FIG. 4, the problem is that the frequency deviates considerably from the ideal, and that A=0.05 _H and β=0.04 _H are quite large.

SUMMARY OF THE INVENTION An object of the present invention is to provide a circuit for recording both NTSC/PAL chroma signals on a videotape, which solves all of the above-mentioned four problems.

The present invention includes: a reference oscillator that oscillates at a specific oscillation frequency; a low-frequency conversion carrier generator that converts the oscillation signal from the reference oscillator into a low-frequency conversion carrier; and a low-frequency conversion carrier generator that generates a low-frequency conversion carrier from the low-frequency conversion carrier generator. It consists of a mixer for generating a converted carrier color signal by mixing the converted carrier and the carrier color signal to be recorded, and a magnetic head for recording the low frequency converted carrier color signal on a magnetic tape, When the color signal system is the NTSC system, the carrier frequency of the above low-pass conversion carrier color signal is 47 + 1/4 times the horizontal frequency, and the phase of the carrier wave is inverted every horizontal period in one field.
In the other field, the low frequency conversion carrier is determined so that no reversal occurs for each horizontal period.If the color signal system to be recorded is the PAL system, the low frequency conversion carrier color signal is such that the frequency of the carrier wave is horizontal. The above low frequency conversion carrier is set so that the frequency is 47-1/8 times the value, and the phase advances by 90 degrees for each horizontal period in one field, while the phase does not advance for each horizontal period in the other channel. This minimizes the semiconductor chip size and power consumption required for the frequency divider used in the above-mentioned low-frequency conversion carrier generator, and by selecting the chroma frequency at 700 KHz or higher, secures bandwidth and improves coexistence with the pilot signal. do.

Embodiments of the present invention will be described below with reference to FIGS. 5 to 11.

FIG. 5 is a block diagram showing the main parts of a chroma signal recording circuit according to an embodiment of the present invention. The feature of FIG. 5 is that the oscillation frequency of the VCO 2 is 189 _H = 3 x N _H , and N = 63 = 3 x 3 x 7. Therefore, the difference between Figure 5 and Figure 1 is
The oscillation frequency of VCO2 and the configuration of frequency divider 9,
As a result, the frequency of the recording chroma signal appearing at the output terminal 19 becomes (47+1/4) _H . The 1/189 frequency divider 9 is composed of 1/3 frequency dividers 30, 31, 32 and 1/7 frequency divider 33. The input frequency of the 1/3 frequency divider 30 is 189 _H = 2.97MHz, which requires high-speed operation. Therefore, as mentioned above, a synchronous counter is desirable, and the configuration of the FF shown in FIG. 6 can be considered.
As is clear from FIG. 6, only two FFs are required, and the chip size and power consumption required for the frequency divider 9 can be minimized. On the other hand, the frequency of the low frequency converted chroma signal is (47 + 1/4) _H ≒ 743KHz, as can be seen from the relationship between the spectrum 39 of this chroma signal and the frequency characteristic 25 of the tape head system shown in Figure 7.
It is a perfect frequency to secure a band of 743±500KHz. In addition, the pilot signal 27
Even when multiplexing chroma signals, the pilot signal frequency is 102 to 165 KHz and the lower end frequency of the chroma signal.
Approximately 80KHz is provided between it and 243KHz, which is an appropriate frequency arrangement to prevent mutual interference.

FIG. 8 is a block diagram showing the main parts of a chroma signal recording circuit according to another embodiment of the present invention. The difference between FIG. 8 and FIG. 5 is that in FIG. 8, the frequency divider 3 in FIG. 5 is divided into 1/2 frequency dividers 41 and 42, and a waveform shaper 43 is added. Phase inversion circuit 6
This is because the format of .

The reason why the frequency divider 3 is divided into 1/2 frequency dividers 41 and 42 is to supply a 189/2 _H signal to the waveform shaper 43, and to supply a 189/4 _H signal with a phase difference of approximately 180° from each other. This is to obtain a signal. (The Q and Q⌒ outputs of the FF can be used as they are.) The phase inversion circuit 6 in _FIG . Two signals are input, and switching is performed so that the input signal on one side is output as is in the first track, and the two input signals are output alternately in each horizontal period in the second track. Waveform shaping circuit 4
3 has the function of adjusting the rising timing of the output signal of the phase inversion circuit 6. As shown in FIG. 9, an embodiment of the waveform shaping circuit 43 is such that the output signal of the 1/2 frequency divider 41 is applied to the T input terminal 45 of the FF, and the output signal of the phase inversion circuit 6 is applied to the D input terminal 46. As a result, a signal with a well-timed rise is sent to output terminal 4.
7.

FIG. 10 is a block diagram showing the main parts of an embodiment in which the NTSC chroma signal recording circuit of the present invention is used in a PAL chroma signal recording circuit. In Figure 10, NTSC is a recording method in which the chroma signal frequency is selected to be (47+1/4) _H on the first track, and the phase is inverted so that it becomes (47+1/4±1/2) _H on the second track. and PAL is the first
In the first track, the phase is set to (47-1/8) _H , and in the second track, the phase is shifted by +90° for each horizontal period so that it becomes (47-1/8 + 1/4) _H. In the second track, a recording method is used in which a phase shift is performed in which the phase is delayed by 90 degrees every horizontal period so that the signal becomes (47-1/8-1/4) _H .
The difference between Fig. 10 and Fig. 8 is that the output of the 1/4 frequency divider 3 is 0°, 90°, 180°, 270°, and the phase is 90° to each other.
In place of the phase inversion circuit 6, the first track of NTSC and PAL does not invert or shift the phase, and the second track inverts the phase of NTSC and PAL. In this case, a phase selection circuit 48 for performing a 90° phase shift is provided.
In NTSC, the frequency is the same as the input chroma signal ( _sc
= 3.579545MHz) is input to the first converter 4, and in PAL, the frequency of the input chroma signal ( _sc =
A switch 50 and a crystal oscillator 51 are provided for inputting a carrier with a frequency 3/8 _H lower than 4.433618MHz) to the first converter 4, and a control signal input terminal 49 is provided for switching between NTSC and PAL. In addition, a pilot signal generation circuit 52 and a pilot signal output terminal 53 are provided.

The pilot signal generation circuit 52 has the following formulas _{: 1} = 189/18 _H = 10.50 _H , ₂ = 189/20 _H = 9.45 _H , ₃ = 189/25
It can output four signals: _H = 7.56 _H , ₄ = 189/29 _H = 6.52 _H , which is the ideal value for the pilot frequency.
(n+1/3) _H < ₁ , ₂ , ₃ , ₄ < (n+2/
3) _H is satisfied. Also, A=|( ₁ − ₂ )−( ₃ − ₄ )
｜
=0.01 _H , β=｜( ₁ − ₃ )−( ₂ − ₄ )｜=0.0
_1H , ensuring sufficient characteristics as a pilot signal.

FIG. 11 is a block diagram showing another embodiment of the NTSC and PAL chroma signal recording circuit described in FIG. 10. The difference between Figure 11 and Figure 10 is
The oscillation frequency of VCO2 is (47 + 1/4) x 8 _H = 378 _H for NTSC, (47 - 1/8) x 8 _H = 375 _H for PAL.
Therefore, frequency divider 9 is 1/378 = 1/3 x 1/ in NTSC.
3 x 1/3 x 1/2 x 1/7, 1/375 = 1/3 x for PAL
The frequency divider 31 is selected to be 1/5 x 1/5 x 1/5, and the 1/3 frequency divider 31 is selected between NTSC and PAL in order to minimize the chip size and power consumption when implementing the frequency divider 9 as an IC. The frequency divider 55 is switched to 1/6 for NTSC and 1/5 for PAL, the frequency divider 56 is switched to 1/3 for NTSC and 1/5 for PAL, and the frequency divider 57 is switched to 1/5 for NTSC. /7, PAL is switched to 1/5. Furthermore, by newly installing the 1/2 frequency divider 54, the output of the frequency divider 54 becomes _189H for NTSC and (187+1/2) _H for PAL. For this purpose, the switch 50 provided in FIG.
The crystal oscillator 51 is no longer necessary.

That is, in this embodiment, the input terminal 4
When operating as an MTSC chroma signal recording device by the control signal supplied to VCO
2 oscillates at 378H, and this oscillation output is divided into 1/8 by 1/2 frequency divider 54 and 1/4 frequency divider 3 to obtain an oscillation output of (47 + 1/4)H. When operating as a chroma signal recording device
VCO2 oscillates at 375H, and by dividing the frequency by 1/8, (47-1/8)H [=(187+1/2)H/4] is obtained.

In addition, as in the case of FIG. 10, the output of the phase selection circuit 48 is such that the phase transition for each horizontal synchronization is 1/2H in NTSC, that is, 90° in PAL, and 378H (in NTSC) or 375H (in NTSC). PAL) is divided into 1/2 by the 1/2 frequency divider 54 and then divided into 1/18, 1/20, 1/25 or 1/29 by the generation circuit 52, so the OSC2 oscillation Output is 1/36, 1/40, 1/50 or 1
Although the frequency is divided by /58, the pilot signal obtained at terminal 53 has the same frequency as in the case of FIG.

FIG. 12 is a diagram showing a specific embodiment of the phase selection circuit 48 shown in FIG. 11, and FIG.
15 is a timing diagram of this. 12th
In the figure, the same parts as in FIG. 11 are represented by the same numbers.

First, the operation in the NTSC format will be explained.

In the NTSC system, the control signal input terminal 49 is controlled to "H", and the frequency division ratio of the frequency divider 9 is set to 1/378 = 1/
3 × 1/3 × 1/3 × 1/2 × 1/7, and the NAND gates 118, 119,
120 to essentially connect the Q output of OFF 106 to the D input. In addition, one track becomes "H" due to the signal _14a indicating the track at one terminal 40.
OFF106 and 107 are reset during the period of . Therefore, the output signals of OFF106, 107 are 14c, 14d, 14e, 14f shown in FIG.
It is as follows. In the NAND gate 114, the inverter 125 is 14b and 14e, 115 and 126 are 14b and 14d, 116 and 127 are 14c and 14
d, 117 and 128 take the AND of 14c and 14d, respectively, to generate signals 14f, 14g, 14h, and 14i.

On the other hand, the VCO 2 has an oscillation frequency of 378 _H due to the frequency divider 9 and phase comparator 13. The output signal of this VCO 2 is passed through a terminal 100 to form a 1/2 frequency divider 54. Connect to the T terminal of OFF103. Further, the Q output 13a of the OFF 103 constitutes a 1/4 frequency divider 3. Connect to the T terminals of OFF104 and 105. In this case, change the output of OFF103 to 13b.
Even if it is connected to the T terminal of OFF104, 105, the effect is exactly the same. The Q terminals of OFF104 and 105 have frequencies as shown in Figure 13.
378/8 _H = (47+1/4) Signals 13c, 13d, 13e, and 13f whose phases differ from each other by 90 degrees are obtained at _H. This signal and the aforementioned 14f, 14g, 14
h, 14i and NAND gates 110, 111,
112 and 113 are ANDed, and during the period when the signal 14a indicating the track is "L", the NAND gate 1 is
24 outputs have a phase difference of 180°. 13c and 13e
is obtained every horizontal period. On the other hand, 14a is “H”
During the period, NAND gates 113, 112, 1
11 is closed, and the output of the NAND gate 124 is
13f is always obtained.

NAND gates 121, 122, 123 are OFF
108 Q, with a switch controlled by the terminal
The phase of the output signal of the NAND gate 124 is inverted every time a pulse signal is applied to the terminal 101. terminal 10
The pulse signal 1 is a signal that detects discontinuity in the reproduced chroma signal that occurs when switching heads, for example. The output signal of the NAND gate 103 is adjusted in phase by the OFF 109 that constitutes the waveform shaping circuit 43, and then sent to the converter 4 via the terminal 102.
connected to.

Next, the operation in PAL mode will be explained.

The difference from the NTSC method is control signal input terminal 4.
9 is controlled to "L" and the frequency division ratio of the frequency divider 9 is switched to 1/375 = 1/3 x 1/5 x 1/5 x 1/5;
and NAND gates 118, 119,
120 is switched, and the signal at the terminal of OFF107 is essentially connected to the D terminal of OFF106. In this case OFF106,107
The output signals of 14b, 14c, and 14c shown in FIG.
14d and 14e. Therefore, signals such as those shown in FIG. 15, 14f, 14g, 14h, and 14i are obtained at the outputs of the inverters 125, 126, 127, and 128. Also in this case OFF1
At the Q terminals of 04 and 105, 13 c, 13 d, 13 e, and 13 f having a frequency of 375/8 _H = (44-1/8) _H and a phase difference of 90 degrees from each other are obtained. By taking the logical product of this signal and the aforementioned signals 14f, 14g, 14h, and 14i, the output of the NAND gate 124 has signals 13c, 13d, 13e, and 13f of one horizontal level while the signal 14a indicating the track is "L". It is obtained every cycle, and 1 during the period when 14a is “H”.
3f is always obtained. Further, during the period when the signal 14a indicating the track is "L", the signals 13f, 13e, 13
d, 13c are obtained every horizontal period, and 13f is always obtained during the period when 14a is "H".
It is easy to imagine that the embodiment of FIG. 5 can be modified. Therefore, both a +90 degree phase shift and a -90 degree phase shift can be easily realized in the embodiment of FIG. Further, 13e, 13d, and 13c other than 13f may be obtained during the period when 14a is "H".

Operations other than those described above are the same as in the NTSC system. Next, we will discuss the influence of BPF5.

The input signal of the BPF 5 is the output signal of the converter 4 as described above. Therefore, the output signal of the BPF 5 exhibits a transient response to a slap-like phase shift of 180 degrees in the case of the NTSC system and 90 degrees in the case of the PAL system. In the NTSC system, this transient response is a phenomenon in which the amplitude of the output signal of the BPF 5 suddenly decreases once at the time of phase switching, but normally this period is sufficiently short and no phase response occurs, so there is no problem.
In addition, when using the PAL method, the amplitude and phase of the BPF5 output signal change at the time of phase switching, but in this case as well, this period is sufficiently short and does not pose a problem.
This is essentially the same phenomenon as that used in the VHS system, so this is not a problem either.

FIG. 16 shows another embodiment that can prevent the transient phenomenon of BPF5 that occurs in the NTSC system.

The difference between FIG. 16 and FIG. 11 is that the phase selection circuit 48 is divided into a 90 degree phase selection circuit 48' and a 180 degree phase selection circuit 54, and the 180 degree phase selection circuit 54 is
It is provided on the output side of BPF5.
Therefore, during NTSC, the transient phenomenon described above does not occur.

Figure 17 shows the 90 degree phase selection circuit 48' of Figure 16.
This is a specific example. The difference between FIG. 16 and FIG. 12 is that when the terminal 200 is controlled to "H" in the NTSC system, the output of the NAND gate 150 is always controlled to "H".
107 is in the reset state and the NAND gate 12
The signal of the terminal of OFF 104 is always obtained as the output of 4, and the waveform shaping circuit 43 includes a circuit for correcting the discontinuity of the reproduced chroma signal that occurs during head switching as described above. The output signal of the NAND gate 124 is adjusted in phase by the OFF 109, and the signal at the terminal Q, which is a signal with opposite phases to each other, is adjusted by the OFF 109.
Connected to NAND gates 121 and 122.
NAND gates 121, 122, and 123 are switches controlled by OFF 108 as described above, and operate in the same manner as in FIG. 12. Also
The operation in the PAL system is the same as that shown in FIG. 12, and the explanation will be omitted.

FIG. 18 shows a specific example of the 180 degree phase selection circuit 54. In FIG. 18, the same parts as in FIG. 16 are represented by the same numbers. First, we will explain the operation in the NTSC format.

In the NTSC system, the control signal input terminal 49 is controlled to "H", so the OFF 153 is reset while the signal indicating the track at the terminal 40 is "H", and the Q terminal is always controlled to "L". On the other hand, during the period when the signal indicating the track is "L", the output of the NAND gate 154 is controlled to "L", so OFF1
The Q terminal 53 is brought into the "L" and "H" states every horizontal period by a horizontal pulse connected to the terminal 18. On the other hand, the switch circuit 152 has a Q of OFF153.
When the terminal is in the "L" position shown in the figure, it is assumed that the terminal is switched to the position opposite to that shown in the figure. The output signal of the BPF 5 is connected to the primary winding of the transformer circuit 57, and the signal extracted from the middle point of the secondary winding is connected to the converter 7. Therefore, as mentioned above, the transformer circuit 5 is activated every horizontal period only during the period when the signal indicating the track is "L".
Since both ends of the secondary winding 7 are alternately grounded by the switch circuit 152, the polarity of the signal taken out from the midpoint of the secondary winding is inverted every horizontal period.

Next, the operation in PAL mode will be explained.

In PAL mode, control signal input terminal 49 is “L”
Therefore, the output of the NAND gate 154 is always "H". Therefore, the OFF 153 is in a reset state, and the Q terminal is always at "L", and the switch circuit 152 remains switched to the illustrated position. Therefore, since the output signal of the BPF 5 is directly connected to the converter via the transformer circuit 57, no phase inversion is performed.

FIG. 19 is another embodiment of FIG. 16.

The difference between FIG. 19 and FIG. 16 is that a 180 degree phase selection circuit 55 is connected between the input signal terminal 1 and the converter 7 instead of being connected to the output signal converter 7 of the BPF 5. It is easy to understand that the 180 degree phase selection circuit 55 can have substantially the same circuit configuration as that shown in FIG. In this case, the input signal circuit of the burst gate circuit 16 is taken out from before the 180-degree phase selection circuit 55.

FIG. 20 shows yet another embodiment of FIG. 16. The difference between FIG. 20 and FIG. 16 is that the output signal of BPF 5 is connected to converter 7, and instead, a 180 degree phase selection circuit 56 is connected to the output of LPF 8. 180 degree phase selection circuit 5
6 is the 180 degree phase selection circuit 54 shown in FIG. 18 mentioned above.
Considering the frequency characteristics of the transformer circuit 57, it is easy to understand that substantially the same circuit configuration is sufficient.

Next, another embodiment that can prevent the BPF transient phenomenon of the embodiment shown in FIG. 10 will be described.

FIG. 21 is another embodiment of FIG. 10.

The difference between FIG. 21 and FIG. 10 is that the phase selection circuit 48 is divided into a 90 degree phase selection circuit 48' and a 180 degree phase selection circuit 54, and the 180 degree phase selection circuit 54 is
It is provided on the output side of BPF5.
The operation in FIG. 21 is the same as that in FIG. 16, and the explanation will be omitted. Furthermore, it can be easily assumed that the embodiments shown in FIGS. 19 and 20 can be applied to the embodiment shown in FIG. 10, as described above.

According to the present invention, the number of flip-flops that require high-speed operation can be minimized, and when integrated into an IC, the chip size and power consumption can be minimized. Furthermore, the chroma signal recording circuits for the NTSC system and the PAL system can be made similar, and an IC for both NTSC and PAL systems can be designed extremely easily. Further, the chroma signal recording circuit of the present invention can be used in combination with a pilot signal generation circuit very easily, and the resulting pilot signal frequency can be set to an optimum value.

[Brief explanation of drawings]

Figure 1 shows the NTSC β format video tape recorder.
A block diagram showing the main parts of the chroma signal recording circuit, Fig. 2 is a circuit diagram showing an example of a 1/5 frequency divider, and Fig. 3 shows the chroma signal spectrum of a β-format video tape recorder and the frequency characteristics of the tape head system. 4 is a block diagram showing an example of the case where a pilot signal is generated from the chroma circuit shown in FIG. A circuit diagram showing an example of a 3 frequency divider, FIG. 7 is a diagram showing an example of the chroma signal spectrum of the present invention and frequency characteristics of a tape head system, and FIG. 8 is a main part of another example of the present invention. Block diagram showing the 9th
Figure 10 is a circuit diagram showing an example of a waveform shaping circuit, Figure 10 is a block diagram showing a main part of an embodiment in which the chroma signal recording circuit of the present invention is used for PAL, and Figure 11 is a block diagram showing an NTSC chroma signal recording circuit of the present invention. FIG. 2 is a block diagram showing a main part of an embodiment of a chroma signal recording circuit that can be used both as a recording circuit and a PAL chroma signal recording circuit that is compatible with the recording circuit. FIG. 12 is a circuit diagram showing a specific embodiment of the phase selection circuit.
3, 14, and 15 are timing diagrams of FIG. 12, FIG. 16 is a block diagram explaining another embodiment of the present invention, and FIG. 17 is a specific embodiment of a 90-degree phase selection circuit. 18 is a circuit diagram of a 180 degree phase selection circuit, FIGS. 19 and 20 are block diagrams explaining still another embodiment, and FIG. 21 is a block diagram showing another embodiment of the present invention. It is a diagram. DESCRIPTION OF SYMBOLS 1... Chroma signal input terminal, 4... First frequency converter, 6... Phase inversion circuit, 7... Second frequency converter, 2... Voltage controlled oscillator, 9...
Frequency divider, 27... Pilot signal, 30... 1/3 frequency divider, 43... Waveform shaping circuit.

Claims (1)

[Claims] 1. A reference oscillator that oscillates at a specific oscillation frequency, a low-frequency conversion carrier generator that generates a low-frequency conversion carrier based on an oscillation signal from the reference oscillator, and the low-frequency conversion carrier generation. a mixer for generating a converted carrier color signal by mixing the low frequency converted carrier from the device with a carrier color signal to be recorded; and a magnetic head for recording the low frequency converted carrier color signal on a magnetic tape; When the color signal system to be recorded is the NTSC system, the carrier frequency of the low-pass conversion carrier color signal is 47+1/4 times the horizontal frequency, and the phase of the carrier wave is reversed every horizontal period in one field. ,
In the other field, the low frequency conversion carrier is determined so that no reversal occurs for each horizontal period.If the color signal system to be recorded is the PAL system, the low frequency conversion carrier color signal is such that the frequency of the carrier wave is horizontal. The above low frequency conversion carrier is set so that the frequency is 47-1/8 times the value, and the phase advances by 90 degrees for each horizontal period in one field, while the phase does not advance for each horizontal period in the other channel. A chroma signal recording device characterized in that: