JPH0422277B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a speech recognition device that recognizes speech.

(B) Conventional Example When trying to control some kind of equipment by recognizing speech, the response time, which mostly corresponds to the recognition operation, always becomes a problem. In order to speed up the response time, it is generally considered to use a CPU, memory, or their peripheral circuits that can operate at high speed, but the entire system becomes expensive and the speed cannot be increased that much.

The existing speech recognition operation is shown in FIG.
a voice input period 10 in which the voice to be recognized is input;
The silent period 20, which means the end of the input voice, and the recognition period 30, which recognizes the input voice, are considered as one cycle, and the next voice recognition cycles 11, 21, and 31 follow these recognition cycles 10, 20, and 30. It begins. Therefore, the voice input period is 10, and the silent period is 2.
0. As long as the recognition periods 30 are serially provided, there is a limit to the speeding up of the recognition operation as described above.

(c) Purpose of the Invention The present invention has been made in view of the above-mentioned difficulties, and it is an object of the present invention to provide a speech recognition device that can speed up recognition operations.

(d) Structure of the Invention The speech recognition device of the present invention includes a first processor section for obtaining a speech characteristic pattern, a second processor section for recognition operation, and a processor section from the first processor section to the second processor section. an interface circuit for transmitting the feature pattern to the first processor section, and stores the feature pattern obtained by the first processor section in a first memory section provided in the first processor section. This made it possible to leave it as is.

(E) Embodiment FIG. 2 shows the recognition operation in the device of the present invention, in which the existence of the voice input period 10 and the silent period 20 is the same as in the first existing one, but the recognition period 3
The recognition operation performed in step 0 is performed in a separate part from the part that recognizes the input speech. That is, one processor P ₁ performs the input speech capture and feature extraction operations, and the other processor P ₂ performs the recognition of the feature patterns of the extracted speech.
These two processors P ₁ and P ₂ are intended to process the feature extraction operation and recognition operation in parallel. Therefore, as is clear from this Figure 2, the voice input 1
0, 11, 12... and silence 20, 21, 22... are alternately handled by one processor _P1 , and the recognition 30,
31, 32, etc. are handled by the other processor _P2 , so that the recognition time can be shortened as a result.

FIG. 3 is a block diagram showing the specific configuration of the device of the present invention, in which 1 is a microphone that converts audio into an electrical audio signal, and 2 is a block diagram that extracts the characteristics of the audio signal from microphone 1. It is a feature extraction circuit, which consists of, for example, eight bandpass filters, and uses frequency spectrum values x ₁ (t), x ₂ (t), ..., x ₃ (t) of each frequency obtained by dividing the audio band into 8 as components. A time series of vector parameters x(t) is sampled over the audio time domain.
3 is a first memory section, and this feature extraction circuit 2
A buffer area that temporarily stores the original speech pattern consisting of the time series of parameters x(t) extracted in
M1BUF and a voice characteristic pattern X obtained by normalizing the time series of parameters x(t) of the original voice pattern stored in the buffer area M1BUF to 16 samples
= Multiple stack areas M1-0, M1-1, M1-2, M1 for storing (x(1), x(2), ..., x(16))
-3... 4 is the above audio extraction circuit 2
The extraction operation in , the loading of the extracted original feature pattern into the buffer area M1BUF of the first memory unit 3, the normalization of the original feature pattern in this buffer area M1BUF, and the normalization of this normalized feature pattern
The first CPU is responsible for the storage process in the stack areas M1-0, ... or the detection operation for detecting the end of the voice from the silent state of the input voice. , the first memory section 3, and the CPU 4 constitute a first processor _P1 .

On the other hand, 5 is a second memory section, which includes vector parameters x(1), x(2), . . . in the same format as the normalized feature pattern X of the voice obtained by the first processor _P1 . Reference pattern consisting of x(16)
A reference pattern area M2PTN in which Xr is stored for a large number of sounds, and a _first
a plurality of second stack areas for introducing and storing the normalized feature pattern X of the input voice stored in the stack units M1-0, . . . of the memory unit 3;
It is equipped with M2-0, M2-1, M2-2, M2-3,... Reference numeral 6 indicates the characteristic pattern X of the input voice stored in the second stack area M2-0, . . . of the second memory unit 5 and its reference pattern area in advance
This is a speech recognition circuit that compares and recognizes a large number of reference patterns stored in the M2PTN, and performs recognition processing using, for example, a linear matching method. That is, according to this linear matching method, each vector parameter x(1), x(2), ..., x(16) of the feature pattern X of the input voice and each vector parameter xr(1), xr(2), ..., xr(16) are linearly correlated, and the error between both patterns X and Xr is calculated as D= ₁₆ 〓 ⁿ⁼¹ |xr(n)−x(n)|, and this The voice of the reference pattern with the minimum error is recognized as the input voice at this time. 7
8 is an I/O port that outputs the recognition result of this speech recognition circuit 6 to an external circuit; 8 is a recognition operation of these speech recognition circuits 6; and 8 is a second stack area M2-0 of the second memory section 5. , M2−1, M2−2, M2−
3, or the output operation at the I/O port 7, etc.
The second memory section 5, voice recognition circuit 6, I/O port 7, and second CPU ₈ constitute a second processor P2. 9 is an interface arranged between these first and second processors P _{1 and} P ₂ ;
It has the function of transmitting the characteristic pattern from P2 to the second processor _P2 , and its operation is performed by the first and second
4 and 8. As shown in FIG. 4, this interface 9 is a latch circuit that temporarily holds the characteristic pattern from the first processor _P1 .
The main components are an RA and a flip-flop FF that controls the latch operation of the latch circuit RA.

The following operation will be explained. When a voice is input to the microphone 1, the feature extraction circuit 2 extracts a time series of vector parameters x(t) representing the feature and stores it in the buffer area of the first memory unit 3.
The feature pattern X introduced into M1BUF and normalized is stored in the stack area M1-
0 at one point, and transmitted to the second processor P ₂ via the interface 9 when necessary.
At this time, if the second processor _P2 is in operation and refuses to receive the feature pattern
The feature pattern It is stored in the stack area M1-1. Thus, even if the transmission of the feature patterns to the second processor _P2 is refused, the feature patterns X, X', X'', etc. sequentially obtained by the first processor _P1 are Multiple stack areas M1-0 and M1- of the memory unit 3
1, M1-2, M1-3, and so on. Then, each time the operation of the second processor _P2 is completed, the stack area M1- of the first memory section 3 is
Each feature pattern X of 0, M1-1, M1-2, M1-3, ... is read out to the FIFO in the order in which it was stored,
a second processor via interface 9;
Sent to _P2 .

On the other hand, in the second processor _P2 , the feature pattern X obtained via the interface 9 is stored in the stack area M2-0 of the second memory section 5,
The feature pattern X is pattern-recognized based on a large number of reference patterns Xr previously stored in the reference pattern area M2PTN of the memory section 5. The recognition result is then output to an external circuit via the I/O port.

Furthermore, in a state where the I/O port is in operation and recognition processing cannot be performed, the characteristic pattern _P1
When a new feature pattern X′ is sent from
The new feature patterns X'', which are stored in M2-1 and successively sent, are sequentially stored in the stack area M2-
2, M2-3,... In this way, the stack areas M2-0 and M2- of the second memory section 5
The characteristic patterns X, . . . stored in 1, M2-2, M2-3, .

Next, the operation of the interface 9 will be explained with reference to FIG. When the characteristic pattern is set on the data bus DB from the first processor P ₁ side and transmission is possible, the processor P ₁ transmits the outgoing signal.
Output VS. The latch circuit is activated by this signal.
RA latches the characteristic pattern currently set on the data bus DB, and at the same time flip-flop FF is set. Therefore, the flip-flop FF set output Q becomes "1", which notifies the second processor _P2 that the characteristic pattern has been written into the latch circuit RA. When the processor _P2 completes receiving the feature pattern, it outputs a reception signal, erases the contents of the latch circuit RA, and at the same time resets the flip-flop FF. It notifies processor P ₁ that transmission of the next characteristic pattern is now possible _. RE is a reset signal for resetting the first processor _P1 from the second processor _P2 .

(F) Effects of the Invention As is clear from the above description, the speech recognition device of the present invention includes a first processor that extracts speech features and a second processor that performs a recognition operation. The feature extraction operation and the recognition operation are processed in parallel, and the first memory section of the first processor section is provided with a FIFO-configured stack for temporarily saving the voice feature pattern.
In addition to eliminating the waiting time in the first processor section, the third memory section of the second processor section is also provided with a FIFO-configured stack for temporarily saving audio characteristic patterns. Since data can be transferred between the first and second processors while the I/O port of the processor section is in operation and recognition processing cannot be performed, the speed of the speech recognition device can be increased.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram showing the existing speech recognition operation, FIG. 2 is a schematic diagram showing the speech recognition operation according to the present invention,
FIG. 3 is a block diagram showing the configuration of the device of the present invention, and FIG. 4 is a block diagram of its main parts, in which 2 is a feature extraction circuit, 3 is a first memory section, 4 and 8 are CPUs,
5 is a second memory section, 6 is a voice recognition circuit, 7 is an I/O port, and 9 is an interface.

Claims (1)

[Claims] 1. A microphone that converts audio into an electrical audio signal, a feature extraction circuit that extracts features of the audio signal obtained from the microphone, and an input audio signal extracted by the feature extraction circuit. A first processor section consisting of a first memory section that stores feature patterns, a first CPU that controls feature extraction operations and memory operations, and an interface circuit from the first processor section. a third memory section that stores a characteristic pattern of the input voice obtained through the second memory section; a second memory section that stores a reference pattern to be compared with the characteristic pattern of the memory section; a speech recognition circuit that compares and recognizes the reference pattern of the input speech with the characteristic pattern of the input speech; an I/O port that outputs the recognition result of the recognition circuit to an external circuit;
It is composed of a second CPU that controls the O port operation, and a second processor section consisting of a second CPU, and the transmission operation of the characteristic pattern in the above interface circuit is transmitted to each CPU of the above two processor sections. As a result, when the second processor section is in operation and refuses to receive feature patterns, the extracted feature patterns are sequentially saved in the first memory section. and the above second
When the operation of the processor unit is completed and a request is made to receive the characteristic patterns, the characteristic patterns in the first memory unit are read out in the order in which they were stored and sent to the second processor unit via the interface circuit, and the When the I/O port of the second processor section is in operation and recognition processing cannot be performed, the feature patterns transferred via the interface circuit are sequentially saved in the third memory section, A speech recognition device characterized in that when the operation of the I/O port is completed and recognition processing is possible, the characteristic patterns of the third memory section are read out in the order in which they were stored and recognition processing is performed.