JPH04223741A - Push button signal generation circuit - Google Patents

Abstract

PURPOSE:To simplify circuit constitution, to miniaturize a circuit scale and to generate the PB signal of high performance without affected by means of a lid glitch generated in a D/A conversion circuit. CONSTITUTION:When a button depression signal Si10 is inputted to a PB signal decision circuit 10, it decodes the button depression signal Si10 concerned, decides an output frequency f0 and outputs the digital signal S10 of a frequency nf0 which is n-times as much as the frequency f0 concerned to the D/A conversion circuit 20 and a switched capacitor LPF 30. The D/A conversion circuit 20 frequency-divides the digital signal S10 into 1/n, converts a frequency-divided result to the analog signal S20 of the frequency f0 and transmits it to the switched capacitor LPF 30. It outputs an analog signal S30 obtained by sampling the analog signal S20 by the digital signal S10 and removing a high frequency component.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a push button signal generation circuit (
This relates to a PB signal generation circuit (hereinafter referred to as a PB signal generation circuit).

0002

2. Description of the Related Art Generally, a push-button dial type telephone has 12 buttons arranged in 4 rows and 3 columns, and each time one of the buttons is pressed, a PB signal generation circuit generates a push-button signal ( (hereinafter referred to as a PB signal). That is, when the button is pressed, the PB signal generation circuit sends out a PB signal consisting of two audio frequency signals, a high group frequency and a low group frequency.

[0003] In this type of PB signal generation circuit, for example, signals of a plurality of frequencies can be realized using one digital/analog conversion circuit (hereinafter referred to as a D/A conversion circuit). This D/A conversion circuit divides signals of a plurality of frequencies, then converts the frequency division result into an analog signal and sends it to a telephone line.

However, when the input digital signal changes, a D/A conversion circuit may generate a very large spike called a "glitch" in the output due to the operating time difference of the internal circuit, and this may cause other There is a risk that the peripheral circuits may malfunction.

[0005] Conventionally, in order to remove such glitches, a glitch removal circuit for D/A conversion output has been proposed, for example, in Japanese Patent Laid-Open No. 61-205023.

FIG. 2 is a block diagram showing a conventional D/A conversion output glitch removal circuit described in the above-mentioned document.

This glitch removal circuit includes a D/A conversion circuit 1 that frequency-divides a digital signal Si and then converts it into an analog signal S1 and outputs a timing signal TS, and a switched capacitor low-pass filter is connected to the output side of the D/A conversion circuit 1. (hereinafter referred to as a switched capacitor LPF) 2 and a clock synchronization circuit 3 are connected.

[0008] The switched capacitor LPF2 samples the analog signal S1 containing high frequency components output from the D/A conversion circuit 1 in response to the clock signal CLK2, and outputs an analog signal S2 obtained by removing the high frequency components from the analog signal S1. It is a circuit. This analog signal S2 is sent out to the telephone line as a PB signal.

The clock synchronization circuit 3 receives a timing signal T.
S, and a clock signal C synchronized with the timing signal TS.
This circuit receives LK1 and outputs another clock signal CLK2 to the switched capacitor LPF2.

FIG. 3 is a signal waveform diagram of FIG. 2.

When a digital signal Si of a predetermined frequency generated by pressing a button is input, the D/A
The conversion circuit 1 divides the frequency of the digital signal Si, converts it into an analog signal S1, outputs the analog signal S1 to the switched capacitor LPF2, and supplies a timing signal TS as shown in FIG. 3 to the clock synchronization circuit 3. do.

The clock synchronization circuit 3 uses a timing signal TS and a clock signal C synchronized with the timing signal TS.
It receives LK1, generates a clock signal CLK2 having a lower frequency than the clock signal CLK1, and supplies it to the switched capacitor LPF2. switched capacitor LP
F2 samples the analog signal S1 using the clock signal CLK2, and sends out an analog signal S2 from which high frequency components of the analog signal S1 have been removed.

In this glitch removal circuit, since the clock signal CLK2 for operating the switched capacitor LPF2 is synchronized with the output analog signal S1 of the D/A conversion circuit 1, it is possible to remove glitches peculiar to the D/A conversion circuit. It is possible to configure a PB signal generation circuit with good performance.

[0014]

However, in the conventional PB signal generation circuit, the switched capacitor LPF2
In order to operate the clock synchronization circuit 3, the clock synchronization circuit 3 is required. Furthermore, this clock synchronization circuit 3 must newly generate a clock signal CLK2 for the switched capacitor LPF in synchronization with the timing signal TS from the D/A conversion circuit 1, which increases the complexity of the circuit configuration and the circuit structure. There was a problem in that it led to an increase in scale. In particular, P
When realizing signals of multiple frequencies with one D/A conversion circuit 1 like the B signal generation circuit, the clock synchronization circuit 3
becomes more complex.

[0015] The present invention solves the problem of the conventional PB signal generation in that outputting a plurality of signals with a D/A conversion circuit leads to a complicated circuit configuration and an enlarged circuit scale. It provides a circuit.

[0016]

[Means for Solving the Problems] FIG. 1 is a functional block diagram showing a PB signal generation circuit of the present invention.

This PB signal generation circuit decodes the button press signal Si10, which is a multi-bit digital signal, to determine the output frequency fo, and generates a digital signal with a frequency nfo that is n times the frequency fo (where n is an integer). It includes a PB signal determining circuit 10 that outputs a signal S10. This PB
A D/A conversion circuit 20 is connected to the output side of the signal determination circuit 10, and a switched capacitor L is connected to the output side of the D/A conversion circuit 20.
PF30 is connected. In addition, the PB signal determination circuit 1
0 is connected to the switched capacitor LPF30.

The D/A conversion circuit 20 converts the digital signal S
This circuit divides the frequency of 10 into 1/n and converts the frequency division result into an analog signal S20 of frequency fo. The switched capacitor LPF30 is a circuit that samples the analog signal S20 using the digital signal S10 as a sampling clock and outputs an analog signal S30 from which high frequency components have been removed.

[0019]

[Operation] According to the present invention, since the PB signal generation circuit is configured as described above, when the PB signal is generated, the button press signal Si10, which is a digital signal, is generated by pressing the button.
is input to the PB signal determining circuit 10, the PB signal determining circuit 10 decodes the pressing signal Si10, determines the frequency fo of the PB signal to be output, and uses the determined frequency f.
A digital signal S10 having a frequency nfo that is n times o is generated, and the digital signal S10 is applied to the D/A conversion circuit 20 and the switched capacitor LPF30.

[0020] The D/A conversion circuit 20 converts the digital signal S
10, the digital signal S10 is frequency-divided by 1/n, and the frequency division result is converted into an analog signal S20 of frequency fo and output to the switched capacitor LPF30. The switched capacitor LPF 30 samples the analog signal S20 from the D/A conversion circuit 20 at the timing of the digital signal S10, and generates an analog signal S from which high frequency components of the analog signal S20 have been removed.
Outputs 30. This analog signal S30 causes PB
A signal is generated and sent out onto a telephone line or the like.

In this way, since the switched capacitor LPF 30 performs sampling operation using the same signal as the digital signal S10 inputted to the D/A conversion circuit 20, a conventional clock synchronization circuit for operating the switched capacitor LPF 30 is not required. can be omitted. moreover,
The switched capacitor LPF 30 is connected to the D/A conversion circuit 2.
Since the sampling operation is performed in synchronization with 0, the D/A
Glitches generated at analog change points of the conversion circuit 20 are removed, and a high-performance analog signal S30 with little distortion can be output. Therefore, the above problem can be solved.

[0022]

[Embodiment] FIG. 4 is a schematic block diagram of a PB signal generation circuit in a push-button dial telephone according to an embodiment of the present invention. Elements common to those in FIG. 1 are designated by common reference numerals. is attached.

This PB signal generation circuit decodes the button press signal Si10, which is a 4-bit digital signal, and determines the low group frequency fl and high group frequency fh of the PB signal S40 to be output, respectively. Digital signals S10a and S1 with frequencies nfl and nfh that are n times fh
It includes a PB signal determining circuit 10 that outputs 0b. P
The output side of the B signal determination circuit 10 is connected to a low group side D/A conversion circuit 20a and a switched capacitor LPF30a, as well as a high group side D/A conversion circuit 20b and a switched capacitor LPF30b. The output sides of the switched capacitors LPF 30a, 30b are connected to an adder 40.

The PB signal determining circuit 10 includes a decoder 11 that decodes a button press signal Si10 to determine load values S11a and S11b, a frequency divider 12a on the low group side connected to the output side of the decoder 11, and a high frequency divider 12a connected to the output side of the decoder 11. It is composed of a frequency divider 12b on the group side. The frequency divider 12a on the low group side is a circuit that receives the load value S11a and generates a digital signal S10a having a frequency nfl that is n times the target low group frequency fl in synchronization with the clock signal CLK. The frequency divider 12b is
Input the load value S11b and select n of the desired high group frequency fh.
This circuit generates a digital signal S10b of twice the frequency nfh.

Of the D/A conversion circuits 20a and 20b connected to the output sides of the frequency dividers 12a and 12b, the D/A conversion circuit on the low group side
The A conversion circuit 20a includes a frequency divider 21a that divides the digital signal S10a to a target low group frequency fl, and a frequency divider 21a that converts the output of the frequency divider 21a into an analog signal to obtain the low group frequency fl.
A D/A converter 22a outputting an analog signal S20a of
It is made up of. Similarly, the high group side D/A conversion circuit 20b converts the digital signal S10b of the high group frequency fh.
A frequency divider 21b divides the frequency of the frequency to a target frequency fh, and the output of the frequency divider 21b is converted into an analog signal S2 of a high group frequency fh.
0b, and a D/A converter 22b for converting to 0b.

Switched capacitor LPF 30a connected to the output side of D/A conversion circuits 20a and 20b, respectively.
, 30b, the switched capacitor LPF on the low group side
30a has a function of removing high frequency components of the analog signal S20a using the low group side digital signal S10a as a sampling clock and outputting an analog signal S30a of the low group frequency fl. Similarly, the switched capacitor LPF30b on the high group side receives the digital signal S1 on the high group side.
Analog signal S20 using 0b as sampling clock
It has a function of removing the high frequency component of b and outputting an analog signal S30b of high group frequency fh.

The adder 40 receives the low group side analog signal S30.
a and the high group side analog signal S30b to generate a PB signal S40 consisting of 16 types of analog signals, and
It has a function of sending out the B signal S40 to the telephone line.

FIG. 5 shows the switched capacitor L in FIG.
FIG. 3 is a circuit diagram showing a configuration example of a PF 30a (30b).

Low group side switched capacitor LPF30
a and the switched capacitor LPF30b on the high group side,
They have the same circuit configuration, with capacitors 31, 32, 33,
ON/OFF by digital signal S10a (or S10b)
Analog switches 34, 35, 36, 37 that operate off
and an operational amplifier 38.

The (-) side input terminal of the operational amplifier 38 has
An analog switch 34, a capacitor 31, and an analog switch 35 are connected in series, and the operational amplifier 38
The (+) side input terminal of is connected to ground. Between the (-) side input terminal and output terminal of the operational amplifier 38,
The capacitor 33 is connected, and the capacitor 33
An analog switch 36, a capacitor 32, and an analog switch 37 are connected in parallel.

This switched capacitor LPF 30a (
or 30b) is the external digital signal S10a
(or S10b) by analog switch 34,3
5, 36, and 37 perform on/off operations periodically. For example, the digital signal S10a (or S10
b) is at “H” level, each analog switch 34
~37 becomes the state shown in FIG. 5, and the input analog signal S20a
(or S20b) is in a hold state in which it is not connected to the capacitor 31. Digital signal S10a (or S
10b) is at the "L" level, each of the analog switches 34 to 37 is switched to a connection state opposite to the state shown in FIG.

FIG. 6 is a signal waveform diagram of the digital signal S10a and the analog signal S20a when the frequency division number n=16. The operations in FIGS. 4 and 5 will be explained with reference to this figure.

The PB signal generation circuit of FIG. 4 generates one analog signal among the four frequency signals in the low group and one signal among the four frequency signals in the high group from the information of the button press signal Si10 consisting of a 4-bit digital signal. It operates to generate a PB signal S40 consisting of 16 types of analog signals by selecting the analog signals and adding each one.

That is, the 4-bit button press signal Si10
is input to the decoder 11 in the PB signal determination circuit 10, the decoder 11 decodes the button press signal Si10 to determine load values S11a and S11b, and the load values S11a and S11b are sent to the frequency divider 12a. , 12b. In the frequency divider 12a on the low group side, the clock signal C is determined by the load value S11a determined by the decoder 11.
Frequency n that is n times the target low group frequency fl in synchronization with LK
A digital signal S10a of fl is generated. Similarly, the frequency divider 12b on the high group side generates a digital signal S10b having a frequency nfh that is n times the target high group frequency fh in synchronization with the clock signal CLK using the load value S11b determined by the decoder 11. .

Here, the outputs of each frequency divider 12a, 12b are considered to have four different frequencies for each of the low group side and the high group side. When considering the frequency divider 12a on the low group side, for example, if fl=697Hz and n=16, then 697×16
= 11.152 KHz digital signal S10a is generated. This digital signal S10a has a period of 89.7 μs.

The output of the frequency divider 12a is sent to the D/A conversion circuit 2.
Frequency divider 21a and switched capacitor LPF3 in 0a
0a. Similarly, the output of frequency divider 12b is D
The signal is supplied to a frequency divider 21b and a switched capacitor LPF 30b in the /A conversion circuit 20b.

In the D/A converter 20a on the low group side, the frequency divider 21a receives the digital signal S1 from the frequency divider 12a.
0a is frequency-divided by 1/n to a target frequency fl, and the frequency division result is sent to the D/A converter 22a. The D/A converter 22a converts the output of the frequency divider 21a into an analog signal,
The analog signal S20a with a period of fl is output to the switched capacitor LPF30a. This analog signal S20
For example, if fl=697Hz, the period of a is 1/
fl=1/697=1434.7 μs. Similarly,
In the high group side D/A conversion circuit 20b, the digital signal S10b from the frequency divider 12b is divided by the frequency divider 21b,
The frequency division result is converted into an analog signal S20b of frequency fh by the D/A converter 22b, and the analog signal S20b is applied to the switched capacitor LPF 30b.

Low group side switched capacitor LPF30
In step a, as shown in FIG. 5, the analog signal S20a from the D/A converter 22a is sampled using the digital signal S10a output from the frequency divider 12a as a sampling clock.

That is, if the digital signal S10a is at "H" level, the analog signal S20a is connected to the capacitor 31.
If the digital signal S10a is at the "L" level, the analog switch 34 is turned on, the analog signal S20a is connected to the capacitor 31, and the sample state SS is entered. That is, as shown in FIG. 6, the point of change of the analog signal S20a output from the D/A converter 22a is set as the hold state HS, and the stable point after the change is set as the sample state SS.

Then, the glitch G that occurs at the change point of the analog signal S20a output from the D/A conversion circuit 20a is not input to the switched capacitor LPF 30a, so the switched capacitor LPF 30a has high performance with little distortion and The analog signal S30a from which the high frequency component of the signal S20a has been removed is output to the adder 40. That is, in the switched capacitor LPF 30a, the digital signal S10a input to the frequency divider 21a
Since the sampling operation is performed using the same signal as, distortion-free filter operation is possible.

The cutoff frequency fc of the switched capacitor LPF 30a is expressed by the following equation 1.

[0042]

[Math 1]

For example, if nfl=32×697Hz C31=C32=1, C33=3.3, then from equation 1, fc=1.5×697Hz, which is 1.5 times the target low group frequency fl=697Hz. Higher frequencies can be attenuated. The same applies when outputting other frequencies. The analog signal S3 output from such a switched capacitor LPF 30a
0a is provided to adder 40.

[0044] High group side switched capacitor LPF30
b is also the switched capacitor LPF30 on the low group side.
Similarly to a, the analog signal S20b output from the D/A converter 22b is sampled using the digital signal S10b output from the frequency divider 12b as a sampling clock, and the high frequency component of the analog signal S20b is removed. S30b is output to the adder 40.

[0045] The adder 40 adds the analog signals S30a and S30b, and adds the analog signals S30a and S30b.
A PB signal S40 is generated and the PB signal S40 is sent to the telephone line.

This embodiment has the following advantages.

(1) D/A conversion circuits 20a, 20b
In order to output analog signals S20a and S20b obtained by dividing the digital signals S10a and S10b outputted from the PB signal determining circuit 10 by 1/n, respectively,
Signals of multiple frequencies, such as the PB signal S40, are also treated as low-distortion signals by the D/A conversion circuits 20a and 20b.
You can output each from

(2) D/A conversion circuits 20a, 20b
Digital signals S10a and S10 respectively input to
Since the switched capacitors LPF30a and 30b are operated using the same signal as the sampling clock, the switched capacitors LPF30a and
In order to operate 30b, a conventional clock synchronization circuit is not required, thereby simplifying the circuit and making it possible to reduce the size of the circuit.

(3) Switched capacitor LPF3
The operations of 0a and 30b are based on the D/A conversion circuits 20a and 20b.
Since it is completely synchronized with the operation of the filter, it is possible to perform high-performance filter operation with little distortion even for signals of multiple frequencies. Moreover, this switched capacitor LPF3
0a and 30b have a function of removing glitches generated in the D/A conversion circuits 20a and 20b, so stable operation can be expected.

Note that the present invention is not limited to the embodiment shown in FIG. 4; for example, the PB signal determining circuit 10 may be configured with other circuits, the switched capacitors LPFs 30a and 30b may be configured with circuits other than those shown in FIG. 5, etc. Various modifications are possible.

[0051]

As described in detail above, according to the present invention, the switched capacitor LPF is operated using the same signal as the digital signal from the PB signal determining circuit inputted to the D/A conversion circuit as a sampling clock. Therefore, the conventional clock synchronization circuit for generating a clock for operating the switched capacitor LPF can be omitted, thereby simplifying the circuit configuration and reducing the size of the circuit.

Furthermore, since the operation of the switched capacitor LPF is always synchronized with the operation of the D/A conversion circuit,
High-performance filter operation with little distortion can be expected even for signals of multiple frequencies. Moreover, since the switched capacitor LPF can remove glitches generated in the D/A conversion circuit, stable operation can be expected.

[Brief explanation of the drawing]

FIG. 1 is a functional block diagram of a PB signal generation circuit of the present invention.

FIG. 2 is a circuit diagram of a conventional D/A conversion output glitch removal circuit.

FIG. 3 is a signal waveform diagram of FIG. 2;

FIG. 4 is a schematic block diagram of a PB signal generation circuit showing an embodiment of the present invention.

FIG. 5 is a circuit diagram of the switched capacitor LPF in FIG. 4.

FIG. 6 is a signal waveform diagram of FIG. 4;

[Explanation of symbols]

Claims (1)

[Claims] Claim 1: Decipher a button press signal to determine an output frequency fo, and multiply the frequency fo by n (where n: an integer).
a push-button signal determining circuit that outputs a digital signal with a frequency nfo; and a digital/analog conversion circuit that divides the output of the push-button signal determining circuit into 1/n and converts the frequency division result into an analog signal with a predetermined frequency. and a switched capacitor low-pass filter that samples the output of the digital/analog conversion circuit at the frequency nfo and removes high frequency components.