JPH0423345U - - Google Patents

Description

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the AMI clock generation circuit according to the present invention, FIG. 2 is a block diagram illustrating the system position of the primary group interface device in which the AMI clock generation circuit is used, and FIG. 3 4 is a block diagram showing the detailed configuration of a primary group interface device including a conventional AMI clock generation circuit, and FIG. 4 is a timing chart of each part of the above embodiment. 30...AMI clock creation circuit, 32...1/
193 frequency divider circuit, 33...OR circuit, 34...1/3 frequency divider circuit, 35...3 output frequency divider circuit, 36...unipolar/bipolar conversion circuit.

Claims (1)

[Scope of utility model registration request] In the AMI clock creation circuit that creates a 64KHz + 8KHz AMI clock signal in which a 64KHz component and an 8KHz component are synthesized from a 1.544MHz clock signal extracted from a 1.544Mbps primary group digital multiplexed signal, a 1.544MHz clock signal is generated. pulse number converting means for converting each of the 193 pulses into 192 pulses within a period including the 193 pulses; and a pulse signal output from the pulse number converting means. A frequency dividing means that divides the frequency to form a plurality of pulse signals with different frequency division ratios, and a logical operation on the plurality of pulse signals output from the frequency dividing means to specify the positive and negative periods of the AMI clock signal. After forming two pulse signals, 64KHz+8K based on these pulse signals
Unipolar/Creating HzAMI clock signal
An AMI clock generation circuit characterized by comprising bipolar conversion means.