JPH04234149A - Forming method of semiconductor device multilayer interconnection interlaminar insulating film - Google Patents
Forming method of semiconductor device multilayer interconnection interlaminar insulating filmInfo
- Publication number
- JPH04234149A JPH04234149A JP41846490A JP41846490A JPH04234149A JP H04234149 A JPH04234149 A JP H04234149A JP 41846490 A JP41846490 A JP 41846490A JP 41846490 A JP41846490 A JP 41846490A JP H04234149 A JPH04234149 A JP H04234149A
- Authority
- JP
- Japan
- Prior art keywords
- spin
- insulating film
- film
- forming
- glass film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 22
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 239000011521 glass Substances 0.000 claims abstract description 28
- 239000011737 fluorine Substances 0.000 claims abstract description 10
- 229910052731 fluorine Inorganic materials 0.000 claims abstract description 10
- 238000004544 sputter deposition Methods 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 8
- -1 fluorine ions Chemical class 0.000 claims abstract description 5
- 238000005468 ion implantation Methods 0.000 claims abstract description 4
- 238000004528 spin coating Methods 0.000 claims abstract description 4
- 125000000217 alkyl group Chemical group 0.000 claims abstract description 3
- SCPYDCQAZCOKTP-UHFFFAOYSA-N silanol Chemical compound [SiH3]O SCPYDCQAZCOKTP-UHFFFAOYSA-N 0.000 claims abstract description 3
- 239000011229 interlayer Substances 0.000 claims description 14
- 239000010410 layer Substances 0.000 claims description 13
- 238000010438 heat treatment Methods 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 229910007156 Si(OH)4 Inorganic materials 0.000 claims description 2
- 239000004020 conductor Substances 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 12
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 11
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 239000000126 substance Substances 0.000 abstract description 4
- 229920000642 polymer Polymers 0.000 abstract description 2
- RMAQACBXLXPBSY-UHFFFAOYSA-N silicic acid Chemical compound O[Si](O)(O)O RMAQACBXLXPBSY-UHFFFAOYSA-N 0.000 abstract 1
- 229910052782 aluminium Inorganic materials 0.000 description 11
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 11
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 5
- WTEOIRVLGSZEPR-UHFFFAOYSA-N boron trifluoride Chemical compound FB(F)F WTEOIRVLGSZEPR-UHFFFAOYSA-N 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910015900 BF3 Inorganic materials 0.000 description 2
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910001873 dinitrogen Inorganic materials 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 235000019441 ethanol Nutrition 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は半導体装置の製造方法に
関し、特に多層配線層間絶縁膜の形成方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a multilayer wiring interlayer insulating film.
【０００２】0002
【従来の技術】従来、この種の多層配線層間絶縁膜は、
以下のように形成されていた。すなわち、図２に示すよ
うに、半導体基板２０１上に第１層目のＡｌ配線層２０
２を形成した後、第１の層間絶縁膜（ＣＶＤ−ＳｉＯ２
膜）２０３，スピンオングラス膜２０４，第２の層間絶
縁膜２０５を順次形成し、３層構造の絶縁膜を層間絶縁
膜として用いる。次に、所定の位置に開孔を形成した後
、第２層目のＡｌ配線層２０６を形成する。以上の方法
によって２層アルミニウム配線構造体が形成される（特
開昭５７−１００７４８号参照）。[Prior Art] Conventionally, this type of multilayer wiring interlayer insulating film is
It was formed as follows. That is, as shown in FIG. 2, a first Al wiring layer 20 is formed on a semiconductor substrate 201.
2, a first interlayer insulating film (CVD-SiO2
A film) 203, a spin-on glass film 204, and a second interlayer insulating film 205 are sequentially formed, and the three-layer insulating film is used as the interlayer insulating film. Next, after forming an opening at a predetermined position, a second Al wiring layer 206 is formed. A two-layer aluminum wiring structure is formed by the above method (see Japanese Patent Laid-Open No. 100748/1983).
【０００３】0003
【発明が解決しようとする課題】上述した従来の多層配
線層間絶縁膜の形成方法は以下のような問題点があった
。すなわち、従来のスピンオングラス膜は凹凸の大きい
半導体基板上に、０．２μｍ以上の厚さに形成すると、
３００℃以上の熱処理時の体積収縮により、亀裂が生じ
てしまうために、厚膜を形成することが難しく、したが
って充分平坦な層間絶縁膜の形成が難しい。SUMMARY OF THE INVENTION The above-described conventional method for forming a multilayer wiring interlayer insulating film has the following problems. That is, when a conventional spin-on glass film is formed to a thickness of 0.2 μm or more on a highly uneven semiconductor substrate,
Because cracks occur due to volumetric shrinkage during heat treatment at 300° C. or higher, it is difficult to form a thick film, and therefore it is difficult to form a sufficiently flat interlayer insulating film.
【０００４】さらに、従来のスピンオングラス膜は吸湿
性が高いことが知られており、第２層目の配線層を形成
するための金属膜スパッタ時にスピンオングラス膜に含
有された水分が、スルーホール側壁のスピンオングラス
膜から放出され、スルーホール底部の第１層目配線の表
面を酸化してしまい、電気的導通をとることが難しい。Furthermore, it is known that conventional spin-on glass films are highly hygroscopic, and water contained in the spin-on glass film during metal film sputtering to form the second wiring layer is absorbed into the through-holes. It is emitted from the spin-on glass film on the sidewall and oxidizes the surface of the first layer wiring at the bottom of the through hole, making it difficult to establish electrical continuity.
【０００５】また、従来のスピンオングラス膜は３００
〜４００℃の低温で焼成した場合には、その膜質が悪い
ために電気的特性に劣るという欠点がある。[0005] Furthermore, the conventional spin-on glass film has a thickness of 300
When fired at a low temperature of ~400°C, there is a drawback that the electrical properties are poor due to poor film quality.
【０００６】本発明の目的は、前記目的を解消した半導
体装置の多層配線層間絶縁膜の形成方法を提供すること
にある。An object of the present invention is to provide a method for forming a multilayer wiring interlayer insulating film for a semiconductor device, which solves the above-mentioned object.
【０００７】[0007]
【課題を解決するための手段】前記目的を達成するため
、本発明に係る半導体装置の多層配線層間絶縁膜の形成
方法においては、第１の導体層が形成された半導体基板
上に化学気相成長法又はスパッタ法により第１の絶縁膜
を形成する工程と、シラノール（Ｓｉ（ＯＨ）４）又は
、アルコキシシラン（Ｓｉ（ＯＲ）４，Ｒ：アルキル基
）のうち少なくとも１つからなる集合体を主成分とする
溶液をスピンコート法によってスピンオングラス膜を形
成する工程と、２００℃以下の温度で熱処理せしめる工
程と、イオン注入法によって該スピンオングラス膜中に
フッ素イオンを注入せしめる工程と、３００〜４５０℃
の温度で熱処理せしめる工程と、化学気相成長法又は、
スパッタ法により第２の絶縁膜を形成する工程とを有す
るものである。[Means for Solving the Problems] In order to achieve the above object, in the method for forming a multilayer wiring interlayer insulating film of a semiconductor device according to the present invention, a chemical vapor phase is applied to a semiconductor substrate on which a first conductor layer is formed. A step of forming a first insulating film by a growth method or a sputtering method, and an aggregate consisting of at least one of silanol (Si(OH)4) or alkoxysilane (Si(OR)4, R: alkyl group) a step of forming a spin-on glass film by a spin coating method with a solution containing as a main component, a step of heat treatment at a temperature of 200° C. or less, a step of implanting fluorine ions into the spin-on glass film by an ion implantation method, ~450℃
a step of heat treatment at a temperature of
The method includes a step of forming a second insulating film by a sputtering method.
【０００８】[0008]
【作用】スピンオングラス膜にフッ素を含有させること
によって、亀裂を発生させることなく厚いスピンオング
ラス膜を形成する。また、スピンオングラス膜中にフッ
素を含有させることにより、吸湿量を抑える。[Operation] By incorporating fluorine into the spin-on glass film, a thick spin-on glass film can be formed without generating cracks. Furthermore, by incorporating fluorine into the spin-on glass film, the amount of moisture absorption is suppressed.
【０００９】[0009]
【実施例】次に、本発明について図面を参照して説明す
る。本実施例では、テトラエトキシシラン（化学式Ｓｉ
（ＯＣ２Ｈ５）４）の重合体を主成分として用い、溶媒
としてエチルアルコールを用いた。溶液中の固形分濃度
は１２重量％とした。図１は、本発明に基づく実施例で
ある２層アルミニウム配線構造体に用いる層間絶縁膜の
形成方法を示す工程断面図である。図１（ａ）に示すよ
うに、シリコン酸化膜１０２を介して厚さ約１μｍの第
１のアルミニウム配線１０３が形成された半導体基板１
０１上に、同図（ｂ）に示すように厚さ約０．３μｍの
プラズマ化学気相成長シリコン酸化膜１０４を形成する
。
次に本発明に基づく塗布溶液を４０００回転で２０秒間
，回転塗布法により塗布し、１５０℃の温度で、窒素ガ
ス雰囲気のオーブン内で３０分間ベークし、約０．４５
μｍのスピンオングラス膜１０５を形成する（図１（ｃ
））。次に同図（ｄ）に示すように、イオンソースとし
て３フッ化ホウ素（ＢＦ３）を用い、エネルギー１５０
ＫｅＶ，注入量５×１０１６／ｃｍ２なる条件でフッ素
イオン（Ｆ（プラス））を該スピンオングラス膜中に注
入した後、４００℃の温度で３０分間、窒素ガス雰囲気
の電気炉内で焼成し、厚さ約０．４μｍのフッ素含有ス
ピンオングラス膜を形成する。続いて、同図（ｅ）に示
すように、厚さ約０．４μｍの第２のプラズマ化学気相
成長シリコン酸化膜１０６を形成する。上記の（ｂ）〜
（ｅ）の工程によって、層間絶縁膜が形成される。次に
、同図（ｆ）に示すようにスルーホール１０７を形成し
た後、第２のアルミニウム配線１０８を形成する。以上
の工程によって同図（ｇ）に示すように２層アルミニウ
ム配線が形成される。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. In this example, tetraethoxysilane (chemical formula Si
The polymer of (OC2H5)4) was used as the main component, and ethyl alcohol was used as the solvent. The solid content concentration in the solution was 12% by weight. FIG. 1 is a process cross-sectional view showing a method for forming an interlayer insulating film used in a two-layer aluminum wiring structure according to an embodiment of the present invention. As shown in FIG. 1(a), a semiconductor substrate 1 on which a first aluminum wiring 103 with a thickness of approximately 1 μm is formed through a silicon oxide film 102.
A plasma enhanced chemical vapor deposition silicon oxide film 104 having a thickness of approximately 0.3 μm is formed on the silicon oxide film 104, as shown in FIG. 1B. Next, the coating solution according to the present invention was applied by a spin coating method at 4000 rpm for 20 seconds, and baked at a temperature of 150° C. for 30 minutes in an oven in a nitrogen gas atmosphere.
A spin-on glass film 105 of μm thickness is formed (FIG. 1(c)
)). Next, as shown in the same figure (d), using boron trifluoride (BF3) as an ion source,
After injecting fluorine ions (F (plus)) into the spin-on glass film under the conditions of KeV and an injection amount of 5 x 1016/cm2, it was fired in an electric furnace in a nitrogen gas atmosphere at a temperature of 400 ° C. for 30 minutes, A fluorine-containing spin-on glass film having a thickness of about 0.4 μm is formed. Subsequently, as shown in FIG. 4(e), a second plasma enhanced chemical vapor deposition silicon oxide film 106 having a thickness of approximately 0.4 μm is formed. (b) above
In step (e), an interlayer insulating film is formed. Next, as shown in FIG. 3(f), after forming a through hole 107, a second aluminum wiring 108 is formed. Through the above steps, a two-layer aluminum wiring is formed as shown in FIG. 3(g).
【００１０】形成した２層アルミニウム配線において、
層間絶縁膜、特にスピンオングラス膜に亀裂の発生は全
くないものであった。また、直径１μｍのスルーホール
の接続抵抗は、１個当り約１２０ｍΩ（配線抵抗を含む
）であり、従来法で形成した場合の接続抵抗（１５０〜
２００ｍΩ）に比べて小さいものであった。また、歩留
りについては、従来法で形成した場合に比べて３０％以
上大きいものであった。In the formed two-layer aluminum wiring,
There were no cracks in the interlayer insulating film, especially in the spin-on glass film. In addition, the connection resistance of a through hole with a diameter of 1 μm is approximately 120 mΩ (including wiring resistance) per hole, and the connection resistance when formed using the conventional method (150 mΩ to 1 μm).
200 mΩ). Furthermore, the yield was 30% or more higher than that when formed by the conventional method.
【００１１】また、シリコン基板上に本発明に基づく厚
さ約０．４μｍのスピンオングラス膜を同様な方法で形
成し、面積１ｍｍ２のアルミニウム電極を形成し、電気
的特性を調べた。本発明に基づくスピンオングラス膜の
リーク電流密度は、５Ｖ印加時に、約５×１０−９Ａ／
ｃｍ２であり、これは、従来のスピンオングラス膜のリ
ーク電流密度（約１×１０−６Ａ／ｃｍ２）よりも２桁
以上小さいものであった。Further, a spin-on glass film of about 0.4 μm in thickness based on the present invention was formed on a silicon substrate by the same method, and an aluminum electrode with an area of 1 mm 2 was formed, and the electrical characteristics were investigated. The leakage current density of the spin-on glass film based on the present invention is approximately 5 x 10-9A/ when 5V is applied.
cm2, which was more than two orders of magnitude smaller than the leakage current density (about 1 x 10-6 A/cm2) of a conventional spin-on glass film.
【００１２】本実施例では、配線材料としてアルミニウ
ムを用いているが、アルミニウム合金，タングステン，
モリブデン，金，銅，金属シリサイド、又はポリシリコ
ンあるいはこれらの組合せによる配線でも良い。In this example, aluminum is used as the wiring material, but aluminum alloy, tungsten,
Wiring may be made of molybdenum, gold, copper, metal silicide, polysilicon, or a combination thereof.
【００１３】また、本発明に基づくスピンオングラス膜
の上下層には、プラズマ化学気相成長シリコン酸化膜を
形成しているが、これらは化学気相成長法によるシリコ
ン窒化膜，シリコン酸化窒化膜、あるいはスパッタ法に
よるシリコン酸化膜，シリコン窒化膜，シリコン酸化窒
化膜、あるいはこれらの組合せによる絶縁膜でもよい。Furthermore, the upper and lower layers of the spin-on glass film according to the present invention are formed with silicon oxide films grown by plasma chemical vapor deposition, but these are silicon nitride films, silicon oxynitride films, and Alternatively, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a combination thereof may be used as an insulating film formed by sputtering.
【００１４】また、イオン注入で用いるイオンソースと
しては、フッ素イオン，Ｆ（プラス）あるいはＦ２（プ
ラス）を生成するものであれば何でも良く、注入エネル
ギー，注入量についてはスピンオングラス膜の厚さに応
じて変化させることができる。The ion source used for ion implantation may be any source as long as it generates fluorine ions, F (plus) or F2 (plus), and the implantation energy and amount will depend on the thickness of the spin-on glass film. It can be changed accordingly.
【００１５】[0015]
【発明の効果】以上説明したように本発明は、フッ素を
含有せしめることによって亀裂の発生なしに厚いスピン
オングラス膜の形成が可能となり、層間絶縁膜の平坦性
は著しく改善され、多層化が容易となるという効果を有
している。さらに、スピンオングラス膜中にフッ素を含
有せしめることによって、吸湿量を著しく抑えることが
できることから、スルーホール抵抗，歩留りともに向上
せしめることができ、高信頼性を有する多層配線構造体
の形成が可能となる。また、電気的にも、絶縁性の高い
スピンオングラス膜の形成が可能となる。したがって、
本発明は多層配線構造体を有する半導体装置の製造及び
歩留り・信頼性の向上に寄与できる。[Effects of the Invention] As explained above, the present invention makes it possible to form a thick spin-on glass film without cracking by containing fluorine, and the flatness of the interlayer insulating film is significantly improved, making multilayering easier. It has the effect that Furthermore, by incorporating fluorine into the spin-on glass film, the amount of moisture absorbed can be significantly suppressed, which improves both through-hole resistance and yield, making it possible to form highly reliable multilayer wiring structures. Become. Furthermore, electrically, it is possible to form a highly insulating spin-on glass film. therefore,
INDUSTRIAL APPLICATION This invention can contribute to the manufacture of the semiconductor device which has a multilayer wiring structure, and improvement of a yield and reliability.
【図１】本発明の実施例を示す工程断面図である。FIG. 1 is a process sectional view showing an embodiment of the present invention.
【図２】従来の多層配線構造体の製造方法によって形成
した２層アルミニウム配線構造体の断面図である。FIG. 2 is a cross-sectional view of a two-layer aluminum wiring structure formed by a conventional method for manufacturing a multilayer wiring structure.
１０１ 半導体基板
１０２ シリコン酸化膜
１０３ 第１のアルミニウム配線
１０４ 第１のプラズマ化学気相成長シリコン酸化膜
１０５ 本発明のスピンオングラス膜１０６ 第２
のプラズマ化学気相成長シリコン酸化膜１０７ スル
ーホール
１０８ 第２のアルミニウム配線101 Semiconductor substrate 102 Silicon oxide film 103 First aluminum wiring 104 First plasma enhanced chemical vapor deposition silicon oxide film 105 Spin-on glass film 106 of the present invention Second
Plasma chemical vapor deposition silicon oxide film 107 Through hole 108 Second aluminum wiring
Claims (1)
上に化学気相成長法又はスパッタ法により第１の絶縁膜
を形成する工程と、シラノール（Ｓｉ（ＯＨ）４）又は
、アルコキシシラン（Ｓｉ（ＯＲ）４，Ｒ：アルキル基
）のうち少なくとも１つからなる集合体を主成分とする
溶液をスピンコート法によってスピンオングラス膜を形
成する工程と、２００℃以下の温度で熱処理せしめる工
程と、イオン注入法によって該スピンオングラス膜中に
フッ素イオンを注入せしめる工程と、３００〜４５０℃
の温度で熱処理せしめる工程と、化学気相成長法又は、
スパッタ法により第２の絶縁膜を形成する工程とを有す
ることを特徴とする半導体装置の多層配線層間絶縁膜の
形成方法。1. A step of forming a first insulating film by chemical vapor deposition or sputtering on a semiconductor substrate on which a first conductor layer is formed, and a step of forming a first insulating film using silanol (Si(OH)4) or alkoxysilane. (Si(OR)4, R: alkyl group) A step of forming a spin-on glass film by a spin coating method with a solution mainly composed of an aggregate consisting of at least one of them; and a step of heat-treating at a temperature of 200°C or less. a step of implanting fluorine ions into the spin-on glass film by an ion implantation method;
a step of heat treatment at a temperature of
1. A method for forming a multilayer wiring interlayer insulating film for a semiconductor device, comprising the step of forming a second insulating film by a sputtering method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP41846490A JPH04234149A (en) | 1990-12-28 | 1990-12-28 | Forming method of semiconductor device multilayer interconnection interlaminar insulating film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP41846490A JPH04234149A (en) | 1990-12-28 | 1990-12-28 | Forming method of semiconductor device multilayer interconnection interlaminar insulating film |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04234149A true JPH04234149A (en) | 1992-08-21 |
Family
ID=18526300
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP41846490A Pending JPH04234149A (en) | 1990-12-28 | 1990-12-28 | Forming method of semiconductor device multilayer interconnection interlaminar insulating film |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04234149A (en) |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6177343B1 (en) | 1995-09-14 | 2001-01-23 | Sanyo Electric Co., Ltd. | Process for producing semiconductor devices including an insulating layer with an impurity |
| US6214749B1 (en) | 1994-09-14 | 2001-04-10 | Sanyo Electric Co., Ltd. | Process for producing semiconductor devices |
| US6235648B1 (en) | 1997-09-26 | 2001-05-22 | Sanyo Electric Co., Ltd. | Semiconductor device including insulation film and fabrication method thereof |
| US6288438B1 (en) | 1996-09-06 | 2001-09-11 | Sanyo Electric Co., Ltd. | Semiconductor device including insulation film and fabrication method thereof |
| US6326318B1 (en) | 1995-09-14 | 2001-12-04 | Sanyo Electric Co., Ltd. | Process for producing semiconductor devices including an insulating layer with an impurity |
| JP2002136878A (en) * | 2000-10-31 | 2002-05-14 | Japan Atom Energy Res Inst | Photocatalytic materials doped with nonmetallic impurities and their preparation |
| US6617240B2 (en) | 1999-12-27 | 2003-09-09 | Sanyo Electric Co., Ltd. | Method of fabricating semiconductor device |
| US6690084B1 (en) | 1997-09-26 | 2004-02-10 | Sanyo Electric Co., Ltd. | Semiconductor device including insulation film and fabrication method thereof |
| US6794283B2 (en) | 1998-05-29 | 2004-09-21 | Sanyo Electric Co., Ltd. | Semiconductor device and fabrication method thereof |
| US6825132B1 (en) | 1996-02-29 | 2004-11-30 | Sanyo Electric Co., Ltd. | Manufacturing method of semiconductor device including an insulation film on a conductive layer |
| US6831015B1 (en) | 1996-08-30 | 2004-12-14 | Sanyo Electric Co., Ltd. | Fabrication method of semiconductor device and abrasive liquid used therein |
| US6917110B2 (en) | 2001-12-07 | 2005-07-12 | Sanyo Electric Co., Ltd. | Semiconductor device comprising an interconnect structure with a modified low dielectric insulation layer |
-
1990
- 1990-12-28 JP JP41846490A patent/JPH04234149A/en active Pending
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6214749B1 (en) | 1994-09-14 | 2001-04-10 | Sanyo Electric Co., Ltd. | Process for producing semiconductor devices |
| US6177343B1 (en) | 1995-09-14 | 2001-01-23 | Sanyo Electric Co., Ltd. | Process for producing semiconductor devices including an insulating layer with an impurity |
| US6268657B1 (en) | 1995-09-14 | 2001-07-31 | Sanyo Electric Co., Ltd. | Semiconductor devices and an insulating layer with an impurity |
| US6326318B1 (en) | 1995-09-14 | 2001-12-04 | Sanyo Electric Co., Ltd. | Process for producing semiconductor devices including an insulating layer with an impurity |
| US6825132B1 (en) | 1996-02-29 | 2004-11-30 | Sanyo Electric Co., Ltd. | Manufacturing method of semiconductor device including an insulation film on a conductive layer |
| US6831015B1 (en) | 1996-08-30 | 2004-12-14 | Sanyo Electric Co., Ltd. | Fabrication method of semiconductor device and abrasive liquid used therein |
| US6288438B1 (en) | 1996-09-06 | 2001-09-11 | Sanyo Electric Co., Ltd. | Semiconductor device including insulation film and fabrication method thereof |
| US6235648B1 (en) | 1997-09-26 | 2001-05-22 | Sanyo Electric Co., Ltd. | Semiconductor device including insulation film and fabrication method thereof |
| US6690084B1 (en) | 1997-09-26 | 2004-02-10 | Sanyo Electric Co., Ltd. | Semiconductor device including insulation film and fabrication method thereof |
| US6794283B2 (en) | 1998-05-29 | 2004-09-21 | Sanyo Electric Co., Ltd. | Semiconductor device and fabrication method thereof |
| US6617240B2 (en) | 1999-12-27 | 2003-09-09 | Sanyo Electric Co., Ltd. | Method of fabricating semiconductor device |
| JP2002136878A (en) * | 2000-10-31 | 2002-05-14 | Japan Atom Energy Res Inst | Photocatalytic materials doped with nonmetallic impurities and their preparation |
| US6917110B2 (en) | 2001-12-07 | 2005-07-12 | Sanyo Electric Co., Ltd. | Semiconductor device comprising an interconnect structure with a modified low dielectric insulation layer |
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