JPH0423427B2 - - Google Patents

Info

Publication number
JPH0423427B2
JPH0423427B2 JP56077652A JP7765281A JPH0423427B2 JP H0423427 B2 JPH0423427 B2 JP H0423427B2 JP 56077652 A JP56077652 A JP 56077652A JP 7765281 A JP7765281 A JP 7765281A JP H0423427 B2 JPH0423427 B2 JP H0423427B2
Authority
JP
Japan
Prior art keywords
substrate
diode
conductivity type
semiconductor substrate
junction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP56077652A
Other languages
English (en)
Japanese (ja)
Other versions
JPS57193054A (en
Inventor
Atsushi Oritani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56077652A priority Critical patent/JPS57193054A/ja
Publication of JPS57193054A publication Critical patent/JPS57193054A/ja
Publication of JPH0423427B2 publication Critical patent/JPH0423427B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/211—Design considerations for internal polarisation
    • H10D89/213—Design considerations for internal polarisation in field-effect devices
    • H10D89/215—Design considerations for internal polarisation in field-effect devices comprising arrangements for charge pumping or biasing substrates

Landscapes

  • Static Random-Access Memory (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP56077652A 1981-05-22 1981-05-22 Substrate bias generating circuit Granted JPS57193054A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56077652A JPS57193054A (en) 1981-05-22 1981-05-22 Substrate bias generating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56077652A JPS57193054A (en) 1981-05-22 1981-05-22 Substrate bias generating circuit

Publications (2)

Publication Number Publication Date
JPS57193054A JPS57193054A (en) 1982-11-27
JPH0423427B2 true JPH0423427B2 (th) 1992-04-22

Family

ID=13639817

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56077652A Granted JPS57193054A (en) 1981-05-22 1981-05-22 Substrate bias generating circuit

Country Status (1)

Country Link
JP (1) JPS57193054A (th)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL8701278A (nl) * 1987-05-29 1988-12-16 Philips Nv Geintegreerde cmos-schakeling met een substraatvoorspanningsgenerator.
JP2024101650A (ja) * 2023-01-18 2024-07-30 セイコーエプソン株式会社 ダイオード回路及び回路装置

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5950224B2 (ja) * 1978-10-30 1984-12-07 富士通株式会社 半導体装置

Also Published As

Publication number Publication date
JPS57193054A (en) 1982-11-27

Similar Documents

Publication Publication Date Title
US4327368A (en) CMOS Transistor pair with reverse biased substrate to prevent latch-up
US4591738A (en) Charge pumping circuit
JP3128262B2 (ja) 半導体集積回路装置
KR920001732A (ko) 반도체 기억장치
US4670669A (en) Charge pumping structure for a substrate bias generator
JP2528794B2 (ja) ラツチアツプ保護回路付き集積回路
US6075720A (en) Memory cell for DRAM embedded in logic
KR950020709A (ko) 소프트에러가 감소된 메모리셀 및 메모리장치와 소프트에러의 감소방법
US4740715A (en) Self substrate bias generator formed in a well
CA1275457C (en) Integrated circuit in complementary circuit technology comprising a substrate bias generator
US5844837A (en) Static memory device including supplemental gate capacitance
JPS6050066B2 (ja) Mos半導体集積回路装置
JPS63279491A (ja) 半導体ダイナミツクram
US4320409A (en) Complementary field-effect transistor integrated circuit device
US5877051A (en) Methods of reducing alpha particle inflicted damage to SRAM cells, methods of forming integrated circuitry, and methods of forming SRAM cells
KR0136595B1 (ko) 상보형 mos 회로기술을 이용한 래치업 방지회로를 가진 집적회로
JPH03232269A (ja) 半導体装置の入力回路
JP2968836B2 (ja) 半導体基板電位発生回路
JPH044755B2 (th)
JP2503707B2 (ja) 半導体記憶装置
JPH09102609A (ja) 半導体装置
US7170816B2 (en) Method and apparatus for passing charge from word lines during manufacture
US6589834B1 (en) Semiconductor chip that isolates DRAM cells from the peripheral circuitry and reduces the cell leakage current
JP2569004B2 (ja) 半導体集積回路装置
KR0179819B1 (ko) 반도체장치의 입력보호회로