JPH0423462A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To simplify processes by a method wherein a side wall spacer is formed of PSG, phosphorus is doped by thermal diffusion and thereby an n<-> region of an N-channel part is formed. CONSTITUTION:On the occasion when an N-channel transistor is made to be LDD(Lightly-Doped-Drain), BF2 is ion-implanted in a P<+> region 9 and an oxide film being thicker than an n<+> region 14 is formed in the P<+> region by accelerated oxidation by F (fluorine) of the BF2. Thereafter the oxide film is removed only from the n<+> region 14, a side wall 10 doped with phosphorus is formed, annealing is executed so as to diffuse the phosphorus only in an N-channel part, and thereby an n<-> region 12 is formed. By this method, a photolithographic process for forming the n<-> region and a process of implantation of the phosphorus of n<-> can be curtailed and thus manufacturing processes can be shortened and simplified.

Description

Detailed Description of the Invention (Industrial Application Field) This invention relates to an N-channel L in a CMOS type semiconductor device.
D D (Light-Doped-Dorain)
) A method of manufacturing a transistor and a single-drain type P-channel transistor.

(Prior Art) Conventionally, in a manufacturing method of this type of semiconductor device, after forming gate electrodes of N-channel and P-channel transistors, a P-channel region is formed when forming an n-layer in order to obtain an LDD structure of the N-channel transistor. Masked with a resist using normal photolithography techniques, the n-
After that, sidewall spacers were formed, photolithography was performed again to mask the P channel region, and ion implantation was performed to form an n+ layer.

(Problems to be Solved by the Invention) However, in the conventional manufacturing method described above, a photolithography process is required to form the N- region of the N-channel transistor portion, making the manufacturing process complicated. The present invention provides a semiconductor device manufacturing method that simplifies the process by eliminating the photolithography process for forming the N-91 region that is required when converting the N-channel transistor into an LDD in the CMO5 type semiconductor device described above. The purpose is to

(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention uses N-channel transistors in an LDD in manufacturing a CMOS type semiconductor device.
When converting, BF is ion-implanted into the p + bfj region, and the P″ region n″ is
Form an oxide film that is thicker than the N-channel region, then remove the oxide film only in the n'' region, form sidewalls doped with phosphorus, perform annealing, and diffuse phosphorus only in the N-channel region to form the n-region. This is what I did.

(Function) Since the present invention employs the manufacturing method as described above, when manufacturing a CMOS type semiconductor device, the photolithography process for forming the n-61 region and the n-phosphorus implantation process can be reduced.
The manufacturing process can be shortened and simplified.

(Example) FIGS. 1(a) to 1(a) are schematic cross-sectional views of steps in an example of the present invention. In FIG. 1(a), reference numeral 1 denotes a single-crystal P-type silicon (Si) substrate, and first, an N-well layer 2 is formed on this silicon substrate 1 using the usual photolithography technique, ion implantation, and annealing. Thereafter, a field oxide film 3 is formed to isolate the elements by a conventional selective oxidation method. Next, an oxide film (SiO
□) 4 is formed by thermal oxidation to about 100 to 300 A. After that, the polysilicon film 5, which will become the gate electrode, is
The polysilicon film 5 is formed by a low pressure CVD method, and impurities such as phosphorus are added by thermal diffusion or ion implantation to reduce the resistance of the polysilicon film 5 by 3×10” to 6×
After doping to a high concentration of about 1020c, the gate electrode 4 is patterned by conventional photolithography and etching using a resist as a mask.Then, as shown in FIG. Silicon substrate 1 is thermally oxidized to prevent channeling during implantation.
An oxide film 6 having a thickness of about 0.00 to 300.00 is formed, and a resist 7 is formed on the N channel portion using a normal photolithography technique. Using this resist 7, field oxide film 3, and gate electrode 5 as masks, BF2 was applied at 1×10'5 to 5×1.
Ion implantation is performed at a dose of about 0.1 cm -2 and an energy of 30 to 40 keV. After the resist 7 is removed, the oxide film 6 for preventing channeling is removed using an enchantment such as dilute hydrofluoric acid.

Next, as shown in FIG. 1C, an oxide film 8 is formed on the entire surface of the silicon substrate under conditions of oxidation of 200 to 400 times. At this time, in the P channel source/drain part,
Since BF2 is ion-implanted, 500 to 800 oxide films are formed for 200 to 400 N channel source/drain regions by accelerated oxidation using F (fluorine). Further, since the gate electrode portion is a polysilicon film, an oxide film of 500 to 800 A is formed on the gate electrode. At the same time, a P' diffusion layer 9 is formed by this oxidation heat treatment.

Next, dilute hydrofluoric acid or the like is used to remove the oxide film 8 on the N-channel source/drain portion under conditions such that the oxide film 8 is just removed. At this time, 300 to 400
The human oxide film 8 remains.

Next, the PSC film that will become the sidewall spacer-10 is
Formed by VD method. PSC at this time.

The phosphorus concentration in the film is adjusted so that the phosphorus concentration in the n-layer is approximately I x 10 l8 cm-3 after the entire thermal history, but for boat fishing it is adjusted to 1 x 1018 cm''3 to 1 x 1
It is determined in the range of 0I1019'. Next, Figure 1(d)
As shown in FIG. 1, sidewall spacers 10 are formed using ordinary RIE (reactive ion etching). At this time, in the N channel part, the PSG sidewall spacer 10 is directly connected to the silicon substrate, whereas in the P channel part, the thermal oxide film 8 is sandwiched between the PSG sidewall spacer 10 and the silicon substrate.

Next, as shown in FIG. 1(e), an oxide film 11 is formed to prevent channeling in the subsequent ion implantation, and the PSG
200-300A on the silicon substrate for the purpose of diffusing phosphorus from the sidewall spacer 10 into the n-region.
Oxidation is performed under the conditions used to form the oxide film 11.

The oxidation concentration at this time is 900 to 100, taking into account the diffusion of phosphorus from the sidewall spacer 10 of the PSG film.
Oxidation is performed at 0°C.

In this oxidation heat treatment, the lower part of the N-channel sidewall spacer 10 is a silicon substrate, and phosphorus is diffused from the sidewall spacer 10 into the silicon substrate.
- forming region 12; On the other hand, since there is a thermal oxide film 8 between the P channel sidewall spacer 10 and the silicon substrate 1, phosphorus in the sidewall spacer 10 does not diffuse into the silicon substrate. Next, a resist 13 is formed on the P channel portion using a normal photolithography technique. Using the resist 13, field oxide film 3, gate electrode 5, and sidewall spacer 10 as masks, arsenic was applied to
By implanting m payons and performing annealing at 900° C., an n″′ region 14 shown in FIG. 1(f) is formed.

Although not shown here, after forming an intermediate insulating film, forming a contact hole, forming a metal wiring, and forming a final protective film, a semiconductor device with a CMOS structure having N-channel and P-channel transistors on the same substrate is produced. is completed.

(Effects of the Invention) As described above in detail, according to the present invention, ion implantation of BF2 into the source and drain portions of the P channel region, accelerated oxidation phenomenon caused by F, and formation of sidewall spacers by PSG are performed. By doping phosphorus from this PSG by thermal diffusion to form the n-region of the N channel part, the process steps of photolithography to form an n-pW region and ion implantation of n phosphorus are reduced. can do.

[Brief explanation of the drawing]

FIG. 1 is a process sectional view of the present invention. ■...P-type Si substrate, 2...N well layer, 3...
Field oxide film, 4, 6, 8.11...Oxide film (S
iOz), 5... Polysilicon film, 7.13... Resist, 9... P'' diffusion layer, 10... PSG sidewall, 12... N- region, 14... N'' region

Claims (1)

[Claims] A method for manufacturing a CMOS semiconductor device having an LDD type N-channel transistor and a single-drain type P-channel transistor, comprising: a) forming a P^+ layer by ion implantation of BF_2 after forming a gate electrode; b) BF only on the P^+ layer by the BF_2 ion implantation;
c) removing the oxide film on the n^+ layer other than on the P^+ layer or the oxide film on the n^+ layer with dilute hydrofluoric acid; At this time, a step of leaving an oxide film on the P^+ layer, d) a step of forming a sidewall spacer with a PSG film for forming the n^- layer, and e) a step of removing phosphorus in the PSG film by annealing. , a step of selectively diffusing only the n^- layer.