JPH04237337A - Information processor - Google Patents

Abstract

PURPOSE:To make it unnecessary to execute interruption inhibiting/releasing processing and to attain rapid processing by combining a register and a logical operation part to execute synchronous processing of processes. CONSTITUTION:A register 1 stores a WAIT bit indicating whether a process in a waiting state exists or not and a POST bit indicating whether a process in an end state exists or not. If a process P is not in the end state when a waiting instruction signal indicating the waiting state of a process W is inputted to a logical operation part 3, the operation part 3 sets up the WAIT bit and outputs a WAIT signal indicating the waiting state of the process W. When the process P has been already in the end state, the process W is continuously executed. When an end instruction signal indicating the end state of the process P is inputted to the operation part 3, the operation part 3 sets up the POST bit. When the WAIT bit has been already set up, a restart signal is outputted.

Description

[Detailed description of the invention]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus capable of parallel execution.

2. Description of the Related Art In recent years, information processing apparatuses have improved their overall processing power by dividing one process into a plurality of processes, which are small processing units, and executing these processes in parallel. At this time, synchronization processing between processes is controlled by an operating system that controls the operating environment of the computer. An example of a conventional information processing device will be described below with reference to the drawings. FIG. 6 shows two processes, a process W that requires a WAIT instruction.
This shows how the process P and the process P that require the POST command are synchronized. Here, the WAIT instruction is an instruction to wait for the processes P being processed in parallel to reach a synchronization point. When a WAIT instruction is issued, a WAIT bit is set indicating that the WAIT instruction is being executed. The POST instruction is an instruction that terminates process P and, if process W arrives at a synchronization point and is in a waiting state due to a WAIT instruction, releases the WAIT instruction of process W. When a POST instruction is issued, a POST bit is set indicating the state in which the POST instruction has been executed. Parallel processing of process W and process P will be described below. When process W reaches the synchronization point, it first checks whether process P has its POST bit set. If the POST bit is set, process W continues processing and the POS
If the T bit is not set, process W is WAI
Processing is interrupted by the T command and the WAIT bit is set. When process P reaches the synchronization point, it checks whether process W has its WAIT bit set. If the WAIT bit is set, then process P
cancels the WAIT command of process W, starts execution of process W, and ends processing of process P. WAIT
If the bit is not set, process P
The process is terminated by the T command and the POST bit is set. Figure 7 shows a JOI in which multiple processes have a joint instruction signal.
This shows processing that outputs N, synchronizes, and becomes one process. When this synchronization is established, all processes other than one predetermined default process 51 output JOIN and terminate. Then, the default process 51 is set to JO by all other processes.
A wait process is performed until the IN is output, and after the JOIN of all processes is output, the remaining processing of the default process 51 is continued. At this time, even if a process other than the default process 51 is continued, the same processing result will be obtained.

[Problems to be Solved by the Invention] However, in the above-mentioned information processing apparatus, since the processing of WAIT and POST commands, or the processing of JOIN commands is performed by the operating system, WAIT
It was necessary to disable and release interrupts at the beginning and end of instruction and POST instruction processing. Furthermore, a process that requires a WAIT command must wait for the end of a process that requires a POST command, which causes overhead because the stopping and restarting processes of processes that require a WAIT command are synchronized. Further, when all JOIN instructions have been executed, process restart processing when re-executing the remaining processing of a predetermined process also becomes overhead. Furthermore, since the number of steps in the program increases, there is a problem in that it takes a long processing time. In order to solve the above problems, the present invention eliminates the need for interrupt disabling and canceling processing by executing the processing conventionally performed by an operating system using a combination of registers and arithmetic units, and also eliminates the need for interrupt disabling and canceling processing. The process to be executed does not need to be a predetermined process, and for this reason, the present invention provides an information processing device that can perform processing faster than before.

[Means for Solving the Problems] In order to solve the above problems, an information processing apparatus of the present invention includes a register indicating the existence of a process in a waiting state and a process in a termination state, and the contents and input of the register. a logical operation unit that determines an output signal from a signal; a register that holds the number of a plurality of processes to be synchronized; a subtraction unit that subtracts 1 from the value of the register that holds the number of processes and stores it again; and the process The device is equipped with a zero determination unit that outputs a termination command signal when the value of the register holding the number of is not zero.

[Operation] The present invention eliminates the need for interrupt prohibition and release processing by realizing the processing conventionally performed by an operating system using a combination of registers and arithmetic units. In addition, the number of steps in the program, which had become large, can be reduced, resulting in faster speed. Furthermore, it is possible to eliminate process stop processing and re-execution processing that were performed for synchronization.

DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a block diagram of an information processing device according to an embodiment of the present invention. FIG. 4 is a diagram showing the relationship between register states and input signals and output signals. As shown in FIG. 2, 1 is a register, 2 is an arithmetic unit, and 3 is a logical arithmetic unit. Register 1 stores at least two bits: a WAIT bit indicating whether or not there is a process in the waiting state, and a POST bit indicating whether or not there is a process in the termination state. When each bit is set, it indicates that the respective process exists; when reset, it indicates that the respective process does not exist. The logic operation unit 3 determines the output signal from the state of each bit of the register and the state of the input signal. In this embodiment, the explanation will be made using positive logic in which a bit set is represented by "1" and a bit reset is represented by "0", but it is also possible to implement negative logic in which the states of the bits are reversed. FIG. 4 shows the relationship between register states and input signals and output signals. The states of registers not shown in FIG. 4 do not exist during normal operation. Further, the portion indicated by "X" may be either "0" or "1". When the wait command signal indicating that the process W is in the waiting state is input to the logic operation unit 3, if the process P is not in the end state, the logic operation unit 3
sets the WAIT bit and outputs a wait signal indicating that process W is in a wait state. Further, if the process P is already in the finished state, that is, if the POST bit is set, the process W is caused to continue execution. The values of the WAIT bit and POST bit after input may be any value. A process P is added to the logic operation unit 3.
When a termination command signal indicating that the terminal is in the termination state is input, the logic operation unit 3 sets the POST bit when the WAIT bit and the POST bit are "0". Furthermore, if the WAIT bit has already been set, the logic operation unit 3 outputs a restart signal for restarting the process W in the waiting state. As described above, according to this embodiment, a part of the processing conventionally performed by an operating system is performed by a combination of registers and a logic operation section, so that processing for inhibiting and canceling interrupts is not necessary. Additionally, since processing is performed using registers and a logic operation section, the number of steps in a previously large program can be reduced, allowing for faster execution. A second embodiment of the present invention will be described below. As shown in Figure 3, 1
2 is a register, 2 is an arithmetic unit, 4 is a subtraction unit, and 5 is a zero determination unit. Register 1 has as an initial value the number of processes to be synchronized minus 1. Arithmetic unit 2 is subtraction unit 4
and a zero determination section 5. The subtraction unit 4 subtracts 1 from the value of register 1 every time a combination command signal is input, and stores it again in register 1, and the zero determination unit 5 subtracts 1 from the value of register 1 every time a combination command signal is input. Executes zero judgment of value. The relationship between the value of register 1 and the input signal and output signal is shown in FIG. The part indicated by “X” in Figure 5 is
It can take either value. Each time a combination command signal indicating that a process to be synchronized has reached a synchronization point is input, 1 is subtracted from the value of register 1 and the value is re-stored. In the zero determination unit 5, every time the combination command signal is input, the register 1 is
It is determined whether the value of register 1 is zero, and if the value of register 1 is not zero, an end signal indicating the end of the process is output. The process to which the termination signal has been output terminates its processing at that point. When the value of register 1 becomes "0", a process to which no end signal is output is generated, and that process continues to perform the remaining procedures. As described above, according to this embodiment, it is possible to eliminate the waiting state of processes to be synchronized, and the time required for stopping and restarting is shortened, thereby increasing speed. FIG. 1 is a block diagram showing a third embodiment which is a combination of the first and second embodiments. In the figure, 1
2 is a register, 2 is a calculation section, 3 is a logic operation section, 4 is a subtraction section, and 5 is a zero determination section. Its operation is similar to the first and second embodiments. Note that the present invention is not limited to the above-mentioned embodiments, and various modifications can be made based on the gist of the present invention, and these are not excluded from the scope of the present invention.

[Effects of the Invention] Since the present invention is a device as described above, it produces the effects as described below. Since the combination of registers and logical operation units performs process synchronization processing, processing for inhibiting and canceling interrupts is not necessary, and speeding up can be achieved. Furthermore, since there are no processes waiting for synchronization, the time required to stop and restart processes is also eliminated, increasing speed.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of an information processing apparatus according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of an information processing device according to an embodiment of the present invention.

FIG. 3 is a configuration diagram of an information processing device according to an embodiment of the present invention.

FIG. 4 is a diagram showing the relationship between register states and input/output signals.

FIG. 5 is a diagram showing the relationship between register states and input/output signals.

FIG. 6 is a diagram of one information processing method in a conventional example.

FIG. 7 is a diagram of one information processing method in a conventional example.

FIG. 8 is a flowchart of processing in a conventional example.

[Explanation of symbols]

1 Register 2 Arithmetic unit 3 Logic operation section 4 Subtraction section 5 Zero judgment section 51 Default process

Claims (3)

[Claims] 1. A readable/writable register whose first bit is set to indicate the existence of a process in a waiting state and whose second bit is set to indicate the presence of a terminated process, and a wait instruction. If the first bit and the second bit are not both set when a signal is input, the first bit is set, and when the wait command signal is input, the second bit is set. If the first bit and the second bit are not both set when the end command signal is input, the second bit is set, and when the end command signal is input, the second bit is set. An information processing device comprising: a logic operation unit that outputs a restart signal when the first bit is set. 2. A readable and writable register that holds a certain value, a subtractor that subtracts 1 from the value of the register when a combination command signal is input, and a subtractor that subtracts 1 from the value of the register, and a subtractor that subtracts 1 from the value of the register when a combination command signal is input. An information processing device comprising: a zero determination unit that outputs an end signal when the result is determined to be non-zero. 3. A readable and writable register that holds a certain value, a subtraction unit that subtracts 1 from the value of the register when a combination command signal is input, and a subtractor that subtracts 1 from the value of the register, and a subtractor that subtracts 1 from the value of the register when a combination command signal is input. 2. The information processing apparatus according to claim 1, further comprising a zero determination section that outputs an end signal when the determination result is not zero.