JPH0423853B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application This invention relates to a technique for improving S/N in a stereo receiver.

Background technology and its problems The antenna input level vs. S/N characteristic in an FM stereo receiver is as shown in Figure 1A during stereo reception.
It is shown as a curve ST for monaural reception, and as a curve MN for monaural reception. That is, when the antenna input level is small, the S/N decreases,
In particular, when receiving stereo signals, the S/N ratio is about 20 dB worse than when receiving monaural signals due to multiple modulation.

For this reason, it has been considered to improve the S/N ratio by switching to monaural reception even for stereo broadcasting when the antenna input level is low. However, in this case, if you simply switch from stereo reception to monaural reception when the antenna input level drops below a certain level, if the antenna input level fluctuates around the stereo/monaural switching level, the switching between stereo mode and monaural mode will occur. The sound changes so frequently that it actually makes your hearing worse.

Therefore, as shown in FIG. 1B, a method has been considered in which when the antenna input level is below a predetermined level, the separation is continuously lowered as the antenna input level decreases. That is, by doing this, when the antenna input level is small, monaural reception is achieved and the S/N is improved,
As the antenna input level increases, separation becomes better from monaural to stereo. In addition, it gradually changes between monaural and stereo depending on the antenna input level, so
Even if the antenna input level fluctuates, the sense of hearing is not impaired.

As shown in Figure 1B, there are two methods for continuously changing the separation: () A method of changing the level of a subchannel signal with a subcarrier frequency of 38 kHz () A method of changing the level of a switching signal with a frequency of 38 kHz ( ) There are methods such as changing the phase of the switching signal.

However, method () requires a band elimination filter, requires a large number of parts, and cannot be integrated into an IC. Also, in method (),
The S/N ratio during monaural reception tends to deteriorate and distortion tends to increase. Furthermore, with method (), the circuit becomes complicated when integrated into an IC, and external components are also required.

OBJECTS OF THE INVENTION The present invention aims to improve the S/N by making it possible to change the separation continuously, and to eliminate the problems in the above-mentioned methods () to ().

Summary of the Invention Therefore, in the present invention, stereo demodulated left and right channel audio signals are
The separation characteristic shown in FIG. 1B is obtained by supplying the signal to the circuit shown in FIG. 2.

Embodiment That is, in FIG. 2, 1 is an intermediate frequency amplifier, 2 is an _FM demodulation circuit, and ₃ is a stereo demodulation circuit. ) sinωt+S _P L: Left channel audio signal R: Right channel audio signal S _P : Pilot signal ω: Subcarrier angular frequency (ω = 2π×38kHz) is demodulated, and this signal S _C is supplied to the demodulation circuit 3. Signals L and R are demodulated. 4 indicates an antenna input level detection circuit, to which the FM intermediate frequency signal is supplied from the intermediate frequency amplifier 1 and rectified to correspond to the antenna input level (Fig. 1B
A level detection signal _S4 (corresponding to the characteristics of) is extracted.

Furthermore, signals L and R are supplied from the demodulation circuit 3 to the bases of transistors Q ₁₁ and Q ₁₄ , the emitters of which are connected to the power supply terminal T ₁₁ through resistors R ₁₁ and R ₁₄ , and the collector of transistor Q ₁₁ is connected to the transistor Q ₁₂ and Q ₁₃ to form a differential amplifier 12, and the collector of transistor Q ₁₄ is connected to the emitters of transistors Q ₁₅ and Q ₁₆ to form a differential amplifier 15.

The bases of the transistors Q ₁₂ and Q ₁₆ are connected to each other, the bases of the transistors Q ₁₃ and Q ₁₅ are also connected to each other, and the bases of the transistors Q 12 and Q ₁₅ are also connected to each other.
The collectors of Q ₁₅ are connected together and the transistor
The collectors of Q ₁₃ and Q ₁₆ are also connected to each other. Also,
The collectors of transistors Q ₁₂ and Q ₁₅ are connected to resistor R ₁₂
and grounded through the de-emphasis capacitor _C12 , and the output terminal of the left channel.
The collectors of transistors Q _{13 and} Q ₁₆ are grounded through a resistor R ₁₃ and a de-emphasis capacitor C ₁₃ , and are also connected to the output terminal T ₁₃ of the right channel.

Furthermore, the signal S ₄ from the detection circuit 4 is transmitted to the transistor
is supplied to the base of Q ₂₁ , and its emitter is connected to the terminal.
connected to T ₁₁ , whose collector is connected to the transistor
Connected to Q ₂₂ collector. this transistor
Q ₂₂ constitutes a current mirror circuit 22 with transistor Q ₂₃ as an input side and as a ground and reference potential point.
The emitter of Q ₂₂ is grounded, and its base is connected to the collector as well as to the base of transistor Q ₂₃ , whose emitter is grounded _.

Further, the emitters of transistors Q ₂₄ and Q ₂₅ are connected to a constant current source Q ₂₆ to form a differential amplifier 24, and the base of transistor Q ₂₄ is connected to a constant current source Q 26.
Connected to the collector of Q ₂₃ as well as resistor R ₂₄
The base of the transistor Q ₂₅ is connected to the power supply V ₂₅ through the bias power supply V ₂₅ .

Further, diodes D _{22 and} D ₂₄ are connected in series between the terminal T ₁₁ and the collector of the transistor Q ₂₄ , and between the connection midpoint of the diodes D ₂₂ and D ₂₄ and the collector of the transistor Q ₂₅ . Diode D ₂₅ is connected. And transistor Q ₂₄
The collector of transistor Q 25 is connected to the bases of transistors Q ₁₃ and Q ₁₅ , and the collector of transistor Q ₂₅ is connected to the bases of transistors Q ₁₂ and Q ₁₆ .

According to such a configuration, the transistors Q ₁₁ ,
Since signals L and R are supplied to _Q14 , signal currents i _L and i _R flow through their collectors, respectively. In addition, a collector current I ₄ of a magnitude corresponding to the signal S ₄ flows through the transistor Q ₂₁ , and this
Since the current I ₄ is also the input current of the current mirror circuit 22, the current I ₄ flows from the power supply V ₂₅ to the transistor Q ₂₃ through the resistor R ₂₄ .

But now the antenna input level is small and I ₄
= 0, the current I ₄ does not flow through the resistor R ₂₄ , so the base potentials of the transistors Q ₂₄ and Q ₂₅ are equal (ignoring the base current of the transistor Q ₂₄ ), and therefore the transistor Q Since the collector currents I _{24 and} I ₂₅ of Q ₂₄ and Q 25 are equal, the transistor
The base potentials of Q ₁₂ , Q ₁₃ , Q ₁₅ , and Q ₁₆ are all equal.

Since the base potentials of transistors Q ₁₂ and Q ₁₃ are equal, the signal current from transistor Q ₁₁
i _L flows in two equal parts to transistors Q ₁₂ and Q ₁₃ , and currents 1/2i _L and 1/2i _L flow to resistors R ₁₂ and R ₁₃ , respectively. Similarly, since the base potentials of transistors Q ₁₅ and Q ₁₆ are equal, the signal current i _R from transistor Q ₁₄ is divided into two and flows into transistors Q ₁₅ and Q ₁₆ , and flows into resistors R ₁₅ and R ₁₆ . Current 1/2i _R , 1/2 respectively
i _R flows.

Therefore, currents 1/2 (i _L + i _R ) and 1/2 (i _L + i _R ) flow through the resistors R ₁₂ and R ₁₃ , so monaural signals 1/2 flow through the terminals T ₁₂ and T ₁₃ , respectively. (L+R), 1/2 (L+R) is taken out. Also, at this time, de-emphasis is performed on these signals 1/2 (L+R) and 1/2 (L+R) by capacitors C ₁₂ and C ₁₃ . Furthermore, even if the signals L and R from the demodulation circuit 3 contain subchannel signal components, these are bypassed by the capacitors C ₁₂ and C ₁₃ .

On the other hand, when the antenna input level is high and I ₄ >0, a voltage drop occurs in the resistor R ₂₄ due to the current I ₄ , and the base potential of the transistor Q ₂₄ becomes lower than the base potential of the transistor Q ₂₅ , so that I ₂₅ > _I24 , so the base potentials of transistors _Q12 and _Q16 are closer to ground than the base potentials of transistors _Q13 and _Q15 . Therefore, the currents i _L and i _R are distributed more to the transistors Q ₁₂ and Q ₁₆ and less to the transistors Q ₁₃ and Q ₁₅ , and the signal current (1-Δ)i _L +Δi is distributed to the resistors R ₁₂ and R ₁₆ . _R , (1-Δ)i _R +Δi _L (0<Δ<
1/2) flows, the signals (1-Δ)L+ΔR and (1-Δ)R+ΔL are taken out to the terminals _T12 and _T13 .

Furthermore, the antenna input level is sufficiently large;
When the current I ₄ is large enough, the voltage drop across the resistor R ₂₄ due to the current I ₄ becomes large and the transistor
Q ₂₄ is off, transistor Q ₂₅ is on, I ₂₄
= 0, I ₂₄ = I ₂₆ (I ₂₆ is the constant current of the constant current source Q ₂₆ ). Therefore, transistors Q ₁₃ and Q ₁₅ are turned off and transistors Q ₁₂ and Q ₁₆ are turned on, so the resistor
Only signal currents i _L and i _R flow through R ₁₂ and R ₁₃ , respectively.
Signals L and R are taken out to terminals T ₁₂ and T ₁₃ .

Therefore, the terminals T ₁₂ and T ₁₃ are indicated by a _coefficient that takes a value of 0≦∆≦1/2 depending _on the current I ₄ . This means that signals L ₀ and R ₀ are obtained.
Then, since the current I ₄ changes according to the antenna input level, the output signals L ₀ and R ₀ of the terminals T ₁₂ and T ₁₃
The separation changes as shown in FIG. 1B. Therefore, a good S/N ratio can always be obtained, and the separation also improves in accordance with the antenna input level.

In this case, especially according to the present invention, there is no need for a band elimination filter, etc., and when integrated into an IC, no external components are required.
Suitable for IC. In addition, since it is a current operation, non-linear distortion can be reduced, and even if the power supply voltage V _CC is low, distortion can be reduced.

Furthermore, since the current I ₄ controls the ratio of the currents I ₂₄ and I ₂₅ and thereby controls the separation, that is, the separation is equal to the current I ₂₄ and I ₂₅
Since it is not related to the absolute size of , there is little variation in characteristics.

In addition, since mixing is performed even when monaural, noise and distortion (these are in opposite phase to each other in currents i _L and i _R ) are also canceled, and therefore distortion is low and noise is small even when monaural. .

FIG. 3 shows an example of the stereo demodulation circuit 3.

That is, in FIG. 3, numeral 31 indicates a double-balanced switching circuit, which includes transistors.
The emitters of Q ₃₁ and Q ₃₂ are connected to each other, and a constant current source transistor is connected between these emitters and ground.
The collector-emitter of Q ₃₃ and the resistor R ₃₃ are connected in series, and the transistors Q ₃₄ to _{Q 36} and the resistor R ₃₆ are connected in the same way. Furthermore, the bases of transistors Q ₃₁ and Q ₃₅ are connected to each other,
The bases of transistors Q ₃₂ and Q ₃₄ are connected to each other, the collectors of transistors Q ₃₁ and Q ₃₄ are connected to each other, the collectors of transistors Q ₃₂ and Q ₃₅ are connected to each other, and the base of transistor Q ₃₆ is connected to bias power supply V. ₃₆ and the base of transistor Q ₃₃ is connected to the base of transistor Q ₃₀ .

This transistor Q ₃₀ , together with the transistor Q ₃₃ , is a current mirror circuit 3 with the ground as the reference potential point and with this transistor Q ₃₀ as the input side.
0, and its emitter is a resistor.
Grounded through R ₃₀ , its base connected to the collector.

The demodulation circuit 2 is connected between the power supply terminal T ₃₁ and the collector of the transistor Q ₃₀ . In this case, the demodulation circuit 2 is a constant current signal source, and supplies a composite signal current i _C and a DC component represented by i _C =(L+R)+(L-R) sinωt. Also, the transistor Q ₃₃ ,
The DC components of the collector currents of Q ₃₆ are made equal to each other.

Further, the emitters of transistors Q ₆₁ and Q ₆₂ are connected to a constant current source Q _P , and their collectors are connected to terminal T ₃₁ through resistors R ₆₁ and R ₆₂ , thereby forming a differential amplifier 61. And the transistor
A signal source S ₃₈ is connected between the bases of Q ₆₁ and Q ₆₂ , and the collectors of transistors Q ₆₁ and Q ₆₂ are connected to the bases of transistors Q ₃₁ and Q ₃₅ and Q ₃₂ and Q ₃₄ , respectively. In this case, the signal source _S38 supplies a switching signal with a subcarrier frequency of 38 kHz synchronized with the pilot signal.

Further, the collectors of transistors Q ₃₁ and Q ₃₄ are connected to the collector of transistor Q ₄₁ . This transistor Q ₃₄ , together with the transistor Q ₄₂ , uses the terminal T ₃₁ as a reference potential, and this transistor
A current mirror circuit 41 is configured with Q ₄₁ as the input side, and its emitter is connected to terminal T ₃₁ through resistor R ₄₁ , and its base is connected to the collector and to the base of transistor Q ₄₂ . The emitter of this transistor _Q42 is connected to _the terminal _T31 through a resistor R42.

For example, by selecting the ratio of the resistors R ₄₁ and R ₄₂ , the collector current I ₄₁ of the transistor Q ₄₁ and the collector current I ₄₂ of the transistor Q ₄₂ can be expressed as I ₄₁ :I ₄₂ =1:γ...() It is assumed that γ=2π/(π−2).

Furthermore, a current addition circuit 43 is configured. That is, the transistor Q ₄₂ is connected in series between its collector and ground, and the collector-emitter of the transistor Q ₄₃ is connected in series with the resistor R _{43 .}
The base of is connected to the base of transistor Q ₃₀ , and the collectors of transistors Q ₄₂ and Q ₄₃ are connected to the left channel output terminal T ₄₃ .

Further, the circuits 51 and 53 are transistors Q ₅₁ to
It is configured in the same manner as the circuits 41 and 43 by Q ₅₃ and the like, the collectors of the transistors Q ₃₂ and Q ₃₅ are connected to the current mirror circuit 51, and the right channel output terminal T _{53 is drawn out from the adder circuit 53} .

According to such a configuration, the composite signal current i _C from the demodulation circuit 2 is transferred to the current mirror circuit 3
0 to the emitters of transistors Q ₃₁ and Q ₃₂ , and a switching signal from a signal source S ₃₈ is supplied to the emitters of transistors Q 31 and Q 32 through differential amplifier 61.
Since the signal is supplied to the bases of Q ₃₁ and Q ₃₂ , switching demodulation is performed in the switching circuit 31, and the collectors of transistors Q ₃₁ and Q ₃₂ receive i ₃₁ =π+2/2πL+π−2/2πR i ₃₂ =π+2/2πR+π Signal currents i ₃₁ and i ₃₂ indicated by −2/2πL flow. Also, at this time, the DC components of the collector currents of transistors Q ₃₃ and Q ₃₆ are large but equal, and
The collector currents of Q ₃₁ and Q ₃₂ are the same as those of transistors Q ₃₄ and
Since the switching is in the opposite phase to the collector current of Q ₃₅ , the transistors Q ₃₁ and Q ₃₄ , Q ₃₂ and Q ₃₅
The combined collector current does not include the switching signal component.

Then, the signal current i ₃₁ is applied to the current mirror circuit 4
1 and the transistors TQ ₄₁ and Q ₄₂
Since the collector current of is set as shown in equation (), the amplified signal current γi ₃₁ flows through the collector of the transistor Q ₄₂ . Furthermore, since the transistor _Q43 is also a part of the current mirror circuit 30 having the transistor _Q30 as its input side, the signal current _iC also flows through the collector of the transistor _Q43 .

Therefore, a signal current i ₅₃ that is the difference between the signal current γi ₃₁ of the transistor Q ₄₂ and the signal current i _C of the transistor Q ₄₃ flows through the terminal T ₄₃ , and at this time, i ₅₃ = γi ₃₁ −i _C = 2π/π−2(π+2/2πL+π−2/2πR) −{(L+R)+(L−R) sinωt} =4/π−2L−(R−L) sinωt.

Therefore, the left channel signal L is obtained at the terminal T ₄₃ (the subchannel signal component is bypassed by the capacitor C ₁₂ in FIG. 2).

Furthermore, at the signal current i ₃₂ , the signals L, R
However, since the relationship is opposite to that of the signal i ₃₁ , the right channel signal R is similarly obtained at the terminal T ₅₃ .

In this way, left and right channel audio signals L and R, which have been demodulated by switching from the composite signal current i _C and whose crosstalk has been canceled, are taken out from the terminals T ₄₃ and T ₅₃ .

According to this stereo demodulation circuit 3, since everything is current operated, the power supply voltage V _CC of terminal T ₃₁
It is possible to achieve large amplitude and low distortion even if the
Audio signals L and R with a good S/N ratio and less distortion can be obtained. Furthermore, when implemented as an IC, even if the absolute values of each element vary, the relative values do not vary, so crosstalk characteristics etc. do not vary and are good. Furthermore, it is suitable for IC implementation.

Furthermore, since the noise and distortion at the terminals T ₄₃ and T ₅₃ are in opposite phases to each other, when the signals L and R are mixed when monaural in the circuit of FIG. At the same time, a monaural signal with less noise and distortion can be obtained.

In addition, in the above, in order to switch between stereo mode and monaural mode, for example, the base of transistor Q ₂₄ , resistor R ₂₄ and transistor Q ₂₃
It is sufficient to connect a switching element in series between the collector and turn it on and off.

Effects of the invention No external parts are required, making it suitable for IC implementation.
It also has less distortion and can operate even at low power supply voltages. Furthermore, there is little variation in characteristics.

[Brief explanation of drawings]

1 and 3 are diagrams for explaining the present invention, and FIG. 2 is a connection diagram of an example of the present invention. 3 is a stereo demodulation circuit, and 4 is an antenna input level detection circuit.

Claims (1)

[Claims] 1 has first to sixth transistors Q ₁₁ to Q ₁₆ ,
The emitters of the first and fourth transistors Q ₁₁ and Q ₁₄ are grounded, and the audio signals L and R of the left and right channels are supplied to their bases, respectively, and the collector of the first transistor Q ₁₁ is connected to the Second and third transistors Q ₁₂ , Q ₁₃
The collector of the fourth transistor _Q14 is commonly connected to the emitters of the fifth and sixth transistors _Q15 and _Q16 ,
The bases of the second and sixth transistors Q ₁₂ and Q ₁₆ are connected to each other, and the bases of the third and fifth transistors Q ₁₃ and Q ₁₅ are connected to each other,
The collectors of the second and fifth transistors Q ₁₂ and Q ₁₅ are connected to each other, the collectors of the third and sixth transistors Q ₁₃ and Q ₁₆ are connected to each other, and the collectors of the second and sixth transistors Q ₁₂ are connected to each other. ,Q ₁₆
and the base potentials of the third and fifth transistors Q ₁₃ and Q ₁₅ are differentially controlled in accordance with the antenna input level, and the base potentials of the second and fifth transistors Q ₁₂ and Q ₁₅ collectors and collectors of the third and sixth transistors Q ₁₃ and Q ₁₆ , the audio signals L and R are mixed and extracted at a ratio corresponding to the antenna input level.