JPH04254994A - Nonvolatile semiconductor storage device - Google Patents

Abstract

PURPOSE:To provide a NAND cell type EEPROM which enables a high-speed data writing. CONSTITUTION:The high-speed data writing is attained by providing a bit line charging means 31 which charges a plural number of bit lines to an intermediate voltage in advance at the time of writing data and selectively discharging the pre-charged bit lines according to data to write in.

Description

[Detailed description of the invention]

[Purpose of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device (EEPROM) using electrically rewritable memory cells having a charge storage layer and a control gate, and particularly to a memory cell array having a NAND cell configuration. EEPR with
Regarding OM.

0002

2. Description of the Related Art Among EEPROMs that can be highly integrated, a NAND cell type EEPROM in which a plurality of memory cells are connected in series is known. One memory cell has a FETMOS structure in which a floating gate and a control gate are stacked on a semiconductor substrate via an insulating film, and multiple memory cells are connected in series with adjacent ones sharing their sources and drains. are connected to form a NAND cell. NA
A drain at one end of the ND cell is connected to a bit line via a selection gate, and a source at the other end is connected to a common source line via a selection gate. A plurality of such memory cells are arranged in a matrix to form an EEPROM. The control gates of the memory cells are arranged continuously in the row direction and serve as word lines.

The operation of this NAND cell type EEPROM is as follows. Data writing is performed in order from the memory cells farthest from the bit line. In the case of an n-channel, a boosted write potential Vpp (about 20 V) is applied to the control gate of the selected memory cell, and the control gates and selection gates of unselected memory cells on the bit line side are applied to the control gate of the selected memory cell. An intermediate potential VppM (=about 10 V) is applied to the bit line, and 0 V (eg, "1") or an intermediate potential (eg, "0") is applied to the bit line depending on the data. At this time, the potential of the bit line is transferred through the unselected memory cells and reaches the drain of the selected memory cell. Data “1”
When , a high electric field is applied between the floating gate and drain of the selected memory cell, electrons are tunnel-injected from the drain to the floating gate, and the threshold value moves in the positive direction. data"
0'', there is no threshold change.

Data erasure is performed simultaneously on all memory cells in a NAND cell. That is, all control gates and selection gates are set to 0V, and a boosted erase potential VppE (=20V) is applied to the p-type well and the n-type substrate. As a result, electrons from the floating gates of all memory cells are emitted to the wells, and the threshold voltages shift in the negative direction.

Data reading is performed by setting the control gate of the selected memory cell to 0V, setting the control gates and selection gates of the other memory cells to power supply potential Vcc (=5V), and determining whether or not current flows in the selected memory cell. This is done by detecting the

[0006] Such a conventional NAND cell type EEPRO
In M, there was a problem in that it took time to boost the voltage of the bit line to an intermediate potential, and therefore it took time to write data. This will be specifically explained using FIGS. 6 and 7. FIG. 6 shows the configuration of a bit line control circuit section of a conventional NAND cell type EEPROM, and FIG. 7 is a control timing diagram thereof. As shown in FIG. 7, data is loaded from time t1, for example, in page mode, and from time t2.
The memory cell enters the write state. In other words, after time t2, the bit line BL and sense amplifier S
Ai, the control signal BL is applied to the transfer gates QT1, QT2,..., QTm connecting the data latch circuit LAi.
D (for example, 10V) is input. This control signal BLD
The rise time TR is approximately 5 μsec. At the same time as the control signal BLD rises, the latch circuit LAi
An intermediate potential VppM (for example, 10 V) from the booster circuit is supplied to necessary bit lines through the booster circuit. In FIG. 7, bit line BL1 remains at 0V and bit line B
An example in which L2 rises to VppM is shown. At this time, the time required for the bit line to rise is approximately tBL
R = 20 μsec. Further, during this writing, the boosted potential Vpp is applied to the selected control gate CG1, and the intermediate potential VppM is applied to the unselected control gate CG2. As shown in FIG. 7, the net time required to write data is approximately tWN = 40 μsec, but if the previous bit line charging time is taken into account, the write time tW is: tW = tBLR + tWN = 60 μsec. ].

The intermediate potential V used for the above write operation
ppM is generated by a boost circuit inside the chip in single 5V power supply operation. However, the internal voltage boosting circuit generally has a weak current supply capability, and therefore it is difficult to shorten the voltage boosting time of the bit line to the intermediate potential. For this reason, especially in highly integrated EEPROMs, there is a possibility that the write time specifications cannot be met.

[0008]

[Problem to be solved by the invention] As described above, the conventional N
The AND cell type EEPROM has a problem in that it is not possible to write data at high speed. The present invention has been made in view of the above points, and an object of the present invention is to provide a NAND cell type EEPROM that enables high-speed writing. [Structure of the invention]

[0009]

[Means for Solving the Problems] A NAND cell type EEPEOM according to the present invention is provided with a bit line charging means for charging a plurality of bit lines to an intermediate potential in advance during data writing, and the precharged bit lines are used to store the data to be written. The present invention is characterized in that data writing is performed by selectively discharging in accordance with the current.

0010

[Operation] Considering that the current supply capacity of the internal booster circuit is limited, it is better to charge the bit line to an intermediate potential in advance, rather than using such a booster circuit to charge the bit line to an intermediate potential during writing. Selective discharge according to data facilitates high-speed operation. Therefore, according to the present invention, a NAND cell type EEPROM capable of high-speed data writing can be obtained.

[0011]

Embodiments Hereinafter, embodiments will be described with reference to the drawings.

FIG. 1 shows a NAND circuit according to an embodiment of the present invention.
1 is a block diagram showing the overall configuration of a cell-type EEPROM. FIG. 21 is a memory cell array in which NAND cells are arranged in a matrix. Around the memory cell array 21, there are a bit line sense amplifier 22 that detects its output, a row address buffer 24 and a row decoder 23 that select a word line, and a column address buffer 2 that selects a bit line.
6 and a column decoder 25 are arranged. The data latch circuit 27 temporarily stores input/output data, and has a capacity equal to the number of bit lines (for example, 2048) in this embodiment. Data read from memory cell array 21 is taken out to data input/output lines via I/O sense amplifier 28 and data out buffer 29. External write data is taken into the data latch circuit 27 from the data input/output line via the data in buffer 30. A bit line charging circuit 31 is provided at the bit line end of the memory cell array 21 on the opposite side from the data latch circuit 27 to precharge the bit line to an intermediate potential before writing data.

FIGS. 2 and 3 show the NAND of this embodiment.
The specific configuration of the cell is shown. (a) in Figure 2 is the layout, (b) is the equivalent circuit, and (a) in Figure 3 is the layout.
(b) are A-A' and B-B' in Fig. 2(a), respectively.
It is a cross section.

In this embodiment, eight memory cells M1 to
M8 constitutes a NAND cell. Each memory cell is connected to a floating gate 14 (141
148) is formed, and a control gate 16 (148) is formed thereon by a second layer polycrystalline silicon film via an interlayer insulating film 15.
61 to 168) are laminated. Floating gate 14 is a charge storage layer. Control gate 1 of each memory cell
Control gate lines CG (CG1 to CG8) 6 are continuously arranged for NAND cells arranged in the horizontal direction, and these usually serve as word lines. memory cell source,
The n-type layer 19, which is a drain diffusion layer, is shared by adjacent ones, and eight memory cells M1 to M8 are connected in series. There are selection gates S1 and S2 on the drain and source sides of these eight memory transistors, respectively.
is provided. The gate insulating film of these selection gates is usually formed separately from the memory cell part and thicker than that, and on top of it are two layers of gate electrodes 149, 169 and 14.
10,1610 is formed. These two layers of gate electrodes are arranged continuously in the direction of the control gate line CG in contact with each other at a predetermined interval to form selection gate lines SG1 and SG2. The substrate on which the elements are formed is covered with a CVD insulating film 17, and a bit line 1 is formed on this.
8 are arranged. The bit line 18 is in contact with the drain diffusion layer of one selection gate S1. The source diffusion layer of the other selection gate S2 is normally provided as a common source line for a plurality of NAND cells.

FIG. 4 specifically shows the configuration of the bit line control circuit section. One end of each bit line BLi (i=1 to m) of the memory cell array 21 is connected to a data latch circuit (LA) via a first transfer gate QT1i.
i) 27 and the sense amplifier (SAi) 22, and is further connected to the output signal CSLi of the column decoder 15.
The input/output line I/O through the transistor controlled by
It is connected to the.

The other end of the bit line BLi is connected via a second transfer gate QT2i to an output line BLCRL of a booster circuit 32 that generates an intermediate potential. The second transfer gate QT2i and the booster circuit 32 constitute the bit line charging circuit 31 in FIG.

FIG. 5 is a timing diagram showing the write operation of the EEPROM according to this embodiment. Prior to writing data into the memory cell, external data is taken into the latch circuit 27, so-called data loading, from time t1. This data loading is performed, for example, in page mode, and FIG. 5 shows an example in which the page length is 512 bits. During data loading in this page mode, for example, at the 254th bit, the booster circuit 32
Therefore, the intermediate potential VppM is applied to the output line BLCRL.
(~10V) charging starts. At the same time, the control line BL
An intermediate potential is also applied to U, all of the second transfer gates QT2i are turned on, and all bit lines BLi are charged to the intermediate potential VppM. This intermediate potential charging can be supplied halfway from the power supply Vcc. As described above, this bit line is charged using the internal booster circuit 32 which has a limited current supply capacity, so the time tBLR is long, but if the bit line is charged by the time the page data load is finished, good. For example, page cycle 100nsec, page length 5
Assuming 12 bits, the data loading time is 100 [n sec ] x 512 = 51.2 [μsec]
]

[0018] Since the time tBLR required to raise the bit line to an intermediate potential is about 20 μsec, the bit line can be sufficiently charged by time t2 when data writing is started. Simultaneously with this precharging of the bit lines, each control gate line is similarly precharged to an intermediate potential.

In this way, all the bit lines are precharged to an intermediate potential during data loading, and at time t2, a write state to the NAND cell is entered. That is, at this timing, the control signal BLD is raised, the first transfer gate QT1i is turned on, and the data latched in the data latch circuit 27 is transferred to the bit line BLi. As a result, the bit line (BL2 in FIG. 5) into which "0" data (intermediate potential) enters is held at an intermediate potential, and the bit line (in FIG. 5, BL2) into which "1" data (OV) enters is held at an intermediate potential.
L1) is grounded and discharged to 0V. Furthermore, in synchronization with the rise of the control signal BLD, the selected control gate line (CG1 in FIG. 5) is connected to the boosted write potential Vpp.
is given. The remaining unselected control gate lines (C
G2) is held at the intermediate potential VppM. As a result, electrons are injected into the floating gates of the selected memory cells along the bit line that has been discharged to 0V.

[0020] The bit line can be discharged at a sufficiently high speed during this write operation compared to charging using an internal booster circuit. The net time tWN required for data writing is 20 μsec as mentioned above, and the time tR required for the control signal BLD to rise is about 4 μsec, so the write time tW is approximately tW = tR + tWN = 45 [μsec]. Become. Therefore, compared to the conventional method, the writing time can be significantly reduced. Data erasing and reading operations are the same as conventional ones.

In the embodiment, all bit lines of the memory cell array were charged to an intermediate potential during data writing.
It is also possible to adopt a method in which all bit lines in the block are charged to an intermediate potential on a block-by-block basis. In addition, the present invention can be implemented with various modifications without departing from the spirit thereof.

[0022]

As explained above, according to the present invention, a bit line is precharged to an intermediate potential before data writing, and is selectively discharged to perform a writing operation, thereby achieving a high-speed writing operation. A writeable NAND cell type EEPROM can be provided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the overall configuration of an EEPROM according to an embodiment of the present invention.

FIG. 2 is a layout and an equivalent circuit diagram showing a NAND cell of the same embodiment.

FIG. 3 is a diagram showing a cross-sectional structure of a NAND cell of the same example.

FIG. 4 is a diagram showing the configuration of a bit line control circuit section of the same embodiment.

FIG. 5 is a timing chart for explaining the data write operation of the same embodiment.

FIG. 6 is a diagram showing the configuration of a bit line control circuit section of a conventional EEPROM.

FIG. 7 is a timing diagram for explaining a conventional data write operation.

[Explanation of symbols]

21...Memory cell array, 22...Bit line sense amplifier, 23...Row decoder, 24...Row address buffer,
25... Column decoder, 26... Column address buffer, 27... Data latch circuit, 28... I/O sense amplifier, 29... Data out buffer, 30... Data in buffer, 31... Bit line charging circuit, 32... Boosting circuit, BL
1 to BLm...bit line, CG1 to CG8...control gate line (word line), QT11 to QT1m...first
transfer gate, QT21 to QT2m...second
transfer gate.

Claims (2)

[Claims] 1. A memory cell array in which a plurality of electrically rewritable memory cells in which a charge storage layer and a control gate are laminated on a semiconductor substrate are connected in series to form a NAND cell and arranged in a matrix; and the memory cell array. row selection means for selecting a word line of the memory cell array; column selection means for selecting a bit line of the memory cell array; data latch means having a function of selectively discharging bit lines; and bit lines connected to the bit lines of the memory cell array via a second transfer gate to charge a plurality of bit lines to an intermediate potential in advance during data writing. A nonvolatile semiconductor memory device comprising a charging means. 2. The nonvolatile device according to claim 1, wherein the bit line charging means charges the bit line to an intermediate potential during data loading before starting data writing to the memory cell array. Semiconductor storage device.