JPH04255995A - Instruction cache - Google Patents

Abstract

PURPOSE:To speed up arithmetic processing by simultaneously executing plural instructions at a CPU even though the instructions are variable. CONSTITUTION:An instruction predecoder 21 is provided and the length of the variable length instruction, which is taken in from a main storage device 3, is decoded by the instruction predecoder 21 and stored in an instruction storage section 22 with the variable length instructions. In case of cache hit, the variable length instructions and the instruction length information stored in the instruction storage section 22 are supplied to CPU 2.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-speed memory, so-called instruction cache, which is used in a computer by being connected between a central processing unit (hereinafter referred to as a CPU) and a main memory.

Although CPUs that execute most instructions in one cycle are currently on the market, users are demanding even faster arithmetic processing. Here, as a method of speeding up arithmetic processing, there is a method of increasing the frequency of the operating clock. However, due to the configuration of the peripheral circuits, it is not possible to support this. Therefore, there is a need for a method for increasing the speed of arithmetic processing without increasing the frequency of the operating clock. One way to meet this demand is to simultaneously execute multiple instructions, and this can be easily done in a so-called fixed-length instruction format computer. However, even in computers with variable-length instruction format,
In order to be able to execute multiple instructions simultaneously, the CP
Improvements are needed in the instruction cache used in connection between the U and the main memory.

0003

2. Description of the Related Art FIG. 3 is a diagram showing a main part of an example of a computer using a conventional instruction cache 1.
is a CPU, and 3 is a main storage device. In the instruction cache 1, numeral 4 is an instruction storage section that stores instructions fetched from the main memory 3, and 5 is an instruction storage section that compares the instruction address output from the CPU 2 with a comparison address held in the instruction cache 1, and This is a cache hit/cache miss determination unit that determines whether there is a hit or a cache miss.

[0004] In such a computer, the CPU 2
When fetching an instruction, first, instruction cache 1 is accessed from CPU 2, and the instruction to be fetched is in instruction cache 1 (cache hit).
, this instruction is captured. On the other hand, if the instruction to be fetched is not in the instruction cache 1 (cache miss), the main memory 3 is accessed,
The corresponding instruction is read out, taken into the CPU 2, and stored in the instruction cache 1.

[0005]

[Problem to be Solved by the Invention] By the way, when the CPU 2 is configured to be able to execute multiple instructions at the same time, and the instructions have a fixed length, the positions of the instructions following the first instruction are fixed. Therefore, by decoding a plurality of instructions, it is possible to simultaneously execute the plurality of instructions and speed up arithmetic processing. However, if the instructions have a variable length, the positions of the instructions following the first instruction vary, so unless the position of the subsequent instructions can be identified by some method, multiple instructions cannot be executed simultaneously.

Here, as a method for making it possible to execute multiple instructions at the same time even with variable length instructions, as shown in FIG. A possible method is to decode the instruction length of the fetched variable-length instruction using the instruction predecoder 6 and supply a plurality of instructions to the instruction decoder 7. In addition, 8
, 9 are instruction registers for temporarily storing instructions.

However, in this method, the instruction length is decoded after the variable length instruction is loaded into the CPU 2, and in this case, it is necessary to decode the instruction length of multiple variable length instructions at the same time. , it is not easy to decode a plurality of variable-length instructions at the same time, and as a result, there is a problem in that the speed of arithmetic processing is rather slowed down.

Furthermore, as shown in FIG. 5, a method can be considered in which an instruction decoder 10 is provided in the instruction cache, the instruction decoder 10 decodes instructions, and the result is stored in the instruction storage section 4. However, in this case, it was necessary to increase the data size of the instruction storage section 4 to correspond to the longest instruction, which was not practical. In addition, 1
1 is an instruction register.

SUMMARY OF THE INVENTION In view of the above, an object of the present invention is to provide an instruction cache that allows a CPU to decode multiple instructions at the same time, even if they are variable length instructions, thereby speeding up arithmetic processing. shall be.

0010

[Means for Solving the Problems] FIG. 1 is an explanatory diagram of the principle of the present invention, and the instruction cache according to the present invention is an instruction length decoder for decoding the instruction length of a variable length instruction fetched from a main storage device 3. The instruction storing means 13 stores the variable length instructions fetched from the main memory 3 together with the instruction length information obtained by the instruction length decoding means 12.

[0011]

[Operation] In the present invention, a variable length instruction is stored in the instruction storage means 13 together with its instruction length information, so when a cache hit occurs, the corresponding instruction is transferred from the instruction storage means 13 together with its instruction length information to the CPU 2. supplied to Therefore, even if the instructions are variable length, the CPU 2 can decode multiple instructions at the same time.

In the case of a cache miss, the corresponding variable length instruction is fetched from the main storage device 3 into the instruction cache of the present invention, and after its instruction length is decoded by the instruction length decoding means 12, the variable length instruction is , are supplied to the CPU 2 together with instruction length information. Therefore, variable length instructions are
Although it takes more time to decode in U2 than when there is a cache hit, even in this case, multiple instructions can still be decoded at the same time.

[0013]

[Embodiment] An embodiment of the present invention will be described below with reference to FIG. Note that in FIG. 2, the CPU and main storage device are given the same reference numerals as in FIGS. 3 to 5.

FIG. 2 is a block diagram showing the main parts of an example of a computer using the instruction cache 14 of this embodiment.
It is built into a microprocessor with 2. That is, this embodiment is an example in which the instruction cache 14 and the CPU 2 are formed on a single semiconductor substrate.

Here, in the instruction cache 14, 1
Reference numeral 5 denotes an instruction address input section, that is, a block that receives an instruction address output from the CPU 2.

Further, 16 is a cache hit/cache miss determination unit, which compares the instruction address output from the CPU 2 and the comparison address held in the instruction cache 14 to determine whether there is a cache hit or a cache miss. This is a block for making decisions, and is made up of a RAM 17 that holds a comparison address, and an address comparison section 18 that compares the comparison address and the instruction address.

Reference numeral 19 denotes an instruction address output section, that is, a block that outputs the instruction address input to the instruction address input section 15 to the main storage device 3 when a cache miss is notified from the address comparison section 18.

Reference numeral 20 denotes an instruction data input section, that is, a block that receives variable length instructions output from the main storage device 3.

Further, 21 is a decoder called an instruction predecoder, which is a block unique to this embodiment.
This decoder is configured to decode variable length instructions taken in from the main storage device 3 prior to the instruction decoder provided in the CPU 2 to obtain instruction length information. Here, the instruction length information is configured as shown in Table 1, for example.

[0020]

[Table 1]

Further, 22 is an instruction storage section, 23 is a bypass section, and 24 is an instruction data output section. It is composed of a RAM 26 for storing instruction length information obtained by the decoder 21.

Here, when the input/output buffer 25 is notified of a cache hit from the address comparator 18, it reads the corresponding instruction and instruction length information from the RAM 26, and
These are supplied to the instruction data output section 24, and when a cache miss is notified from the address comparison section 18, instruction data is received from the instruction data input section 20, and instruction length information is received from the instruction predecoder 21. ,
It operates to write these into the RAM 26.

Furthermore, when a cache miss occurs, the bypass section 23 receives a variable length instruction from the instruction data input section 20, receives instruction length information from the instruction predecoder 21, and transfers these to the instruction data output section 24. It is something.

The instruction data output section 24 is connected to the instruction storage section 22.
Alternatively, variable length instructions and instruction length information supplied from the bypass section 23 are output to the CPU 2.

In this embodiment, the main storage device 3
The variable length instruction fetched from the instruction predecoder 21
Since the variable-length instruction is stored in the instruction storage unit 22 together with the instruction length information decoded by
is supplied to the CPU 2 via the instruction data output section 24. Therefore, even if the instructions are variable length, the CPU 2 can decode a plurality of instructions at the same time to increase the speed.

In the case of a cache miss, the corresponding variable length instruction is fetched from the main storage device 3, its instruction length is decoded by the instruction pre-decoder 21, and then the variable length instruction is supplied to the CPU 2 together with instruction length information. be done. Therefore, it takes more time for this variable length instruction to be decoded by the CPU 2 than when there is a cache hit, but even in this case, it is still possible to decode a plurality of instructions at the same time.

[0027]

According to the present invention, the instruction length decoding means is provided and the instruction length information obtained by the instruction length decoding means is stored in the instruction storage means together with the variable length instruction, so that cache hits can be avoided. In this case, the corresponding variable length instruction and its instruction length information are transferred from the instruction storage means to the CP
Since the instruction can be supplied to U, even if the instruction is a variable length instruction, the CPU can decode multiple instructions at the same time and increase the speed.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the principle of the present invention.

FIG. 2 is a block diagram showing main parts of an embodiment of the present invention together with a CPU and a main storage device.

FIG. 3 is a block diagram showing main parts of an example of a computer using a conventional instruction cache.

FIG. 4 is a block diagram showing the main parts of another example of a computer using a conventional instruction cache.

FIG. 5 is a block diagram showing the main parts of yet another example of a computer using a conventional instruction cache.

[Explanation of symbols]

2 CPU 3 Main memory 12 Instruction length decoding means 13 Instruction storage means

Claims (1)

[Claims] 1. An instruction length decoding means (12) for decoding the instruction length of a variable length instruction fetched from a main memory device (3); An instruction cache comprising: instruction storage means (13) for storing instruction length information obtained by the length decoding means (12).