JPH0425726B2 - - Google Patents
Info
- Publication number
- JPH0425726B2 JPH0425726B2 JP20487183A JP20487183A JPH0425726B2 JP H0425726 B2 JPH0425726 B2 JP H0425726B2 JP 20487183 A JP20487183 A JP 20487183A JP 20487183 A JP20487183 A JP 20487183A JP H0425726 B2 JPH0425726 B2 JP H0425726B2
- Authority
- JP
- Japan
- Prior art keywords
- switching means
- capacitor
- operational amplifier
- potential point
- common potential
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000003990 capacitor Substances 0.000 claims description 48
- 239000000470 constituent Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 238000004891 communication Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H19/00—Networks using time-varying elements, e.g. N-path filters
- H03H19/004—Switched capacitor networks
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Filters That Use Time-Delay Elements (AREA)
Description
（技術分野）
本発明はLSI化に適したDCオフセツト量が少
なく且つ構成素子数の少ないスイツチトキヤパシ
タSC振幅等化器に関するものである。
（背景技術）
通信機器のLSI化が進展するに伴つて、通信機
器の重要な構成要素である振幅等化器に対しても
LSI化が強く要請されて来ている。LSI化振幅等
化器の構成法として次の２つの方法が考えられ
る。
(1) 抵抗Ｒ、キヤパシタＣ及び演算増幅器OP−
AMPを用いる方法。
(2) スイツチSW、Ｃ及びOP−AMPを用いる方
法。
LSI化の場合のＲ，Ｃの実現精度の観点から、
最近は殆んど(2)の方法が、図１に示す双２次形回
路が主に用いられている。図１に示す回路のＺ領
域の伝達関数T1（Z-1）は次式で与えられる。
T1（Z-1）＝Vput／Vio＝N1／D1 …(1)
ここでN1＝−｛K8＋K7−（2K8＋K7−K2K5）
Z-1＋K8Z-2｝
D1＝１＋K1−（２＋K1−K2K3）Z-1＋Z-2
Ｚ＝ei〓T：Ｔ＝１／c：c＝クロツク周波数
C1＝C2＝1.0，K3＝K4，K5＝K6
である。
この回路構成では、構成素子数（Ｒ，Ｃ、及び
SW）が多いこと、及び回路から発生するDCオ
フセツト量が多い等の欠点がある。このため、こ
の回路により、LSI化振幅等化器を実現した場
合、チツプ面積が増大し、更に外付部品が必要と
なる場合がある。
（発明の課題）
本発明は前記欠点を除去するため、構成素子数
の少なく、しかも回路から発生するDCオフセツ
ト量が前記回路より少ない新しい回路を提供する
ものである。
（発明の要約）
本発明の特徴は、非反転入力端子が共通電位点
へ接続された演算増幅器Ｍと、第１容量K5と第
２容量K4と第３容量K1と第４容量K2と第５容量
K3と、信号入力端子と共通電位点とを切換えて
前記第１容量K5の他端へ接続する第１スイツチ
ング手段SW１と、前記演算増幅器Ｍの反転入力
端子と共通電位点を切換えて、前記第１容量K5
の一端へ接続する第２スイツチング手段SW２
と、前記演算増幅器Ｍの出力端子と共通電位点と
を切換えて前記第２容量K4の他端へ接続する第
３スイツチング手段SW３と、前記演算増幅器Ｍ
の反転入力端子と共通電位点を切換えて、前記第
１容量K4の一端へ接続する第２スイツチング手
段SW２と、前記演算増幅器Ｍの出力端子と共通
電位点とを切換えて前記第３容量K1の他端へ接
続する第４スイツチング手段SW４と、前記演算
増幅器Ｍの反転入力端子と共通電位点を切換え
て、前記第３容量K1の一端へ接続する第２スイ
ツチング手段SW２と、他端が共通電位点に接続
された前記第５容量K3の一端と共通電位点とを
切換えて、前記第４容量K2の他端へ接続する第
５スイツチング手段SW５と、前記演算増幅器Ｍ
の出力端子と共通電位点を切換えて前記第４容量
K2の一端へ接続する第４スイツチング手段SW４
と、第６容量K6と、第７容量C2と、第８容量C1
と、前記信号入力端子と前記第６容量K6の他端
とを接続する第７スイツチング手段SW７と、前
記演算増幅器Ｍの反転入力端子と前記第６容量
K6の一端とを接続する第８スイツチング手段SW
８と、前記演算増幅器Ｍの反転入力端子と前記他
端が共通電位点に接続された前記第５容量K3の
一端とを接続する第９スイツチング手段SW９
と、前記演算増幅器Ｍの出力端子と信号出力端子
とを接続する第10スイツチング手段SW１０と、
前記演算増幅器Ｍの反転入力端子に前記第７、第
８容量C1，C2の他端が接続される構成と、前記
第７容量C1の一端と前記第８容量C2の一端とを
切換えて前記演算増幅器Ｍの出力端子に接続する
第６スイツチング手段SW６とを備え、前記各ス
イツチング手段は２相クロツクで、駆動され、且
つ第１及び第３スイツチング手段とからなる組
と、第２、第４及び第５スイツチング手段とから
なる組とは逆相関係で共通電位点に接続され、第
６スイツチング手段は第１及び第３スイツチング
手段とからなる組と同相関係にあり、第７、第８
及び第10スイツチング手段とからなる組は第１及
び第３スイツチング手段とからなる組と同相関係
にあり、且つ第９スイツチング手段は第２、第４
及び第５スイツチング手段と同相関係にあるスイ
ツトキヤパシタ振幅等化器にある。
（発明の構成および作用）
図２は、本発明による構成素子数の少ない、し
かも回路から発生するDCオフセツト量の少ない
SCを用いた振幅等化器である。この回路のＺ領
域に於ける伝達関数T2（Z-1）は次式で与えられ
る。
T2（Z-1）＝Vput／Vio＝−N2／D2 …(2)
ここでN2＝K6（１＋K1）−（2K6＋K1K6−K2
K5）Z-1＋K6Z-2｝
D2＝１＋K1−（２＋K1−K2K4）Z-1＋Z-2
Ｚ＝ei〓T：Ｔ＝１／c：c＝クロツク周波数
C1＝C2＝1.0，K2＝K3
である。
また、図３は適用周波数がクロツク周波数c
に比べて十分小さい場合の回路から発生するDC
オフセツト量に着目したRC等価回路である。図
３に於いて、E(1)io，E(2)ioをDCオフセツト量の起電
圧、Y(1)io，Y(2)ioをDCオフセツト量の駆動抵抗と
する。この回路の出力端子に於けるDCオフセツ
ト量Vput(0)は次の様になる。
Vput(0)＝R4Ｙ(1)
inＥ(1)
in−R2R4／R1Ｙ(2)
inＥ(2)
in …(3)
従つて、DCオフセツト量を小さくするにはR4
を小さく（又はK4を大きく）しなければならな
い。本発明は、このK4を図１の回路に比較して
大きくとれる回路である。また構成素子数も表１
に示す如く少なくなつている。
(Technical Field) The present invention relates to a switched capacitor SC amplitude equalizer with a small amount of DC offset and a small number of constituent elements, which is suitable for LSI implementation. (Background technology) As the use of LSI in communication equipment progresses, amplitude equalizers, which are important components of communication equipment,
There is a strong demand for LSI technology. The following two methods can be considered for configuring the LSI amplitude equalizer. (1) Resistor R, capacitor C and operational amplifier OP-
Method using AMP. (2) Method using switches SW, C and OP-AMP. From the viewpoint of realization accuracy of R and C in the case of LSI,
Recently, for most method (2), the biquadratic circuit shown in FIG. 1 is mainly used. The Z-domain transfer function T 1 (Z −1 ) of the circuit shown in FIG. 1 is given by the following equation. T 1 (Z -1 ) = V put / V io = N 1 / D 1 ...(1) Here, N 1 = - {K 8 + K 7 - (2K 8 + K 7 - K 2 K 5 )
Z -1 +K 8 Z -2 } D 1 = 1 + K 1 - (2 + K 1 - K 2 K 3 ) Z -1 + Z -2 Z = e i 〓 T : T = 1/c: c = clock frequency C 1 = C2 =1.0, K3 = K4 , K5 = K6 . In this circuit configuration, the number of constituent elements (R, C, and
There are disadvantages such as a large amount of SW) and a large amount of DC offset generated from the circuit. Therefore, if an LSI amplitude equalizer is implemented using this circuit, the chip area will increase and additional external components may be required. (Problem of the Invention) In order to eliminate the above-mentioned drawbacks, the present invention provides a new circuit which has a smaller number of constituent elements and which generates less DC offset than the circuit described above. (Summary of the Invention) The present invention is characterized by an operational amplifier M whose non-inverting input terminal is connected to a common potential point, a first capacitor K5 , a second capacitor K4 , a third capacitor K1 , and a fourth capacitor K. 2 and 5th capacity
K3 , a first switching means SW1 for switching the signal input terminal and the common potential point and connecting it to the other end of the first capacitor K5 , and switching the inverting input terminal of the operational amplifier M and the common potential point, Said first capacity K 5
second switching means SW2 connected to one end of
, a third switching means SW3 for switching the output terminal of the operational amplifier M and a common potential point and connecting it to the other end of the second capacitor K4 ;
A second switching means SW2 switches the inverting input terminal of the operational amplifier M and the common potential point to connect it to one end of the first capacitor K4 , and switches the output terminal of the operational amplifier M and the common potential point to connect the third capacitor K4 to one end of the first capacitor K4. a fourth switching means SW4 connected to the other end of the third capacitor K1 , a second switching means SW2 connected to one end of the third capacitor K1 by switching a common potential point with the inverting input terminal of the operational amplifier M; a fifth switching means SW5 that switches between one end of the fifth capacitor K3 connected to the common potential point and the common potential point and connects it to the other end of the fourth capacitor K2 ; and the operational amplifier M
by switching the output terminal and common potential point of the fourth capacitor.
Fourth switching means SW4 connected to one end of K2
, the sixth capacitor K 6 , the seventh capacitor C 2 , and the eighth capacitor C 1
, a seventh switching means SW7 connecting the signal input terminal and the other end of the sixth capacitor K6 , and an inverting input terminal of the operational amplifier M and the sixth capacitor K6.
Eighth switching means SW for connecting one end of K6
8 and a ninth switching means SW9 for connecting the inverting input terminal of the operational amplifier M and one end of the fifth capacitor K3 , the other end of which is connected to a common potential point.
and tenth switching means SW10 for connecting the output terminal of the operational amplifier M and the signal output terminal,
The other ends of the seventh and eighth capacitors C 1 and C 2 are connected to the inverting input terminal of the operational amplifier M, and one end of the seventh capacitor C 1 and one end of the eighth capacitor C 2 are connected. a sixth switching means SW6 connected to the output terminal of the operational amplifier M, each switching means being driven by a two-phase clock; , the fourth and fifth switching means are connected to a common potential point in an opposite phase relationship, the sixth switching means is in phase relationship with the group consisting of the first and third switching means, and the seventh, 8th
and the tenth switching means are in phase with the group consisting of the first and third switching means, and the ninth switching means is in phase with the set consisting of the first and third switching means.
and a switch capacitor amplitude equalizer in phase with the fifth switching means. (Structure and operation of the invention) Figure 2 shows a circuit according to the present invention that has a small number of constituent elements and a small amount of DC offset generated from the circuit.
This is an amplitude equalizer using SC. The transfer function T 2 (Z -1 ) of this circuit in the Z region is given by the following equation. T 2 (Z -1 ) = V put /V io = -N 2 /D 2 ...(2) Here, N 2 = K 6 (1 + K 1 ) - (2K 6 + K 1 K 6 - K 2
K 5 ) Z -1 +K 6 Z -2 } D 2 = 1 + K 1 - (2 + K 1 - K 2 K 4 ) Z -1 + Z -2 Z = e i 〓 T : T = 1/ c : c = clock frequency C 1 =C 2 =1.0, K 2 =K 3 . In addition, in Figure 3, the applied frequency is the clock frequency c.
DC generated from the circuit when it is sufficiently small compared to
This is an RC equivalent circuit focusing on the amount of offset. In FIG. 3, E(1) io and E(2) io are the electromotive voltages of the DC offset amount, and Y(1) io and Y(2) io are the drive resistances of the DC offset amount. The DC offset amount Vput (0) at the output terminal of this circuit is as follows. V put(0) = R 4 Y(1) inE(1) in−R 2 R 4 /R 1 Y(2) inE(2) in …(3) Therefore, to reduce the DC offset amount, R Four
must be made smaller (or K4 larger). The present invention is a circuit in which this K4 can be increased compared to the circuit of FIG. Table 1 also shows the number of constituent elements.
As shown in the figure, it is decreasing.
【表】
次に本発明の有用性を確かめるため、図４に示
す要求特性を設計、試作をおこなつた。周波数範
囲（０〜100kHzまで）に於いて、要求精度を満
足するパラメータの組を図１と図２の回路につい
て表２に示す。また、同表にLSI化する場合に問
題になる最小容量比を単位とした場合の各々の容
量比及び総容量を示す。従つて、本発明の回路が
総容量で1/8になり、チツプ面積が大巾に少なく
なる。また、表３に測定DCオフセツトを示す。
このDCオフセツトも本発明の回路が1/9になり外
付部品によるDCオフセツト対策がなくなると思
われる。[Table] Next, in order to confirm the usefulness of the present invention, we designed and produced a prototype with the required characteristics shown in FIG. Table 2 shows a set of parameters that satisfy the required accuracy in the frequency range (0 to 100 kHz) for the circuits of FIGS. 1 and 2. In addition, the same table shows each capacity ratio and total capacity when the minimum capacity ratio, which is a problem when converting to LSI, is used as a unit. Therefore, the total capacity of the circuit of the present invention is reduced to 1/8, and the chip area is greatly reduced. Table 3 also shows the measured DC offset.
This DC offset is also reduced to 1/9 in the circuit of the present invention, and it is thought that there is no need to take countermeasures against DC offset using external components.
【表】【table】
【表】
（発明の効果）
以上のごとく、本発明によるとLSI化に適した
構成素子数の少ないDCオフセツトの少ない振幅
等化器が得られる。[Table] (Effects of the Invention) As described above, according to the present invention, an amplitude equalizer with a small number of constituent elements and a small DC offset, which is suitable for LSI implementation, can be obtained.
図１は従来の回路図、図２は本発明による回路
図、図３は図２のRC等価回路図、図４は振幅要
求特性の一例を示す図である。
Ｍ……演算増幅器、SWi……スイツチング手
段、Ci，Ki……キヤパシタ。
FIG. 1 is a conventional circuit diagram, FIG. 2 is a circuit diagram according to the present invention, FIG. 3 is an RC equivalent circuit diagram of FIG. 2, and FIG. 4 is a diagram showing an example of amplitude required characteristics. M... operational amplifier, SW i ... switching means, C i , K i ... capacitor.
Claims (1)
算増幅器Ｍと、第１容量K5と第２容量K4と第３
容量K1と第４容量K2と第５容量K3と、信号入力
端子と共通電位点とを切換えて前記第１容量K5
の他端へ接続する第１スイツチング手段SW１
と、前記演算増幅器Ｍの反転入力端子と共通電位
点を切換えて、前記第１容量K5の一端へ接続す
る第２スイツチング手段SW２と、前記演算増幅
器Ｍの出力端子と共通電位点とを切換えて前記第
２容量K4の他端へ接続する第３スイツチング手
段SW３と、前記演算増幅器Ｍの反転入力端子と
共通電位点を切換えて、前記第１容量K4の一端
へ接続する第２スイツチング手段SW２と、前記
演算増幅器Ｍの出力端子と共通電位点とを切換え
て前記第３容量K1の他端へ接続する第４スイツ
チング手段SW４と、前記演算増幅器Ｍの反転入
力端子と共通電位点を切換えて、前記第３容量
K1の一端へ接続する第２スイツチング手段SW２
と、他端が共通電位点に接続された前記第５容量
K3の一端と共通電位点とを切換えて、前記第４
容量K2の他端へ接続する第５スイツチング手段
SW５と、前記演算増幅器Ｍの出力端子と共通電
位点を切換えて前記第４容量K2の一端へ接続す
る第４スイツチング手段SW４と、第６容量K6
と、第７容量C2と、第８容量C1と、前記信号入
力端子と前記第６容量K6の他端とを接続する第
７スイツチング手段SW７と、前記演算増幅器Ｍ
の反転入力端子と前記第６容量K6の一端とを接
続する第８スイツチング手段SW８と、前記演算
増幅器Ｍの反転入力端子と前記他端が共通電位点
に接続された前記第５容量K3の一端とを接続す
る第９スイツチング手段SW９と、前記演算増幅
器Ｍの出力端子と信号出力端子とを接続する第10
スイツチング手段SW１０と、前記演算増幅器Ｍ
の反転入力端子に前記第７、第８容量C1，C2の
他端が接続される構成と、前記第７容量C1の一
端と前記第８容量C2の一端とを切換えて前記演
算増幅器Ｍの出力端子に接続する第６スイツチン
グ手段SW６とを備え、前記各スイツチング手段
は２相クロツクで、駆動され、且つ第１及び第３
スイツチング手段とからなる組と、第２、第４及
び第５スイツチング手段とからなる組とは逆相関
係で共通電位点に接続され、第６スイツチング手
段は第１及び第３スイツチング手段とからなる組
と同相関係にあり、第７、第８及び第10スイツチ
ング手段とからなる組は第１及び第３スイツチン
グ手段とからなる組と同相関係にあり、且つ第９
スイツチング手段は第２、第４及び第５スイツチ
ング手段と同相関係にあることを特徴とするスイ
ツトキヤパシタ振幅等化器。1 an operational amplifier M whose non-inverting input terminal is connected to a common potential point, a first capacitor K5 , a second capacitor K4 , and a third capacitor
By switching the capacitor K 1 , the fourth capacitor K 2 , the fifth capacitor K 3 , the signal input terminal and the common potential point, the first capacitor K 5
First switching means SW1 connected to the other end
and a second switching means SW2 that switches the inverting input terminal of the operational amplifier M and the common potential point to connect it to one end of the first capacitor K5 , and switches the output terminal of the operational amplifier M and the common potential point. and a second switching means SW3 that switches a common potential point with the inverting input terminal of the operational amplifier M and connects it to one end of the first capacitor K4 . means SW2, fourth switching means SW4 for switching the output terminal of the operational amplifier M and the common potential point and connecting it to the other end of the third capacitor K1 , and the inverting input terminal of the operational amplifier M and the common potential point. and the third capacity
Second switching means SW2 connected to one end of K1
and the fifth capacitor whose other end is connected to a common potential point.
By switching one end of K 3 and the common potential point, the fourth
Fifth switching means connected to the other end of the capacitor K2
SW5, a fourth switching means SW4 that switches the potential point common to the output terminal of the operational amplifier M and connects it to one end of the fourth capacitor K2 , and a sixth capacitor K6.
, a seventh capacitor C 2 , an eighth capacitor C 1 , a seventh switching means SW7 for connecting the signal input terminal and the other end of the sixth capacitor K 6 , and the operational amplifier M
an eighth switching means SW8 that connects the inverting input terminal of the operational amplifier M to one end of the sixth capacitor K6 , and the fifth capacitor K3 that connects the inverting input terminal of the operational amplifier M and the other end to a common potential point. a ninth switching means SW9 for connecting one end of the operational amplifier M; and a tenth switching means SW9 for connecting the output terminal of the operational amplifier M and the signal output terminal.
switching means SW10 and the operational amplifier M
The other ends of the seventh and eighth capacitors C1 and C2 are connected to the inverting input terminal of and a sixth switching means SW6 connected to the output terminal of the amplifier M, each switching means being driven by a two-phase clock and having a first and a third switching means.
The set consisting of the switching means and the set consisting of the second, fourth and fifth switching means are connected to a common potential point in an inverse phase relationship, and the sixth switching means consists of the first and third switching means. The set consisting of the seventh, eighth and tenth switching means is in phase with the set consisting of the first and third switching means, and the ninth switching means is in phase with the set consisting of the first and third switching means.
A switch capacitor amplitude equalizer characterized in that the switching means is in phase with the second, fourth and fifth switching means.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20487183A JPS6097714A (en) | 1983-11-02 | 1983-11-02 | Amplitude equalizer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20487183A JPS6097714A (en) | 1983-11-02 | 1983-11-02 | Amplitude equalizer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6097714A JPS6097714A (en) | 1985-05-31 |
| JPH0425726B2 true JPH0425726B2 (en) | 1992-05-01 |
Family
ID=16497776
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20487183A Granted JPS6097714A (en) | 1983-11-02 | 1983-11-02 | Amplitude equalizer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6097714A (en) |
-
1983
- 1983-11-02 JP JP20487183A patent/JPS6097714A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6097714A (en) | 1985-05-31 |
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