JPH0425744B2 - - Google Patents
Info
- Publication number
- JPH0425744B2 JPH0425744B2 JP58070477A JP7047783A JPH0425744B2 JP H0425744 B2 JPH0425744 B2 JP H0425744B2 JP 58070477 A JP58070477 A JP 58070477A JP 7047783 A JP7047783 A JP 7047783A JP H0425744 B2 JPH0425744 B2 JP H0425744B2
- Authority
- JP
- Japan
- Prior art keywords
- signal
- signals
- detection
- phase
- multiplying
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
- H04L27/22—Demodulator circuits; Receiver circuits
- H04L27/233—Demodulator circuits; Receiver circuits using non-coherent demodulation
- H04L27/2332—Demodulator circuits; Receiver circuits using non-coherent demodulation using a non-coherent carrier
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Description
【発明の詳細な説明】
本発明は4相位相変調された信号を遅延検波回
る回路に係り、特に集積回路化に適した検波回路
に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit for delay detection of a signal subjected to four-phase phase modulation, and particularly to a detection circuit suitable for integration into an integrated circuit.
従来知られている遅延検波回路は、中間周波数
帯で使用するものであり、集積回路化に適さない
という欠点があつた。 Conventionally known delay detection circuits are used in intermediate frequency bands and have the disadvantage of being unsuitable for integration into integrated circuits.
本発明の目的は、このような欠点を除いてベー
スバンド帯で信号処理を行うことで、集積回路化
を容易にする遅延検波回路を提供することにあ
る。 An object of the present invention is to provide a delay detection circuit that eliminates such drawbacks and performs signal processing in the baseband band, thereby facilitating integration into an integrated circuit.
本発明によれば、4相位相変調波を入力信号と
して、該入力変調波の中心周波数にほぼ等しい発
振周波数を有する局部発振器の出力から得られる
信号を局部発振信号とする第1の直交検波器と、
これに対して相対位相が45°の奇数倍だけ異なる
第2の直交検波器を有し、前記第1の直交検波器
の出力の二つのベースバンド信号を第1および第
2の信号とし、前記第2の直交検波器の出力の直
交する二つのベースバンド信号を第3および第4
の信号とするとき、該第3および第4の信号がそ
れぞれ前記第1および第2の信号に対して遅延を
前記4相位相変調波のシンボル周期だけ異ならせ
る手段とを有し、前記第1の信号と前記第3の信
号を乗算した信号を第5の信号とし、前記第2の
信号と前記第4の信号を乗算した信号を第6の信
号とし、前記第1の信号と前記第4の信号を乗算
した信号を第7の信号とし、前記第2の信号と前
記第3の信号を乗算した信号を第8の信号とし、
前記第5の信号と前記第6の信号とを加算して得
られる信号を2値化し、これを第1の検波信号と
し、前記第7の信号と前記第8の信号との減算を
行つてから得られる信号を2値化し、これを第2
の検波信号とし、前記第1および第2の検波信号
の組み合わせから得られる4値の信号を検波出力
信号とすることによつて上記目的を達成できる。 According to the present invention, the first quadrature detector uses a four-phase modulated wave as an input signal and uses a signal obtained from the output of a local oscillator having an oscillation frequency approximately equal to the center frequency of the input modulated wave as a local oscillation signal. and,
On the other hand, a second quadrature detector whose relative phase differs by an odd multiple of 45° is provided, two baseband signals output from the first quadrature detector are used as first and second signals, and the The two orthogonal baseband signals output from the second orthogonal detector are
when the third and fourth signals each have a delay different from the first and second signals by the symbol period of the four-phase modulated wave, and the first A signal obtained by multiplying the signal and the third signal is defined as a fifth signal, a signal obtained by multiplying the second signal and the fourth signal is defined as a sixth signal, and a signal obtained by multiplying the signal by the fourth signal is defined as a sixth signal. A signal obtained by multiplying the signal by the third signal is set as a seventh signal, a signal obtained by multiplying the second signal and the third signal is set as an eighth signal,
A signal obtained by adding the fifth signal and the sixth signal is binarized, this is used as a first detection signal, and the seventh signal and the eighth signal are subtracted. Binarize the signal obtained from the
The above object can be achieved by using a detection signal as a detection signal and using a four-value signal obtained from a combination of the first and second detection signals as a detection output signal.
以下図面を用いて詳しい説明を行う。 A detailed explanation will be given below using the drawings.
第1図は本発明の実施例を示すブロツク図であ
る。同図の入力端子には複素振幅平面で第2図に
示すような位相変調波が入力される。このような
変調波は4相位相変調波として知られており、搬
送波の位相は、同図の丸印で示した点のうちいず
れかを4値の送信信号によつてとる。相続くシン
ボル時刻における位相変化は0°,±90°,180°のう
ちのいずれかであり、遅延検波とはこの4通りの
位相変化を検出することである。 FIG. 1 is a block diagram showing an embodiment of the present invention. A phase modulated wave as shown in FIG. 2 on a complex amplitude plane is input to the input terminal in the figure. Such a modulated wave is known as a four-phase modulated wave, and the phase of the carrier wave is determined by a four-value transmission signal at one of the points indicated by circles in the figure. The phase change at successive symbol times is one of 0°, ±90°, and 180°, and differential detection means detecting these four types of phase changes.
位相変調波は一般に次のように表わされる。 A phase modulated wave is generally expressed as follows.
V(t)=A(t)cos〔Wct+P(t) ……(1)
ここで、A(t)は振幅(A(t)≧0),Wcは
変調波の中心角周波数、P(t)は変調入力信号
によつて決まる位相である。この変調入力信号
は、そのまま入力される二つの信号と、遅延回路
5によつて遅延されてから入力される二つの信号
に分岐される。第1図の局部発振器2の出力は位
相差分離回路3により直交する信号の二つの組、
すなわち0°と90°および45°と135°の組に分離され
る。4つに分岐された入力信号は、それぞれこれ
に対応して分離された4つの局部発振信号とミク
サ31,32,33,34によりベースバンド帯
に周波数変換され、雑音制限および妨害波除去の
ための低域通過フイルタ41,42,43,44
に入力される。その出力信号はそれぞれ次のよう
に表わすことができる。 V(t)=A(t)cos[Wct+P(t)...(1) Here, A(t) is the amplitude (A(t)≧0), Wc is the center angular frequency of the modulated wave, P(t ) is the phase determined by the modulating input signal. This modulated input signal is branched into two signals: one is input as is, and the other is delayed by the delay circuit 5 and then input. The output of the local oscillator 2 in FIG.
That is, it is separated into pairs of 0° and 90° and 45° and 135°. The four branched input signals are frequency-converted to the baseband band by mixers 31, 32, 33, and 34, respectively, and are separated into four local oscillation signals corresponding to the four local oscillation signals, and are used to limit noise and remove interference waves. low pass filters 41, 42, 43, 44
is input. The output signals can be respectively expressed as follows.
γ1(t)=A(t)Bcos〔P(t)+ΔQ(t)〕 ……(2)
γ2(t)=A(t)Bsin〔P(t)+ΔQ(t)〕 ……(3)
γ3(t)=A(t−T)Bcos〔P(t−T)+ΔQ(t
−T)+45°−WcT ……(4)
γ4(t)=A(t−T)Bsin〔P(t−T)+ΔQ
(t−T)+45°−WcT ……(5)
ここで、Bは定数であり、ΔQ(t)は変調波の中
心周波数と局部発振周波数がわずかにずれている
ことによりゆつくり変化する位相項である。搬送
波の中心周波数Wc/2πはシンボル周波数1/T
よりもはるかに高く選ばれるのが普通であるの
で、位相項WcTは周期Tをわずかだけ調整する
ことにより、容易に2πとすることができる。従
つて以下ではこの項を無視する。 γ 1 (t)=A(t)Bcos[P(t)+ΔQ(t)] ……(2) γ 2 (t)=A(t)Bsin[P(t)+ΔQ(t)] ……( 3) γ 3 (t)=A(t-T)Bcos [P(t-T)+ΔQ(t
−T)+45°−WcT ……(4) γ 4 (t)=A(t−T)Bsin[P(t−T)+ΔQ
(t-T)+45°-WcT...(5) Here, B is a constant, and ΔQ(t) is the phase that slowly changes due to the slight deviation between the center frequency of the modulated wave and the local oscillation frequency. It is a term. The center frequency Wc/2π of the carrier wave is the symbol frequency 1/T
Since it is usually chosen to be much higher than , the phase term WcT can easily be set to 2π by adjusting the period T only slightly. Therefore, this term will be ignored below.
γ1(t)とγ3(t)を乗算回路61に入力して得られる
信号γB(t)およびγ2(t)とγ4(t)を乗算回路62に入力
して得られる信号ζ4(t)は各々次のように与えられ
る。 A signal γ B (t) obtained by inputting γ 1 (t) and γ 3 (t) to the multiplication circuit 61 and a signal obtained by inputting γ 2 (t) and γ 4 (t) to the multiplication circuit 62 ζ 4 (t) are given as follows.
γ13(t)=γ1(t)γ3(t)
=1/2A(t−T)B2cos〔P(t−T)−P
(t)
+ΔQ(t−T)−ΔQ(t)+45°〕
+1/2A(t−T)B2cos〔P(t−T)
+P(t)+ΔQ(t−T)+ΔQ(t)+45°〕
……(6)
γ24(t)=γ2(t)γ4(t)
=1/2A(t−T)A(t)B2cos〔P(t−T)
−P(t)+ΔQ(t−T)−ΔQ(t)+45°〕
−1/2A(t−T)A(t)B2cos〔P(t−T)
+P(t)+ΔQ(t−T)+ΔQ(t)+45°〕
……(7)
γ13(t)とγ24(t)を加算回路71に入力して得られ
る信号γd1(t)は次のようになる。 γ 13 (t)=γ 1 (t)γ 3 (t) = 1/2A(t-T) B 2 cos [P(t-T)-P (t) +ΔQ(t-T)-ΔQ(t )+45°] +1/2A(t-T)B 2 cos[P(t-T) +P(t)+ΔQ(t-T)+ΔQ(t)+45°]
...(6) γ 24 (t)=γ 2 (t)γ 4 (t) = 1/2A(t-T)A(t)B 2 cos [P(t-T) −P(t)+ΔQ (t-T)-ΔQ(t)+45°] -1/2A(t-T)A(t)B 2 cos[P(t-T) +P(t)+ΔQ(t-T)+ΔQ(t) +45°〕
...(7) The signal γ d1 (t) obtained by inputting γ 13 (t) and γ 24 (t) to the adder circuit 71 is as follows.
γd1(t)=A(t−T)A(t)B2cos〔P(t−T)
−P(t)+ΔQ(t−T)−ΔQ(t)+45°〕
……(8)
同様にγ1(t)とγ4(t)を乗算回路63に入力し、γ2
(t)とγ3(t)を乗算回路64に入力して得られる信号
を減算回路72に入力することにより、その出力
信号γd2(t)は次のようになる。 γ d1 (t)=A(t-T)A(t)B 2 cos [P(t-T) −P(t)+ΔQ(t-T)−ΔQ(t)+45°]
...(8) Similarly, γ 1 (t) and γ 4 (t) are input to the multiplier circuit 63, and γ 2
(t) and γ 3 (t) are input to the multiplier circuit 64 and the resulting signal is input to the subtraction circuit 72, so that the output signal γ d2 (t) is as follows.
γd2(t)=A(t−T)A(t)B2sin〔P(t−T)
−P(t)+ΔQ(t−T)−ΔQ(t)+45°〕
……(9)
局部発振周波数が変調波の中心周波数とほぼ等
しいときには、位相項ΔQ(t−T)−ΔQ(t)は小
さくて無視できる。このとき、
Vd1(t)≒A(t−T)A(t)B2cos
〔P(t−T)−P(t)+45°〕 ……(10)
Vd2(t)≒A(t−T)A(t)B2sin
〔P(t−T)−P(t)+45°〕 ……(11)
となる。遅延時間Tはシンボル周期に等しく選ば
れるので、位相項P(t−T)−P(t)は送信信号
に応じて第3図の丸印で示したように0°,±90°,
180°のいずれかの点をとるので、これに45°を加
えた信号Vd1(t),Vd2(t)の位相は第3図のX印で
示したような位相をとる。これにより、信号Vd1
(t)およびVd2(t)をそれぞれ極性判定回路81,8
2に入力して出力端子91,92に得られる信号
X(t),Y(t)から位相差P(t−T)−P(t)が第4
図のように求まり、遅延検波が行われることが示
された。 γ d2 (t)=A(t-T)A(t)B 2 sin [P(t-T) −P(t)+ΔQ(t-T)−ΔQ(t)+45°]
...(9) When the local oscillation frequency is approximately equal to the center frequency of the modulated wave, the phase term ΔQ(t-T)−ΔQ(t) is small and can be ignored. At this time, V d1 (t)≒A(t-T)A(t)B 2 cos [P(t-T)-P(t)+45°] ...(10) V d2 (t)≒A( t-T)A(t)B 2 sin [P(t-T)-P(t)+45°] ...(11) Since the delay time T is chosen to be equal to the symbol period, the phase term P(t-T)-P(t) varies as 0°, ±90°,
Since any point within 180° is taken, the phases of the signals V d1 (t) and V d2 (t) obtained by adding 45° to this point are as shown by the X mark in FIG. This causes the signal V d1
(t) and V d2 (t) by polarity determination circuits 81 and 8, respectively.
2 and obtained at the output terminals 91 and 92, the phase difference P(t-T)-P(t) is the fourth
It was found as shown in the figure, indicating that delayed detection was performed.
この実施例においては、局部発振信号の直交す
る信号の二つの組、すなわち0°と90°の組と45°と
135°の組の間の位相差は45°としたけれども、第
3図からも明らかのように、45°の奇数倍の値と
しても、第4図に示した関係が変化するのみで、
同様に検波出力を得ることができる。また、この
45°の奇数倍の位相差、あるいは同相と直交の検
波を行うための90°位相差を得るためには、この
実施例におけるように局部発振信号の間に位相差
を与える代りに入力変調波信号の間に位相差を与
えてもよいことはよく知られている事実である。
また、遅延回路5は高周波帯に設けるのではな
く、ミクサ33と乗算回路61の間およびミクサ
34と乗算回路62の間のベースバンド帯に独立
に2個設けてもよいことは自明である。さらに、
雑音が存在する実際の場合には、極性判定回路8
1,82の出力を雑音の影響が最も少ない時刻で
サンプルする必要があるけれど基本的な動作には
関係ないので、ここでは説明を省略した。 In this example, two sets of orthogonal signals of the local oscillator signal are used, namely a set of 0° and 90° and a set of 45° and
Although the phase difference between the 135° pairs was set to 45°, as is clear from Figure 3, even if the value is an odd multiple of 45°, the relationship shown in Figure 4 will only change.
Similarly, the detection output can be obtained. Also, this
In order to obtain a phase difference of an odd multiple of 45° or a 90° phase difference for in-phase and quadrature detection, instead of providing a phase difference between the local oscillation signals as in this example, the input modulated wave It is a well-known fact that a phase difference may be provided between signals.
Furthermore, it is obvious that two delay circuits 5 may be provided independently in the baseband band between the mixer 33 and the multiplier circuit 61 and between the mixer 34 and the multiplier circuit 62 instead of providing them in the high frequency band. moreover,
In the actual case where noise is present, the polarity determination circuit 8
Although it is necessary to sample the outputs of 1 and 82 at a time when the influence of noise is least, it is not related to the basic operation, so the explanation is omitted here.
以上説明したように、本発明はダイレクトコン
バージヨン方式を用いて遅延検波を行うことがで
きるので集積回路化を容易にする効果がある。 As explained above, since the present invention can perform delayed detection using the direct conversion method, it has the effect of facilitating integration into an integrated circuit.
第1図は本発明の実施例を示すブロツク図、第
2図は本発明の対象とする4相位相変調波の信号
点を示す図、第3図は本発明の動作を説明するた
めに信号点を複素振幅平面に示した図、第4図は
二つの検波出力信号と位相変化の関係を示す図で
ある。これらの図において、1は入力端子、2は
局部発振器、3は位相差分離回路、31,32,
33,34はミクサ、41,42,43,44は
低域通過フイルタ、5は遅延回路、61,62,
63,64は乗算回路、71は加算回路、72は
減算回路、81,82は極性判定回路、91,9
2は検波出力端子である。
FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing signal points of a four-phase phase modulated wave targeted by the present invention, and FIG. 3 is a diagram showing signal points for explaining the operation of the present invention. FIG. 4, which is a diagram showing points on a complex amplitude plane, is a diagram showing the relationship between two detected output signals and phase changes. In these figures, 1 is an input terminal, 2 is a local oscillator, 3 is a phase difference separation circuit, 31, 32,
33, 34 are mixers, 41, 42, 43, 44 are low-pass filters, 5 is a delay circuit, 61, 62,
63 and 64 are multiplication circuits, 71 is an addition circuit, 72 is a subtraction circuit, 81 and 82 are polarity determination circuits, 91 and 9
2 is a detection output terminal.
Claims (1)
調波の中心周波数にほぼ等しい発振周波数を有す
る局部発振器の出力から得られる信号を局部発振
信号とする第1の直交検波器と、これに対して相
対位相が45°の奇数倍だけ異なる第2の直交検波
器を有し、第1の直交検波器のベースバンド信号
を第1および第2の信号とし、前記第2の直交検
波器の出力のベースバンド信号を第3および第4
の信号とするとき、該第3および第4の信号がそ
れぞれ前記第1および第2の信号に対して遅延を
前記4相位相変調波のシンボル周期だけ異ならせ
る手段を有し、前記第1の信号と、前記第3の信
号を乗算した信号を第5の信号とし、前記第2の
信号と前記第4の信号を乗算した信号を第6の信
号とし、前記第1の信号と前記第4の信号を乗算
した信号を第7の信号とし、前記第2の信号と前
記第3の信号を乗算した信号を第8の信号とし、
前記第5の信号と前記第6の信号とを加算して得
られる信号を2値化し、これを第1の検波信号と
し、前記第7の信号と前記第8の信号との減算を
行つて得られる信号を2値化し、これを第2の検
波信号とし、前記第1および第2の検波信号の組
み合わせから得られる4値の信号を検波出力信号
とすることを特徴とする遅延検波回路。1. A first quadrature detector which uses a four-phase phase modulated wave as an input signal and whose local oscillation signal is a signal obtained from the output of a local oscillator having an oscillation frequency approximately equal to the center frequency of the input modulated wave; a second quadrature detector whose relative phase differs by an odd multiple of 45°, the baseband signals of the first quadrature detector are used as first and second signals, and the output of the second quadrature detector is The baseband signals of the third and fourth
, the third and fourth signals have means for making the delays different from the first and second signals by the symbol period of the four-phase modulated wave, and the first A signal obtained by multiplying the signal by the third signal is defined as a fifth signal, a signal obtained by multiplying the second signal by the fourth signal is defined as a sixth signal, and a signal obtained by multiplying the signal by the fourth signal is defined as a sixth signal. A signal obtained by multiplying the signals of is set as a seventh signal, a signal obtained by multiplying the second signal and the third signal is set as an eighth signal,
A signal obtained by adding the fifth signal and the sixth signal is binarized, this is used as a first detection signal, and the seventh signal and the eighth signal are subtracted. A delay detection circuit characterized in that the obtained signal is binarized, this is used as a second detection signal, and a four-value signal obtained from a combination of the first and second detection signals is used as a detection output signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58070477A JPS59196653A (en) | 1983-04-21 | 1983-04-21 | Delay detecting circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58070477A JPS59196653A (en) | 1983-04-21 | 1983-04-21 | Delay detecting circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59196653A JPS59196653A (en) | 1984-11-08 |
| JPH0425744B2 true JPH0425744B2 (en) | 1992-05-01 |
Family
ID=13432638
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58070477A Granted JPS59196653A (en) | 1983-04-21 | 1983-04-21 | Delay detecting circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59196653A (en) |
-
1983
- 1983-04-21 JP JP58070477A patent/JPS59196653A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59196653A (en) | 1984-11-08 |
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