JPH04258179A - Manufacture of photodetector with built-in circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in the structure of a light-receiving element having a built-in signal processing circuit that increases the photosensitivity and speeds up the response speed.

0002

2. Description of the Related Art Photodetectors with built-in circuits are widely used in optical sensors, photocouplers, and the like. FIG. 6 is a schematic cross-sectional view of an example of the structure of a conventional general light-receiving element with a built-in circuit. In the figure, a photodiode A, which is a light receiving element, and an NPN transistor B, which is a signal processing circuit element, are formed on a single semiconductor substrate 1 of a first conductivity type, for example, a P type. The photodiode A includes a second conductivity type, for example, an N-type buried diffusion layer 2 buried in a P-type semiconductor substrate 1, an N-type epitaxial layer 4 grown thereon, and a P-type diffusion layer 6 on the surface thereof (a photodiode A). Anode of the diode), an N-type compensation diffusion layer 5 (cathode of the photodiode) extending from the surface to the N-type buried diffusion layer 2, and the like. NPN transistor B consists of an N-type buried diffusion layer 2-1 buried in a P-type semiconductor substrate 1, an N-type epitaxial layer 4-1 grown thereon, and a P-type diffusion layer 6-1 (transistor) on the surface of the N-type buried diffusion layer 2-1. (base), an N-type diffusion layer 7 (emitter of the transistor) therein, and an N-type compensation diffusion layer 5-1 (collector of the transistor) extending from the surface to the N-type buried diffusion layer 2-1. The photodiode A and the NPN transistor B and other signal processing circuit elements are separated by element isolation P-type diffusion layers 3, 3, . . . .

In the structure shown in FIG. 6 described above, the N-type epitaxial layer 4 of the photodiode A and the N-type epitaxial layer 4-1 of the NPN transistor B are formed at the same time, so their thicknesses are the same. It has become.

[0004] Due to recent demands for faster data transmission, improved S/N ratios, etc., it is desired that light receiving elements with a built-in circuit have higher light sensitivity and faster response speed.

In order to increase the light sensitivity, photodiode A
It is necessary to make the thickness of the N-type epitaxial layer 4 in the portion sufficiently thick according to the wavelength of the light used for the signal. However, if the N-type epitaxial layer 4 is made too thick, it takes a long time for the generated photocarriers to travel through the portions of this layer that are not depleted layers due to diffusion, which impedes an increase in response speed. Also, if the thickness of the N-type epitaxial layer 4 is increased, the PNP transistor B formed at the same time
The thickness of the N-type epitaxial layer 4-1 at the portion 4-1 also increases, leading to an increase in the collector resistance of the NPN transistor, which becomes an obstacle to increasing the response speed.

On the other hand, in order to increase the response speed of the photodetector with a built-in circuit, it is effective to reduce the junction capacitance of the photodiode A, and for this purpose, it is necessary to increase the specific resistance of the N-type epitaxial layer 4. be. But then N
N-type epitaxial layer 4- in the part of PN transistor B
The specific resistance of the NPN transistor B also increases, and the collector resistance of the NPN transistor B increases, which results in the opposite of increasing the response speed.

From the above, in order to achieve both high photosensitivity and high response speed of the light-receiving element with a built-in circuit, the N-type epitaxial layer 4 in the photodiode A portion must have a high specific resistance and be thick, and the NPN transistor B Ideally, the N-type epitaxial layer 4-1 in the portion 4-1 should have a low resistivity and be thin.

A structure that satisfies the above conditions is shown in FIG. This is the applicant's April 1, 1999
This was disclosed in Japanese Patent Application No. 1-93991 filed on the 3rd.

That is, the photodiode A is constructed by embedding a first N-type buried diffusion layer 2 in a P-type semiconductor substrate 1, and then forming a first high-resistivity N-type epitaxial layer (i in the sense that it is close to an intrinsic semiconductor). After forming the second N-type buried diffusion layer 10 only under the region where the N-type compensation diffusion layer 5 is planned to be formed in this layer, the second N-type high specific resistance epitaxial layer 11 is formed. The second N-type buried diffusion layer 10 is laminated from the surface.
An N-type compensating diffusion layer 5 is formed to reach a maximum of
It has a structure in which a type diffusion layer 6 is formed.

The NPN transistor B is constructed by embedding a P-type buried diffusion layer 8 in a P-type semiconductor substrate 1, and then forming a first N-type high resistivity epitaxial layer 9 (in FIG. (not shown because it is compensated by the diffused P-type buried diffusion layer 8), a second N-type buried diffusion layer 10-1 is buried in this layer, and an N-type diffusion layer 13 is formed on top of the second N-type buried diffusion layer 10-1. (This N-type diffusion layer 13 is diffused into the second N-type high-resistivity epitaxial layer 11 by heat treatment after the growth of the second N-type high-resistivity epitaxial layer 11, which will be described later, as shown in FIG. 7. become). An N-type epitaxial layer 11 (not shown in FIG. 7 because it is compensated by an N-type well diffusion layer 12 as described later) is laminated thereon. This N-type high resistivity epitaxial layer 1
1 is compensated for by the N-type well diffusion layer 12 and the N-type diffusion layer 13, and then the N-type compensation diffusion layer 5-1, which becomes the collector, reaches from the surface to the second N-type buried diffusion layer 10-1, and further to the surface. It has a structure in which a P-type diffusion layer 6-1 serving as a base and an N-type diffusion layer 7 serving as an emitter are further formed in a part of the P-type diffusion layer 6-1.

In the structure shown in FIG. 7, in the photodiode A portion, the first and second N-type high resistivity epitaxial layers 9 and 11 stacked in two layers form a thick film epitaxial layer with high resistivity. layers are realized and N
In the part of the PN transistor B, the N-type well diffusion layer 12
Since the upper N-type high resistivity epitaxial layer portion compensated by becomes an effective epitaxial layer, a low resistivity and thin epitaxial layer is realized.

0012

However, in order to form the structure shown in FIG. 7, it is necessary to control the spread of each diffusion layer quite precisely. That is, if the upward spread of the first N-type buried diffusion layer 2 is too large, the effective thickness of the N-type high resistivity epitaxial layers 9 and 11 in the photodiode A portion becomes thinner. The spread of this first N-type buried diffusion layer 2 must be suppressed as much as possible.

[0013] Also, the second
If the N-type buried diffusion layer 10-1 diffuses too far downward,
Since a PN junction is formed in a portion of the P-type buried diffusion layer 8 with a high impurity concentration, the withstand voltage between the active island region of the NPN transistor B and the element isolation P-type diffusion layer 3 decreases, and this junction capacity will also increase. Second N-type buried diffusion layer 10-1
And if the upward spread of the N-type diffusion layer 13 is large, the N
The breakdown voltage BVCEO of the PN transistor B decreases. In order to meet these demands for the buried diffusion layer, it is desirable to reduce the number of heat treatment steps after laminating the upper second N-type high resistivity epitaxial layer 11. However, on the other hand,
In order to obtain good NPN transistor characteristics, the N-type well diffusion layer 12 and the N-type diffusion layer 13 need to be deeply formed with a relatively low impurity concentration and a uniform impurity concentration profile in the depth direction. Therefore, heat treatment at a considerably high temperature and for a long time was required, and it was difficult to avoid the above-mentioned deterioration of properties. Furthermore, when forming the N-type high-resistivity epitaxial layer 11, N-type impurities are auto-doped from the N-type diffusion layer 13, causing variations in the impurity concentration of the N-type high-resistivity epitaxial layer 11, resulting in deterioration of the characteristics of the photodiode. There was a problem.

[0014]

[Means for Solving the Problems] In order to solve the above-mentioned problem, the present invention provides an N-type high resistivity epitaxial layer for compensating the second N-type high resistivity epitaxial layer portion of the signal processing circuit section such as the NPN transistor B. The diffusion layer was formed by ion implantation so that the N-type impurity concentration was highest at the interface between the P-type diffusion layer serving as the base and the N-type high resistivity epitaxial layer.

[0015]

[Function] With the above-described structure, the heat treatment process required to form the N-type diffusion layer that compensates for the second N-type high resistivity epitaxial layer on the surface of the signal processing circuit section is unnecessary. Therefore, the spread of each diffusion layer can be suppressed, and a light receiving element with a built-in circuit as shown in FIG. 7 can be formed without causing characteristic deterioration of the signal processing circuit section. Also, P
Faster NPN than conventional ones with a uniform impurity concentration profile in the depth direction and suppressing the downward spread of the type diffusion layer
You can get a transistor.

Furthermore, a step of forming the N-type diffusion layer 13 and
The heat treatment process can be reduced, leading to cost reductions.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a schematic cross-sectional view of one embodiment of the present invention, and FIGS. 2, 3, 4, and 5 are schematic cross-sectional views of each step to obtain the structure of FIG.

For convenience of explaining the structure of FIG. 1, first, FIGS.
The process shown in FIG. 5 will be explained. First, as shown in FIG. 2, a first N-type buried diffusion layer 2 is formed in a region of a P-type semiconductor substrate 1 where a photodiode is to be formed, and a P-type buried diffusion layer 2 is formed in a region where a signal processing circuit is to be formed. Form layer 8.

Next, as shown in FIG. 3, after a first N-type high resistivity epitaxial layer 9 is laminated over the entire surface, a second N-type epitaxial layer 9 is deposited on the area where the cathode electrode of the photodiode is to be taken out and the area where the NPN transistor is to be formed. Mold buried diffusion layer 10,1
Form 0-1. Note that through these steps, the first N-type buried diffusion layer 2 and the P-type diffusion layer 8 are diffused vertically.

Next, as shown in FIG.
A type high resistivity epitaxial layer 11 is laminated over the entire surface, and an N type diffusion layer 12 is formed by ion implantation in a region where a signal processing circuit is to be formed. When forming the N-type diffusion layer 12, the position where the interface between the P-type diffusion layer 6-1, which will be the base to be formed later, and the second N-type high resistivity epitaxial layer 11 will be formed is the most In order to increase the N-type impurity concentration, N
Perform ion implantation of type impurities.

Furthermore, as shown in FIG. 5, there is an element isolation P-type diffusion layer 3, an N-type compensation diffusion layer 5 reaching from the surface to the second N-type buried diffusion layer 10, and a second N-type diffusion layer 5 extending from the surface to the second N-type buried diffusion layer 10. The N-type compensation diffusion layer 5-1 reaching the buried diffusion layer 10-1 is diffused. Thereafter, as shown in FIG. 1, the surface is covered with a P-type diffusion layer 6 for the anode of the photodiode, a P-type diffusion layer 6-1 for the base of the NPN transistor, and an N-type diffusion layer for the emitter.
A mold diffusion layer 7 is formed.

In the above embodiment, the ion implantation of the N type diffusion layer 12 was performed before the formation of the element isolation P type diffusion layer 3, but after the formation of the element isolation P type diffusion layer 3, the base It may be done before the formation of the P-type diffusion layer 6-1.

Furthermore, instead of the N-type high specific resistance epitaxial layer 9, an N-type high specific resistance substrate may be attached and used.

Furthermore, in the above embodiments, the conductivity type may be P type or N type as long as the operation of each element is possible.

[0025]

According to the present invention, the second N-type diffusion layer 10
, 10-1 can be heat-treated at a low temperature for a short time.
1 and the P-type buried diffusion layer 8 are as follows:
This can be determined at the time of forming the N-type diffusion layers 10 and 10-1, and the spread of each diffusion layer can be precisely controlled. therefore,
The characteristics of the signal processing circuit section are not deteriorated.

Further, since the downward spread of the base diffusion layer is suppressed, it is possible to obtain a faster-than-normal NPN transistor having a uniform impurity concentration profile in the depth direction.

Furthermore, the N-type diffusion layer 13 formation step and the N-type diffusion layer 13 formation step and
Since a heat treatment process for forming the mold diffusion layer 12 is not necessary, cost reduction can be achieved.

[Brief explanation of the drawing]

FIG. 1 is a schematic cross-sectional view of an embodiment of the invention.

2 is a schematic cross-sectional view of one step to obtain the structure of FIG. 1; FIG.

3 is a schematic cross-sectional view of one step to obtain the structure of FIG. 1; FIG.

4 is a schematic cross-sectional view showing one step for obtaining the structure of FIG. 1. FIG.

5 is a schematic cross-sectional view showing one step for obtaining the structure of FIG. 1. FIG.

FIG. 6 is a schematic cross-sectional view of an example of a conventional structure.

FIG. 7 is a schematic cross-sectional view of another example of a conventional structure.

[Explanation of symbols]

1 P-type semiconductor substrate 2 N-type buried diffusion layer 3 Element isolation P-type diffusion layer 4, 4-1 N-type epitaxial layer 5 N-type compensation diffusion layer 6, 6-1 P-type diffusion layer 7 N-type diffusion layer 8 P-type buried diffusion layers 9, 11 N-type high resistivity epitaxial layers 10, 10
-1 N-type buried diffusion layer 12 N-type diffusion layer A Photodiode B NPN transistor

Claims (1)

[Claims] 1. Consists of a light receiving element and a signal processing circuit provided on a high resistivity epitaxial layer of a first conductivity type formed on a semiconductor substrate, and a base layer of a second conductivity type of the signal processing circuit. The base of the first conductivity type high resistivity epitaxial layer is formed so that the impurity concentration is highest at the position where the interface of the first conductivity type high resistivity epitaxial layer is formed, thereby suppressing the spread of the base layer. An impurity diffusion layer of the first conductivity type is formed by ion implantation below the planned region, and a high resistivity epitaxial layer of the first conductivity type of the signal processing circuit section is compensated for to form a low resistivity layer of the first conductivity type. A method for manufacturing a light receiving element with a built-in circuit, comprising a step of forming an epitaxial layer.