JPH04258992A - Phase controller for liquid crystal driving timing signal - Google Patents

Abstract

PURPOSE:To adjust the phases of each horizontal timing signal for driving each liquid crystal panel device used for a three-plate type liquid crystal projector. CONSTITUTION:A first horizontal timing signal generating circuit 37 outputs a first horizontal timing signal to a first liquid crystal panel device 9, based on a horizontal synchronizing signal, and outputs a first phase control signal S1 to a first and a second phase control circuits 43, 45. A second and a third horizontal timing signal generating circuits 39, 41 output a second and a third horizontal timing signals to a second and a third liquid crystal panel devices 19, 21, based on horizontal synchronizing signals from a first and a second phase control circuits 43, 45, and output a second and a third phase control signals S2, S3 to a first and a second phase control circuits 43, 45. A first and a second phase control circuits 43, 45 slide a phase of the horizontal synchronizing signal and output it in accordance with a phase difference of a first phase control signal S1, and a second and a third phase control signals S2, S3.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase control device for a timing signal for driving a liquid crystal, and more particularly to an improvement in a phase control device suitable for use in a three-panel liquid crystal projector using three liquid crystal panel devices.

0002

BACKGROUND OF THE INVENTION Conventionally, as shown in FIG. 3, a three-panel liquid crystal projector of this type emits, for example, R (red) light and B (blue) light, respectively, on the optical axis from a lamp 1 that functions as a white light source. The dichroic mirrors 3 and 5 to be separated and the reflecting mirror 7 are arranged, and the dichroic mirror 5 and the reflecting mirror 7 are separated.
A first liquid crystal panel device (which controls G (green) light during
dichroic mirrors 13 and 15 that combine the B light and the G light on the optical axis of the reflected light from the reflecting mirror 11; A second liquid crystal panel device 19 for controlling the R light is disposed between the reflecting mirror 11 and the dichroic mirror 13, and a second liquid crystal panel device 19 for controlling the B light is disposed between the dichroic mirrors 5 and 13. 3
It has a configuration in which a liquid crystal panel device 21 is arranged.

[0003] In such a three-panel liquid crystal projector,
Separate the white light from lamp 1 into three primary colors and
- The third liquid crystal panel devices 9, 19, and 21 control the amount of light for each pixel, combine the lights, and project the lights from the lens 17 onto, for example, a screen (not shown) to form an image. For example, the first liquid crystal panel device 9 in a three-panel liquid crystal projector includes a shift register 23, a sample hold circuit 25, a vertical driver 27, and N pieces in the horizontal direction x M pieces in the vertical direction (symbols N and M are LCD panel 2 with pixels of (integer)
9.

The first liquid crystal panel device 9 is shown in FIG.
As shown in the figure, the shift register 23 shifts the horizontal shift clock CL1 synchronized with the horizontal start pulse P1 to pixels in the horizontal direction and outputs it to the sample and hold circuit 25, and the sample and hold circuit 25 samples and holds the video signal A of the G light. At the same time, latch and close the LCD panel 29.
A vertical shift clock synchronized with the vertical start pulse is sequentially outputted from the vertical driver 27 to the corresponding vertical pixel line of the liquid crystal panel 29 to block or transmit each pixel. Control the amount of light. second and third liquid crystal panel devices 19;
21 is also similar to the first liquid crystal panel device 9.

In the first to third liquid crystal panel devices 9, 19, and 21 used in such a three-panel liquid crystal projector, when the phases of the horizontal shift clocks that sample and hold the video signal are shifted from each other, the three primary colors at the imaging position are Since there is a risk that the phase lock may shift and cause a convergence shift, PLL (Phase Lock
A horizontal shift clock is formed and applied with phase synchronization using a dLoop circuit (not shown).

[0006]

[Problem to be solved by the invention] However, PLL
Even if a horizontal shift clock whose phase is matched to the horizontal synchronization signal is created in a circuit, due to variations in circuit elements forming the PLL circuit and phase errors in operation, the first to third liquid crystal panel devices 9, 19 , 21 is difficult to accurately match the phases of the horizontal shift clocks to the signals. Therefore, as shown in FIG. 5, with respect to the horizontal start pulse P1 and horizontal shift clock CL1 to the first liquid crystal panel device 9, the horizontal start pulses P2 and P3 to the second and third liquid crystal panel devices 19 and 21 are applied. and horizontal shift clocks CL2, CL3
If the phase of is advanced or delayed, the sample and hold points of the video signal in each of the first to third liquid crystal panel devices 9, 19, and 21 differ, resulting in a convergence shift and degrading the image quality. In particular, in large liquid crystal panel devices with an increased number of pixels, it is necessary to increase the horizontal shift clock frequency for sampling and holding, so if there is even a slight phase shift between the horizontal shift clocks CL1 to CL3,
Images are formed with each pixel shifted left and right, resulting in a decrease in image quality.

The present invention has been made in order to solve the above-mentioned conventional drawbacks, and it is possible to suppress the mutual phase shift of each timing signal supplied to a plurality of liquid crystal panel devices. The purpose is to provide a control device.

[Means for Solving the Problems] In order to solve such problems, the present invention provides phase control so that the phase difference between a first phase comparison signal formed from a horizontal synchronization signal and the horizontal synchronization signal is constant. a first horizontal timing signal generation circuit that outputs the first timing signal obtained as a video signal sampling clock to the first liquid crystal panel device; and a second phase comparison signal formed from the inputted horizontal synchronization signal. a second horizontal timing signal generation circuit that outputs a second timing signal whose phase is controlled so that the phase difference with the horizontal synchronization signal is constant to a second liquid crystal panel device as a video signal sampling clock; A third timing signal whose phase is controlled so that the phase difference between the third phase comparison signal formed from the horizontal synchronization signal and the horizontal synchronization signal is constant is used as a sampling clock of the video signal on the third liquid crystal panel. and a third horizontal timing signal generation circuit for outputting to the device.

[0008] Moreover, the first phase outputs the horizontal synchronization signal, which controls the phase of the horizontal synchronization signal so that the phase difference between the first and second phase comparison signals is constant, to the second horizontal timing signal generation circuit. a control circuit, and the first and third
The second phase control circuit controls the phase of the horizontal synchronization signal so that the phase difference between the phase comparison signals is constant, and outputs the horizontal synchronization signal to the third horizontal timing signal generation circuit.

[0009]

[Operation] In the present invention equipped with such a means, in the first to third horizontal timing signal generation circuits to which a horizontal synchronization signal is added, the first to third phase comparison signals and the horizontal synchronization signal are The first to third timing signals controlled so that the phase difference is constant are output to the first to third liquid crystal panel devices, while the first phase comparison signal is output to the first and second phase control circuits. added to.

In these first and second phase control circuits, the first phase comparison signal from the first horizontal timing signal generation circuit and the second and third phase comparison signals from the second and third horizontal timing signal generation circuits are controlled. The phase of the horizontal synchronizing signal is controlled so that the phase difference between the phase comparison signals of is constant, and the phase-controlled horizontal synchronizing signal is applied to the second and third horizontal timing signal generating circuits.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Examples of the present invention will be described below with reference to the drawings. Note that parts common to the conventional example are given the same reference numerals. FIG. 1 is a block diagram showing an embodiment of a phase control device according to the present invention. The first, second, and third vertical timing signal generation circuits 31, 33, and 35 to which the vertical synchronization signal separated from the composite television signal is input are connected to the first, second, and third vertical timing signal generating circuits 31, 33, and 35 to be described later
Second and third horizontal timing signal generation circuits 37, 3
9 and 41, and the vertical synchronization signal input thereto, generate first, second and third vertical timing signals formed by two of a vertical start pulse and a vertical shift clock. , a circuit for outputting to the second and third liquid crystal panel devices 9, 19, and 21. The horizontal synchronization signal separated from the composite television signal is connected to a first horizontal timing signal generation circuit 37 and phase shifters 47, 49 of first and second phase control circuits 43, 45.

As shown in FIG. 2, the first horizontal timing signal generation circuit 37 generates a phase difference between, for example, a horizontal synchronizing signal of 31.5 KHz (during sequential scanning) and a first phase comparison signal S1 of 31.5 KHz, which will be described later. A phase comparator 51 that compares and outputs a difference signal according to the phase difference, a low pass filter (hereinafter abbreviated as LPF) 53 that cuts high frequency components of the difference signal from this phase comparator 51, and a high frequency cut. A voltage controlled oscillator (hereinafter abbreviated as VCO) 55 which oscillates a pulse signal of approximately 20 MHz whose oscillation frequency is varied so as to keep the difference signal level constant according to the difference signal level generated by the oscillation pulse signal; a frequency divider 57 that outputs a first phase comparison signal S1 of 31.5 KHz to the phase comparator 51;
The PLL configuration includes a timing signal output circuit 59 that outputs timing signals as the horizontal start pulse P1 and horizontal shift clock CL1 from the frequency-divided signal from the frequency divider 57 to the first liquid crystal panel device 9.

The first liquid crystal panel device 9 is shown in FIG.
As shown in FIG. 2, it is formed from a shift register 23, a sample hold circuit 25, a vertical driver 27, and a liquid crystal panel 29, and receives timing from a first horizontal timing signal generation circuit 37 and a first vertical timing signal generation circuit 31. Driven by a signal. The same applies to the other second and third liquid crystal panel devices 19 and 21.

The timing signal output circuit 59 includes phase comparators 61 and 6 of the first and second phase control circuits 43 and 45.
3 and outputs the first phase comparison signal S1. The first phase control circuit 43 includes a phase comparator 61 that outputs a phase difference between signals from a timing signal output circuit 59 and a timing signal output circuit 75 (described later), and an LPF 65 that cuts high-frequency components of the difference signal. A shifter that shifts (slides) the phase of the horizontal synchronizing signal in accordance with the high-frequency cut difference signal level so that the difference signal level becomes constant and outputs it to the phase comparator 67 of the second horizontal timing signal generation circuit 39. It is formed from a phaser 47.

The second horizontal timing signal generation circuit 39, like the first horizontal timing signal generation circuit 37, includes a phase comparator 67, an LPF 69, a VCO 71, 31.
Frequency divider 7 outputting the second phase comparison signal S2 of 5KHz
3, horizontal start pulse P2 and horizontal shift clock C
The PLL configuration includes a timing signal output circuit 75 that outputs a second timing signal as L2 to the second liquid crystal panel device 19. The timing signal output circuit 75 outputs a signal having the same frequency as the second phase comparison signal S2 to the phase comparator 61 of the first phase control circuit 43. The second liquid crystal panel device 19 is driven by timing signals from the second horizontal timing signal generation circuit 39 and the second vertical timing signal generation circuit 33.

The second phase control circuit 45 includes a timing signal output circuit 59 and a timing signal output circuit 87 to be described later.
a phase comparator 63 that outputs the phase difference of the signals from the signal, an LPF 77 that cuts the high-frequency components of the difference signal, and a horizontal synchronizer that keeps the difference signal level constant according to the high-frequency cut difference signal level. It is formed of a phase shifter 49 that shifts the phase of the signal and outputs it to the phase comparator 79 of the third horizontal timing signal generation circuit 41. Similarly to the second horizontal timing signal generation circuit 39, the third horizontal timing signal generation circuit 41 includes a phase comparator 79, an LPF 81, and a V
CO83 and a third phase comparison signal S3 of 31.5KHz
It has a PLL configuration formed by a frequency divider 85 that outputs the horizontal start pulse P3 and a timing signal output circuit 87 that outputs a third timing signal as the horizontal shift clock CL3 to the third liquid crystal panel device 21. There is.

The timing signal output circuit 87 outputs a signal having the same frequency as the third phase comparison signal S3 to the phase comparator 63 of the second phase control circuit 45. The third liquid crystal panel device 21 is driven by timing signals from the third horizontal timing signal generation circuit 41 and the third vertical timing signal generation circuit 35. In addition, the LPF in Figure 2
65 and 77 are shown included in the phase comparators 61 and 63 in FIG.

The operation of the above-mentioned phase control device of the present invention will be explained below. First, the operation of the first liquid crystal panel device 9 will be explained. The horizontal synchronization signal separated from the composite television signal is applied to the first horizontal timing signal generation circuit 37, and the phase difference between the horizontal synchronization signal and the first phase comparison signal S1 formed based on the horizontal synchronization signal becomes constant. YoniP
The LL phase is controlled, and a first timing signal as the horizontal start pulse P1 and horizontal shift clock CL1 is output from the timing signal output circuit 59 to the first liquid crystal panel device 9. A vertical synchronization signal is applied to the first vertical timing signal generation circuit 31, and the first vertical timing signal as a vertical start pulse or vertical shift clock synchronized with the horizontal synchronization signal and the vertical synchronization signal is applied to the first liquid crystal panel device 9. The first horizontal and vertical timing signals drive the first liquid crystal panel device 9.

Next, the operation of the second liquid crystal panel device 19 will be explained. The horizontal synchronization signal input via the first phase control circuit 43 is transmitted to the second horizontal timing signal generation circuit 39.
PLL phase control is performed so that the phase difference with the horizontal synchronization signal and the second phase comparison signal S2 formed based on this signal is constant, and the second signal as the horizontal start pulse P2 and the horizontal shift clock CL2 is The timing signal is output from the timing signal output circuit 75 to the second liquid crystal panel device 19. Moreover, the second phase comparison signal S2 is applied from the timing signal output circuit 75 to the phase comparator 61, which outputs the phase difference between the first and second phase comparison signals S1 and S2, and the LPF 65 outputs the phase difference between the first and second phase comparison signals S1 and S2. The phase shifter 47 slides the phase of the horizontal synchronizing signal so that the difference signal level is constant according to the high-frequency cut difference signal level, and the signal is sent to the phase comparator 67 of the second horizontal timing signal generation circuit 39. Added.

Therefore, the phase of the second timing signal outputted from the second horizontal timing signal generation circuit 39 to the second liquid crystal panel device 19 is the same as the first phase from the first horizontal timing signal generation circuit 37. The phase is controlled to match the comparison signal S1. On the other hand, in the second vertical timing signal generation circuit 33, a second vertical timing signal synchronized with the horizontal synchronization signal and the vertical synchronization signal is outputted to the second liquid crystal panel device 19, and the second horizontal and vertical timing signals are outputted to the second liquid crystal panel device 19. The second liquid crystal panel device 19 is driven by this.

Furthermore, the operation of the third liquid crystal panel device 21 will be explained. The horizontal synchronization signal inputted via the second phase control circuit 45 is transmitted to the third horizontal timing signal generation circuit 4.
1 and a second horizontal timing signal generation circuit 39
Similarly, a third timing signal subjected to PLL phase control is output from the timing signal output circuit 87 to the third liquid crystal panel device 21. Additionally, the timing signal output circuit 87
The third phase comparison signal S3 is applied to the phase comparator 63, which outputs the phase difference between the first and third phase comparison signals S1 and S3, and the LPF 77 outputs a difference signal with high frequency cut. Depending on the level, the phase shifter 49 slides the phase of the horizontal synchronizing signal so that the difference signal level is constant, and is applied to the phase comparator 79 of the third horizontal timing signal generating circuit 41.

Therefore, the phase of the third timing signal outputted from the third horizontal timing signal generation circuit 41 to the third liquid crystal panel device 21 is different from that of the first phase comparison signal S1.
The phase is controlled to match. On the other hand, in the third vertical timing signal generation circuit 35, a third vertical timing signal synchronized with the horizontal synchronization signal and the vertical synchronization signal is generated as a third vertical timing signal.
The third horizontal and vertical timing signals drive the third liquid crystal panel device 21.

As described above, in the above-mentioned liquid crystal drive timing signal phase control device, when the first horizontal timing signal to the first liquid crystal panel device 9 is subjected to PLL phase control based on the horizontal synchronization signal and outputted, The first phase comparison signal S1 generated in the first and second phase control circuits 43,
45, these first and second phase control circuits 43
, 45, the second and third liquid crystal panel devices 19, 2
The phase of the second and third horizontal timing signals to 1 is compared with the second and third phase comparison signals S2 and S3 that are created when outputting the PLL phase control based on the horizontal synchronization signal, and Since PLL phase control is performed by shifting the phase of the horizontal synchronizing signal so that the phase difference is constant, the second and third horizontal timing signals are controlled to match the phase of the first horizontal timing signal. Therefore, the first
Since the third liquid crystal panel devices 9, 19, and 21 each operate by sampling the same point of the video signal, a three-panel liquid crystal projector using these first to third liquid crystal panel devices 9, 19, and 21 operates by sampling the same point of the video signal. Color shift in reproduced images is less likely to occur.

[0024]

As described above, the present invention provides PLL phase control of the first to third horizontal timing signals applied to the first to third liquid crystal panel devices, and
Since the second and third horizontal timing signals are each formed from the horizontal synchronization signal whose phase is slid according to the phase difference with the horizontal timing signal, the second and third horizontal timing signals are different from the first horizontal timing signal. is controlled to match the phase of the horizontal timing signal. Therefore, these first
~first driven by third horizontal timing signal~
Since the third liquid crystal panel device samples the same point of the video signal, a three-panel liquid crystal projector using these first to third liquid crystal panel devices is less likely to cause color shift in the reproduced image, maintaining high image quality. can. In particular, the present invention is particularly useful since it is necessary to increase the frequency of the first to third horizontal timing signals when the first to third liquid crystal panel devices are increased in size.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a phase control device for a timing signal for driving a liquid crystal according to the present invention.

FIG. 2 is a block diagram showing first to third horizontal timing signal generation circuits and first and second phase control circuits in FIG. 1;

FIG. 3 is a schematic diagram showing the configuration of a three-panel liquid crystal projector.

FIG. 4 is a diagram schematically showing a liquid crystal panel device.

FIG. 5 is a diagram showing the operation of the liquid crystal panel device.

[Explanation of symbols]

1 Lamps 3, 5, 13, 15 Dichroic mirrors 7, 11
Reflection mirror 9 First liquid crystal panel device 17 Lens 19 Second liquid crystal panel device 21 Third liquid crystal panel device 23 Shift register 25 Sample hold circuit 27 Vertical driver 29 Liquid crystal panels 31, 33, 35 First, second and third 3 vertical timing signal generation circuits 37, 39, 41 first, second and third horizontal timing signal generation circuits 43, 45 first and second phase control circuits 47, 4
9 Phase shifters 51, 61, 63, 67, 79 Phase comparators 53, 6
5, 69, 77, 81 LPF55, 71, 83
VCO 57, 73, 85 Frequency divider

Claims (1)

[Claims] Claim 1: A first timing signal whose phase is controlled so that the phase difference between a first phase comparison signal formed from a horizontal synchronization signal and the horizontal synchronization signal is constant is used as a sampling clock of a video signal. A first horizontal timing signal generation circuit outputs to a liquid crystal panel device, and a second phase comparison signal formed from the input horizontal synchronization signal is phase-controlled so that the phase difference between the horizontal synchronization signal and the horizontal synchronization signal is constant. A second horizontal timing signal generation circuit outputs a second timing signal as a sampling clock of a video signal to a second liquid crystal panel device, and the phase difference between the first and second phase comparison signals is kept constant. a first phase control circuit that controls the phase of the horizontal synchronization signal and outputs the horizontal synchronization signal to the second horizontal timing signal generation circuit; and a third phase comparison formed from the input horizontal synchronization signal. a third horizontal timing signal generation circuit that outputs a third timing signal whose phase is controlled so that the phase difference between the signal and its horizontal synchronization signal is constant to a third liquid crystal panel device as a sampling clock of the video signal; , a second control circuit that controls the phase of the horizontal synchronization signal so that the phase difference between the first and third phase comparison signals is constant, and outputs the horizontal synchronization signal to the third horizontal timing signal generation circuit; 1. A phase control device for a timing signal for driving a liquid crystal, comprising a phase control circuit.