JPH04259258A - Manufacture of mis field effect semiconductor device - Google Patents

Abstract

PURPOSE:To provide a manufacturing method which can form a MIS field effect semiconductor device having an LDD(Lightly Doped Drain) structure in a self-alignment manner, and prevent deterioration of electric characteristic even in the case of a miniaturization. CONSTITUTION:A low concentration impurity region is formed in a P-type semiconductor substrate 100, a high concentration impurity region is formed in the low impurity region, a recess is formed on the low and high concentration impurity regions to divide the high concentration region to 106, 108, sidewalls are formed on part of a bottom and sidewall of the recess, with the sidewall as a mask a channel region 110 is formed in the low concentration region in the bottom of the recess, the low concentration region is divided into 102, 104, and a gate electrode 114 is formed on surfaces of low and high concentration regions 102, 104, 106, 108 of the sidewall, bottom of the recess, and the region 110 through a gate insulating film 112.

Description

[Detailed description of the invention]

0001

[Industrial Field of Application] This invention relates to LDD (Light
The present invention relates to a method of manufacturing a MIS field effect semiconductor device having a ly Doped Drain structure.

0002

2. Description of the Related Art Integrated circuits made of MIS field effect semiconductor devices can be highly integrated compared to integrated circuits made of bipolar elements. For this reason, MIS field effect semiconductor devices are widely used in electronic circuits.

However, as the miniaturization of such MIS field effect semiconductor devices progresses, the electric field concentrates near the drain, so a large number of hot carriers are formed in the area where the electric field is concentrated, and these hot carriers It is captured by the gate insulating film. Therefore, the electrical conductivity of the drain region and the channel region changes, causing a decrease in the drain current and a decrease in the threshold (Threshold).
) Deterioration of the electrical characteristics of the MIS field effect semiconductor device, such as voltage shift, occurs.

[0004] In order to solve the above drawbacks, LD
D-structure MIS field effect semiconductor devices have been proposed. In this semiconductor device, impurity regions having a lower concentration than the source and drain regions are provided in portions of the source and drain regions that are in contact with the channel region in order to alleviate electric field concentration near the drain.

However, as miniaturization progresses further, the substantial distance (effective channel length) between the source region and the drain region increases.
As the distance becomes narrower, problems such as short channel effects and punch-through occur.

In order to improve these drawbacks, a buried gate type semiconductor device as shown in FIG. 8 has been proposed. (For example, “1988 International
onal ElectronDevices Mee
ting [IEMD88]” Proceedings pp. 226
229, etc.) FIG. 8 is a cross-sectional structural diagram of a conventional buried gate type MIS field effect semiconductor device.

In FIG. 8, 800 is a P-type semiconductor substrate, 802 and 804 are N- type semiconductor regions for relaxing the electric field, and 806 is an N+-type semiconductor region constituting a drain region. Reference numeral 808 denotes an N+ type semiconductor region constituting a source region. Further, 810 is a P+ type semiconductor region forming a channel region formed by diffusing P type impurities to control the threshold voltage, 812 is a gate insulating film, and 814 is a gate insulating film.
is the gate electrode.

Next, a general manufacturing method will be explained based on FIGS. 9 to 13. Note that FIGS. 9 to 13 are cross-sectional views of a semiconductor device in each manufacturing process by a conventional semiconductor device manufacturing method.

1-a) As shown in FIG. 9, an N-type semiconductor region 400 is formed by ion-implanting N-type impurities into a P-type semiconductor substrate 800 and further performing thermal diffusion. After that, in order to form a recess, for example, the P-type semiconductor substrate 80 is
A mask 401 is formed by oxidizing the surface of 0.

1-b) As shown in FIG. 10, a recess is formed in the P-type semiconductor substrate 800 using anisotropic etching, and the N-type semiconductor region 400 is divided into N-type semiconductor regions 802, 804 is formed. And mask 40
Remove 1.

1-c) As shown in FIG. 11, the surface of the P-type semiconductor substrate 800 is oxidized to form a gate insulating film 812.
form. Then, P-type impurities are ion-implanted into a region where a channel is to be formed in the P-type semiconductor substrate 800 and thermally diffused to form a P+
A shaped semiconductor region 810 is formed.

1-d) As shown in FIG. 12, a gate electrode 814 made of polycrystalline silicon is formed on the gate insulating film 812 using, for example, the CVD method.

1-e) As shown in FIG. 13, using the gate electrode 814 as a mask, the N-type semiconductor region 802,
N+ type semiconductor regions 806 and 808 are formed by ion-implanting N type impurities into 804 and further performing thermal diffusion.

[0014]

However, in the conventional manufacturing method as described above, since the N+ type semiconductor region is formed using the gate electrode 814 as a mask,
There is a problem in that if the position of the gate electrode 814 shifts, the electrical characteristics of the semiconductor device will deteriorate.

In other words, if the gate electrode 814 is shifted to the left (source side) from its normal position, the length of the N-type semiconductor region 804 on the source side becomes longer, and the length of the N-type semiconductor region 802 on the drain side increases. The length of will become shorter. Then, on the source side, the resistance component of the N-type semiconductor region 804 increases and the mutual conductance decreases.

Furthermore, on the drain side, the electric field applied to the P+ type semiconductor region 810 and the N− type semiconductor region 802 increases, resulting in the formation of a large number of hot carriers, which causes problems such as a decrease in the drain current. Occur.

The present invention has been made in view of the above-mentioned problems, and involves forming in a self-aligned manner a low concentration impurity region and a channel region for relaxing an electric field at the bottom of a recess formed in a semiconductor substrate. Accordingly, it is an object of the present invention to provide a method for manufacturing an MIS field effect semiconductor device in which the electrical characteristics of the MIS field effect semiconductor device can be made independent of manufacturing process precision such as mask alignment errors.

[0018]

[Means for Solving the Problems] The present invention has been made to achieve the above-mentioned objects, and includes doping a first impurity of a second conductivity type into a semiconductor substrate of a first conductivity type to form a low concentration impurity. a step of doping the high concentration impurity region with a first impurity of a second conductivity type to a depth shallower than the low concentration impurity region to form a high concentration impurity region;
forming a recess in the low concentration impurity region that is shallower than the low concentration impurity region and deeper than the high concentration impurity region; forming a mask material on the low concentration impurity region and the high concentration impurity region;
A step of etching the mask material using anisotropic etching to form a sidewall on a part of the bottom and sidewall of the recess, and using the sidewall as a mask, a first conductivity type is etched in the low concentration impurity region at the bottom of the recess. After removing the sidewalls, forming a gate insulating film on the surfaces of the low concentration and high concentration impurity regions on the sidewalls and bottom of the recess, A method of manufacturing an MIS field effect semiconductor device includes a step of forming a gate electrode on a surface of a film.

[0019]

In the present invention, a low concentration impurity region and a channel region are formed in a self-aligned manner on the bottom surface of a recess formed in a semiconductor substrate using a sidewall formed on the side wall surface of the recess as a mask. Therefore, the shortest distance of the low concentration impurity region from the high concentration impurity region to the channel region can be easily controlled by the sidewall thickness, optimizing the electrical characteristics of the manufactured MIS field effect semiconductor device. be able to.

[0020]

EXAMPLES The present invention will be explained below based on examples. FIG. 1 is a diagram showing an embodiment of the present invention, and shows a positional sectional view of a semiconductor device manufactured using a manufacturing method based on the present invention. Moreover, FIGS. 2 to 7 are cross-sectional structural views for explaining the manufacturing process of the present invention.

First, the structure of a semiconductor device manufactured according to the present invention will be explained. In FIG. 1, 100 is a P-type semiconductor substrate, and in this embodiment, the P-type corresponds to the first conductivity type described in claim 1, and the P-type corresponds to the second conductivity type. This is the N type.

Further, 110 is a P+ type semiconductor region corresponding to the channel region described in claim 1, 102,
104 is an N-type semiconductor region corresponding to the low concentration impurity region described in claim 1, and 106 and 108 are
This is an N+ type semiconductor region corresponding to the high concentration impurity region described in .

Note that the N+ type semiconductor region 106 constitutes a drain region, and the N+ type semiconductor region 108 constitutes a source region. Then, the N-type semiconductor region 102
, 104 are N+ type semiconductor regions 106, 108, respectively.
FIG. 1 shows a cross-sectional structure of an MIS field effect semiconductor device having an LDD structure.

Next, the manufacturing method will be explained step by step based on FIGS. 2 to 7. 2-a) As shown in FIG. 2, a P-type semiconductor substrate 100
In order to protect the surface from ion implantation, the surface of the P-type semiconductor substrate 100 is oxidized thinly (about 500 angstroms) to form a protective film 142. This protective film 142
N-type impurity ions, such as phosphorus, which correspond to the first impurity described in claim 1, are implanted into the P-type semiconductor substrate 100 through the semiconductor substrate 100 to form a low concentration N-type impurity region 144.

2-b) As shown in FIG.
N-type impurity ions, such as arsenic, which correspond to the first impurity described in claim 1, are implanted into the low-concentration N-type impurity region 144 through the N-type impurity region 142 at a shallower depth than the low-concentration impurity region 144. A type impurity region 146 is formed and further heat treatment is performed to activate the implanted N type impurity ions.

2-c) As shown in FIG. 4, the surface of the highly concentrated N-type impurity region 146 is oxidized to form a thick oxide film, and the oxide film above the portion where the recess is to be formed is removed by photo-etching. A mask material 150 is formed by removing the N-type impurity region 144 and an N-type impurity region shallower than the N-type impurity region 144 by anisotropic etching.
A recess deeper than the + type semiconductor regions 106 and 108 is formed in the P type semiconductor substrate 100. At this time, the formed concave portion allows the N type impurity region 146 to become the N+ type semiconductor region 106,
It is divided into two parts, 108.

2-d) As shown in FIG. 5, for example, a CVD method is applied on the mask material 150 and the P-type semiconductor substrate 100 (including the N-type impurity region 144 and the N+ type semiconductor regions 106 and 108). A mask material 152 corresponding to the mask material according to claim 1 and having a substantially uniform thickness.
form.

2-e) As shown in FIG.
The sidewall 154 is formed by performing anisotropic etching using a reactive ion etching method or the like to remove the mask material 152 except for a portion of the sidewall and bottom of the recess. Next, using the sidewall 154 as a mask, P-type impurity ions such as boron, which correspond to the second impurity described in claim 1, are implanted into the N-type impurity region 144 at the bottom of the recess and the P-type semiconductor substrate 100. P+ type semiconductor region 1 by thermal diffusion
form 10. At this time, the N type impurity region 144 is P
N is electrically separated into two by the + type semiconductor region 110.
- type semiconductor regions 102 and 104.

2-f) As shown in FIG. 7, after removing the mask material 150 and the sidewalls 154, the P+
type semiconductor region 110, N-type semiconductor region 102, 104
Then, the surfaces of the N+ type semiconductor regions 106 and 108 are oxidized to form a gate insulating film 112. Then, a gate electrode 114 made of polycrystalline silicon is formed on the gate insulating film 112 using, for example, a CVD method.

By manufacturing the MIS field effect semiconductor device using the manufacturing method described above, it becomes possible to form the N-type semiconductor regions 102 and 104 in a self-aligned manner. Therefore, as in the case of manufacturing using the conventional manufacturing method, the N-type semiconductor regions 102, 10
It is possible to prevent deterioration of electrical characteristics and reduction of mutual conductance due to hot carrier effects caused by variations in the lengths of the wires.

Furthermore, N-type semiconductor regions 102 and 104
Since the gate electrode 114 is formed along the carrier path of the gate electrode 11, the carrier density of the carrier path near the surfaces of the N-type semiconductor regions 102 and 104 is
This can be controlled by the voltage applied to 4. Therefore, even when the impurity concentration of the N-type semiconductor regions 102 and 104 is lowered to improve the electric field relaxation effect, the mutual conductance decreases due to the series resistance component of the N-type semiconductor regions 102 and 104, and due to the influence of hot carriers. Deterioration of electrical characteristics, etc. can be prevented.

In the above embodiment, an N-type FET was formed using an N-type impurity in a P-type semiconductor substrate, but the conductivity type of each semiconductor region may be reversed. In other words, for an N-type semiconductor substrate, a P-type F is created using a P-type impurity.
ET may also be formed.

In the above embodiment, arsenic is used as the first impurity for forming the N- type semiconductor regions 102 and 104, and phosphorus is used as the first impurity for forming the N+ type semiconductor regions 106 and 108, respectively. However, the first impurities forming the N- type semiconductor regions 102, 104 and the N+ type semiconductor regions 106, 108 may be the same impurity, or other impurities other than arsenic and phosphorus may be used as the N-type impurities. An impurity other than boron may be used as the P-type impurity.

Further, the P+ type semiconductor region 110 is a region for forming a channel, and the conductivity type is P+ type in the above embodiment, but the N− type semiconductor regions 102 and 10
In order to control the threshold voltage, the amount of implanted P-type impurity ions is reduced and the conductivity type of the channel region is changed to N.
--It may be a shape.

[0035]

As described above, according to the present invention, a sidewall is formed on a part of the sidewall and bottom of the recess forming the gate electrode and the channel region, and the sidewall is used as a mask to form the recess. A low concentration impurity region and a channel region can be formed in a self-aligned manner on the bottom surface of the substrate. Therefore, the length of the low concentration impurity region does not depend on the precision of mask alignment, and there is an effect that variations in the electrical characteristics of the MIS field effect semiconductor device can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing a MIS field effect semiconductor device manufactured according to the present invention.

FIG. 2 is a cross-sectional view for explaining the manufacturing process of an embodiment of the present invention.

FIG. 3 is a sectional view for explaining the manufacturing process of an embodiment of the present invention.

FIG. 4 is a cross-sectional view for explaining the manufacturing process of an embodiment of the present invention.

FIG. 5 is a cross-sectional view for explaining the manufacturing process of an embodiment of the present invention.

FIG. 6 is a cross-sectional view for explaining the manufacturing process of an embodiment of the present invention.

FIG. 7 is a cross-sectional view for explaining the manufacturing process of an embodiment of the present invention.

FIG. 8 is a cross-sectional view showing a conventional semiconductor device.

FIG. 9 is a cross-sectional view for explaining the manufacturing process of a conventional semiconductor device.

FIG. 10 is a cross-sectional view for explaining the manufacturing process of a conventional semiconductor device.

FIG. 11 is a cross-sectional view for explaining the manufacturing process of a conventional semiconductor device.

FIG. 12 is a cross-sectional view for explaining the manufacturing process of a conventional semiconductor device.

FIG. 13 is a cross-sectional view for explaining the manufacturing process of a conventional semiconductor device.

[Explanation of symbols] 100 P-type semiconductor substrate 102, 104, 160, 144 N-type low concentration impurity region 106, 108, 146 N-type high concentration impurity region 110 Channel region 112 Gate insulating film 114 Gate electrode 154 Sidewall

Claims (1)

[Claims] 1. A step of doping a semiconductor substrate of a first conductivity type with a first impurity of a second conductivity type to form a low concentration impurity region; , forming a high concentration impurity region by doping with a first impurity of a second conductivity type, and forming a recess in the high concentration impurity region that is shallower than the low concentration impurity region and deeper than the high concentration impurity region. forming a mask material on the low concentration and high concentration impurity regions,
etching the mask material using anisotropic etching to form sidewalls on a part of the bottom and sidewalls of the recess, and etching the low concentration impurity region at the bottom of the recess using the sidewall as a mask; forming a channel region by doping with a second impurity of a first conductivity type; and after removing the sidewalls, a gate insulating film is formed on the surfaces of the low concentration and high concentration impurity regions on the sidewalls and bottom of the recess. and forming a gate electrode on the surface of the gate insulating film.
A method for manufacturing an S field effect semiconductor device.