JPH04259989A - Power control method - Google Patents

Power control method

Info

Publication number
JPH04259989A
JPH04259989A JP9121309A JP2130991A JPH04259989A JP H04259989 A JPH04259989 A JP H04259989A JP 9121309 A JP9121309 A JP 9121309A JP 2130991 A JP2130991 A JP 2130991A JP H04259989 A JPH04259989 A JP H04259989A
Authority
JP
Japan
Prior art keywords
power supply
section
power
control circuit
transfer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP9121309A
Other languages
Japanese (ja)
Inventor
Shigeyuki Maeda
繁幸 前田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP9121309A priority Critical patent/JPH04259989A/en
Publication of JPH04259989A publication Critical patent/JPH04259989A/en
Withdrawn legal-status Critical Current

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  • Static Random-Access Memory (AREA)
  • Dram (AREA)
  • Power Sources (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は、半導体記憶装置のデー
タバックアップ時における電源制御方式に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply control method during data backup of a semiconductor memory device.

【0002】半導体記憶装置では、動作中に停電もしく
は人為的によって電源の供給が停止すると、半導体メモ
リ内のデータが消失してしまうので、磁気ディスク等の
不揮発性記憶にデータを退避(バックアップ)させる必
要がある。このため半導体記憶装置では、このような不
慮の給電停止時に備えて補助電源(バッテリ)を装備し
ている。
[0002] In a semiconductor memory device, if the power supply is interrupted due to a power outage or an artificial interruption during operation, the data in the semiconductor memory will be lost, so the data is evacuated (backed up) to nonvolatile storage such as a magnetic disk. There is a need. For this reason, semiconductor memory devices are equipped with an auxiliary power source (battery) in case of such an unexpected power supply stoppage.

【0003】0003

【従来の技術】従来の半導体記憶装置においては、停電
などにより主電源からの給電が停止すると、自動的に補
助電源からの給電に切り替わり、データのバックアップ
処理を行うが、この際補助電源は、データのバックアッ
プ処理が全て終了するまで、装置全体に電源を供給して
いた。
2. Description of the Related Art In conventional semiconductor storage devices, when the power supply from the main power supply stops due to a power outage, etc., the power supply is automatically switched to the auxiliary power supply and data backup processing is performed. Power was supplied to the entire device until all data backup processing was completed.

【0004】図4は従来の半導体記憶装置の電源制御方
式の構成を示す。図において、1は上位装置との間のデ
ータ転送を制御する入出力制御部、2は半導体記憶素子
で構成された半導体メモリ部、3は電源が遮断された時
にも蓄積された情報を失わない不揮発性記憶部、4は半
導体メモリ部2 と不揮発性記憶部3 の間のデータ転
送を制御する転送制御回路部、5は半導体記憶装置に電
力を供給する主電源部、7は電源が遮断され主電源部5
 が動作しない時電力を供給する補助電源部、81は主
電源部5 と補助電源部7 を切り換える電源切換回路
である。
FIG. 4 shows the configuration of a conventional power supply control system for a semiconductor memory device. In the figure, 1 is an input/output control unit that controls data transfer with a host device, 2 is a semiconductor memory unit composed of semiconductor memory elements, and 3 is a semiconductor memory unit that does not lose stored information even when the power is cut off. A non-volatile memory section, 4 a transfer control circuit section that controls data transfer between the semiconductor memory section 2 and the non-volatile memory section 3, 5 a main power supply section that supplies power to the semiconductor memory device, and 7 a main power supply section when the power is cut off. Main power supply section 5
An auxiliary power supply section 81 supplies power when the main power supply section 5 is not operating, and a power supply switching circuit 81 switches between the main power supply section 5 and the auxiliary power supply section 7 .

【0005】図に示されたように従来の電源制御方式で
は、電源が遮断され主電源部5 が動作しない時には、
電源切換回路81によって主電源部5と補助電源部7 
とが切り換えられるが、は装置全体が補助電源部7 の
負荷になるため補助電源部7 の電力供給能力は大であ
る必要があった。
As shown in the figure, in the conventional power supply control system, when the power is cut off and the main power supply section 5 does not operate,
The main power supply section 5 and the auxiliary power supply section 7 are connected by the power supply switching circuit 81.
However, since the entire device becomes a load on the auxiliary power supply section 7, the power supply capacity of the auxiliary power supply section 7 had to be large.

【0006】[0006]

【発明が解決しようとする課題】このため、データのバ
ックアップ処理の間、処理に関与しない部分にも電源が
供給されていたので、その分大きな消費電力を要し、大
容量の補助電源が必要となり、また補助電源として使わ
れるバッテリの消耗を早めるという問題があった。本発
明はこのような点にかんがみて、データのバックアップ
処理の間の消費電力を低減する手段を提供することを目
的とする。
[Problem to be solved by the invention] For this reason, during data backup processing, power is supplied to parts that are not involved in the processing, which requires a large amount of power consumption and requires a large-capacity auxiliary power supply. Moreover, there was a problem in that the battery used as an auxiliary power source was depleted more quickly. In view of these points, it is an object of the present invention to provide a means for reducing power consumption during data backup processing.

【0007】[0007]

【課題を解決するための手段】上記の課題は下記の如く
に構成された電源制御方式によって解決される。図1は
、本発明の原理図である。
[Means for Solving the Problems] The above problems are solved by a power supply control system configured as follows. FIG. 1 is a diagram showing the principle of the present invention.

【0008】上位装置との間のデータ転送を制御する入
出力制御部1 と、半導体メモリ部2 と、不揮発性記
憶部3 と、電源遮断時に半導体メモリ部2 と不揮発
性記憶部3 との間のデータ退避を制御する転送制御回
路部4 と、周辺回路部6 と、電源遮断時に電力を供
給する補助電源部7 とを有する半導体記憶装置におい
て、転送制御回路部4 内に転送作業に不必要な回路に
順次電源供給を遮断する指示を出す電源逐次遮断機能9
 と、該電源逐次遮断機能9 の指示により複数のブロ
ックに分割された装置内の回路に供給する電源を制御す
る電源制御回路部8 とを設け、電源遮断時に半導体メ
モリ部2 から不揮発性記憶部3 へデータを転送する
際には、データ保持及びデータ転送に関与するブロック
のみに電源を供給するように制御することにより、補助
電源部7 の消費電力を低減するように構成する。
[0008] An input/output control unit 1 that controls data transfer with a host device, a semiconductor memory unit 2, a non-volatile memory unit 3, and a connection between the semiconductor memory unit 2 and the non-volatile memory unit 3 when power is cut off. In a semiconductor storage device having a transfer control circuit section 4 for controlling data saving, a peripheral circuit section 6, and an auxiliary power supply section 7 for supplying power when the power is cut off, there are no unnecessary parts in the transfer control circuit section 4 for the transfer operation. Sequential power cutoff function 9 that issues instructions to sequentially cut off power supply to different circuits
and a power supply control circuit section 8 which controls the power supply to the circuits in the device divided into a plurality of blocks according to instructions from the power supply sequential cutoff function 9. When data is transferred to the auxiliary power supply section 7, the power consumption of the auxiliary power supply section 7 is reduced by controlling the supply of power only to blocks involved in data retention and data transfer.

【0009】[0009]

【作用】電源逐次遮断機能9 により転送作業に不必要
な回路に順次電源供給を遮断する指示が出され、該指示
により電源制御回路部8 は複数のブロックに分割され
た装置内の回路に供給する電源を逐次遮断する。
[Operation] The power supply sequential cutoff function 9 issues an instruction to sequentially cut off the power supply to circuits unnecessary for the transfer operation, and in response to this instruction, the power supply control circuit section 8 supplies power to the circuits in the device divided into multiple blocks. Turn off the power supply sequentially.

【0010】0010

【実施例】第2図は本発明の実施例の構成図である。図
において、8は複数のブロックに分割された装置内の回
路に供給する電源を制御する電源制御回路、9はデータ
バックアップに必要な回路かどうか判断し、不必要な回
路のブロック番号を電源制御回路に通知する電源逐次遮
断回路である。その他、図4と同一符号の物は同一物で
ある。
Embodiment FIG. 2 is a block diagram of an embodiment of the present invention. In the figure, 8 is a power control circuit that controls the power supplied to circuits in the device that are divided into multiple blocks, and 9 is a power control circuit that determines whether the circuit is necessary for data backup and changes the block number of unnecessary circuits. This is a sequential power cutoff circuit that notifies the circuit. Other components having the same reference numerals as those in FIG. 4 are the same.

【0011】図では、半導体メモリ部を6つのブロック
に分割し,さらに入出力制御部、周辺回路部、転送制御
部、不揮発性記憶部の計10個の回路ブロックに分割し
て制御する。
In the figure, the semiconductor memory section is divided into six blocks and further divided into a total of 10 circuit blocks including an input/output control section, a peripheral circuit section, a transfer control section, and a nonvolatile storage section for control.

【0012】装置が動作中に、停電などにより主電源部
5 からの給電が停止すると、転送制御回路4 内の電
源逐次遮断回路9 の指示により補助電源部7 より電
源が供給され、データのバックアップ処理が開始される
。処理に先立ち、電源逐次遮断回路9 は、データのバ
ックアップ処理に関与しない回路部分のブロック番号1
および2を電源制御回路部8 へ通知する。この信号に
より電源制御回路部8 は、バックアップ処理に関与し
ない、入出力制御部1 および周辺回路部6 への給電
を停止する。次に、転送制御回路部4 によって、半導
体メモリ部2 内のデータが不揮発性記憶部3 へバッ
クアップされる。その際、半導体メモリ部2 のブロッ
ク番号3 の先頭アドレスのデータから順に不揮発性記
憶部3 へ転送する。ブロック番号3の最終アドレスの
データを転送し終わると、電源逐次遮断回路9 は、デ
ータのバックアップが終了したブロックの番号であるブ
ロック番号3を、電源制御回路部8 へ通知する。この
信号を受けた電源制御回路部8 は、当該ブロックの電
源を遮断する。以下ブロック番号4,5・・の順に同様
に処理し、ブロック番号8の電源が遮断されると、電源
逐次遮断回路9 は、ブロック番号9,10を電源制御
回路部8 に通知する。この信号により電源制御回路部
8 は、不揮発性記憶部3(ブロック番号9)、転送制
御回路部4(ブロック番号BLOCK 10)の順に電
源を遮断し、最後に補助電源部7 によって、電源制御
回路部8 の電源を遮断して処理を終了する。
When the power supply from the main power supply section 5 stops due to a power outage or the like while the device is in operation, power is supplied from the auxiliary power supply section 7 according to instructions from the power supply sequential cutoff circuit 9 in the transfer control circuit 4, and the data is backed up. Processing begins. Prior to processing, the sequential power cutoff circuit 9 blocks block number 1 of the circuit portion not involved in data backup processing.
and 2 are notified to the power supply control circuit section 8. In response to this signal, the power supply control circuit section 8 stops power supply to the input/output control section 1 and the peripheral circuit section 6 that are not involved in the backup process. Next, the data in the semiconductor memory section 2 is backed up to the nonvolatile storage section 3 by the transfer control circuit section 4. At this time, the data is sequentially transferred to the nonvolatile storage section 3 starting from the first address of block number 3 in the semiconductor memory section 2 . When the data at the final address of block number 3 has been transferred, the sequential power cutoff circuit 9 notifies the power supply control circuit section 8 of the block number 3, which is the number of the block whose data has been backed up. The power supply control circuit unit 8 that receives this signal cuts off the power to the block. The same process is subsequently performed in the order of block numbers 4, 5, etc., and when the power of block number 8 is cut off, the power supply sequential cutoff circuit 9 notifies the power supply control circuit unit 8 of block numbers 9 and 10. In response to this signal, the power supply control circuit section 8 shuts off the power to the nonvolatile storage section 3 (block number 9), the transfer control circuit section 4 (block number BLOCK 10) in this order, and finally the auxiliary power supply section 7 cuts off the power supply to the power supply control circuit section 3 (block number 9). The process is ended by cutting off the power to section 8.

【0013】第2図の電源制御回路部8 の構成例を第
3図に示す。電源制御回路部8 は主電源部5 と補助
電源部7 とを切り換える電源切換回路81と、電源逐
次遮断回路9 から通知される回路ブロック番号をデコ
ードするデコード部82と、デコード部82のデコード
結果を保持するラッチ部83と該ラッチ部83の情報に
よりON,OFFされ、その出力電力が各回路ブロック
に供給されるスイッチ部84から構成される。図中のデ
コード部82およびラッチ部83は、ハードウェアで直
接構成してもよいが、1チップのマイクロコンピュータ
で代用すると、より安価に構成できる。またスイッチ部
84は、パワートランジスタなどで構成される。
FIG. 3 shows an example of the configuration of the power supply control circuit section 8 shown in FIG. 2. The power supply control circuit section 8 includes a power supply switching circuit 81 that switches between the main power supply section 5 and the auxiliary power supply section 7 , a decoding section 82 that decodes the circuit block number notified from the power supply sequential cutoff circuit 9 , and a decoding result of the decoding section 82 . It consists of a latch section 83 that holds , and a switch section 84 that is turned on and off according to the information of the latch section 83 and whose output power is supplied to each circuit block. The decoding section 82 and latch section 83 in the figure may be constructed directly with hardware, but they can be constructed more inexpensively if they are replaced with a one-chip microcomputer. Further, the switch section 84 is composed of a power transistor or the like.

【0014】[0014]

【発明の効果】以上説明したように本発明は、半導体記
憶装置において、装置内の機構を各機能ブロック毎に分
割して電源を供給し、データのバックアップ処理を行う
際には、処理に関与する部分のみに電源を供給するよう
に制御することにより、バックアップ処理時の消費電力
を必要最低限に抑えることが可能となり、それによって
、装置に必要なバッテリの容量を低減でき、バッテリ容
量の小型化、あるいは,分割されたブロックに見合う容
量の小型バッテリの並設など、バックアップに伴うバッ
テリ構成の小型化を実現できるという効果がある。
Effects of the Invention As explained above, the present invention provides a semiconductor storage device in which power is supplied to the internal mechanism of the device by dividing it into functional blocks, and when backing up data, the device is not involved in the processing. By controlling the power to be supplied only to the parts that need to be used, it is possible to reduce power consumption during backup processing to the minimum necessary, thereby reducing the battery capacity required for the device and reducing the battery capacity. This has the effect of making it possible to downsize the battery configuration associated with backup, such as by reducing the size of the battery, or by installing small batteries with a capacity commensurate with the divided blocks in parallel.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】  本発明の原理図[Figure 1] Principle diagram of the present invention

【図2】  本発明の実施例の構成図[Figure 2] Block diagram of an embodiment of the present invention

【図3】  電源制御回路の構成図[Figure 3] Block diagram of power supply control circuit

【図4】  従来の電源制御方式の構成図[Figure 4] Block diagram of conventional power supply control method

【符号の説明】[Explanation of symbols]

1  入出力制御部                
2    半導体メモリ部 3  不揮発性記憶部              4
    転送制御回路部 5  主電源部                  
  6    周辺回路部7  補助電源部     
             8    電源制御回路部 9  電源逐次遮断機能
1 Input/output control section
2 Semiconductor memory section 3 Nonvolatile storage section 4
Transfer control circuit section 5 Main power supply section
6 Peripheral circuit section 7 Auxiliary power supply section
8 Power supply control circuit section 9 Power supply sequential cutoff function

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】  上位装置との間のデータ転送を制御す
る入出力制御部(1)と、半導体メモリ部(2)と、不
揮発性記憶部(3)と、電源遮断時に半導体メモリ部(
2)から不揮発性記憶部(3)へのデータ退避を制御す
る転送制御回路部(4)と、電源遮断時に電力を供給す
る補助電源部(7)とを有する半導体記憶装置において
、転送制御回路部(4)内に転送作業に不必要な回路に
順次電源供給を遮断する指示を出す電源逐次遮断機能(
9)と、該電源逐次遮断機能(9)の指示により複数の
ブロックに分割された装置内の回路に供給する電源を制
御する電源制御回路部(8)とを設けることにより、電
源遮断時に半導体メモリ部(2)から不揮発性記憶部(
3)へデータを退避する際には,データ保持及びデータ
転送に関与するブロックのみに電源を供給するように制
御することにより、補助電源部(7)の消費電力を低減
することを特徴とする、半導体記憶装置の電源制御方式
1. An input/output control unit (1) that controls data transfer with a host device, a semiconductor memory unit (2), a non-volatile memory unit (3), and a semiconductor memory unit (1) that controls data transfer with a host device.
In a semiconductor storage device having a transfer control circuit section (4) that controls data saving from 2) to a nonvolatile storage section (3), and an auxiliary power supply section (7) that supplies power when the power is cut off, the transfer control circuit In section (4), there is a power supply cutoff function (sequential power cutoff function) that issues instructions to sequentially cut off the power supply to circuits unnecessary for the transfer operation.
9) and a power supply control circuit section (8) that controls the power supply to the circuits in the device divided into multiple blocks according to instructions from the power supply shutdown function (9). From the memory section (2) to the non-volatile storage section (
3) When saving data to the auxiliary power supply section (7), the power consumption of the auxiliary power supply section (7) is reduced by controlling the supply of power only to blocks involved in data retention and data transfer. , a power supply control method for semiconductor storage devices.
JP9121309A 1991-02-15 1991-02-15 Power control method Withdrawn JPH04259989A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9121309A JPH04259989A (en) 1991-02-15 1991-02-15 Power control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9121309A JPH04259989A (en) 1991-02-15 1991-02-15 Power control method

Publications (1)

Publication Number Publication Date
JPH04259989A true JPH04259989A (en) 1992-09-16

Family

ID=12051549

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9121309A Withdrawn JPH04259989A (en) 1991-02-15 1991-02-15 Power control method

Country Status (1)

Country Link
JP (1) JPH04259989A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003195989A (en) * 2001-12-26 2003-07-11 Internatl Business Mach Corp <Ibm> Computer device, power source supply control method and program
US20100257385A1 (en) * 2009-04-01 2010-10-07 International Business Machines Corporation Recycling of cache content
US10747449B2 (en) 2014-07-31 2020-08-18 Toshiba Memory Corporation Reduction of power use during address translation via selective refresh operations

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003195989A (en) * 2001-12-26 2003-07-11 Internatl Business Mach Corp <Ibm> Computer device, power source supply control method and program
US20100257385A1 (en) * 2009-04-01 2010-10-07 International Business Machines Corporation Recycling of cache content
US8352762B2 (en) * 2009-04-01 2013-01-08 International Business Machines Corporation Recycling of cache content
US10747449B2 (en) 2014-07-31 2020-08-18 Toshiba Memory Corporation Reduction of power use during address translation via selective refresh operations

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Effective date: 19980514