JPH0426505B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention provides a plurality of controllers that are arranged in parallel via a transmission bus, and each controller is divided according to the number of controllers and is connected to the controller via a system bus. In addition, there is a dual port memory with a two-bank configuration that can be accessed from other controllers via a transmission bus, a switching circuit that alternately switches banks of the dual port memory, and a switching control circuit that controls this switching circuit. The present invention relates to a data exchange method for performing broadcast data exchange between a plurality of controllers via the dual port memory.

[Conventional technology]

Conventionally, as this type of data exchange system, there is, for example, the following system proposed by the applicant (Japanese Unexamined Patent Publication No.
60-8970). FIG. 4 is a block diagram showing such a system.

This is processor (CPU) 11 ₁ , ROM1
1 ₂ and RAM 11 ₃ , a dual port memory 7 consisting of two ports (banks) 7a and 7b, and its switching circuit 1.
2 ₁ , 12 ₂ , a switching control circuit 13 , and a transmission system 14 including a transmission bus. (also simply referred to as the transmission side or transmission system), thereby configuring a so-called multi-controller system.

Each bank 7a, 7b of dual port memory 7
is divided into a plurality of blocks B ₁₁ to B _1N , B ₂₁ to _{B 2N} corresponding to the number of controllers, B ₁₁ and B ₂₁ for one controller, B ₁₂ and B ₂₂ for another controller, etc. Assigned as follows. This controller 10 and other controllers (transmission system)
Data exchange with this dual port memory 7
It is done through. For example, block B ₁₁ ,
Assuming that block B ₂₁ is assigned for data exchange between the controller 10 and a certain transmission system, when block B ₁₁ is connected to the controller 10 side and receives (reads) data, block B ₂₁
is connected to the transmission system and transmits (writes) data, while when block B ₁₁ is connected to the transmission system and transmits (writes) data, the controller 10
is connected to block B ₂₁ to receive data (read)
Do this. The switching circuits 12 ₁ and 12 ₂ switch each block in these banks, and the switching control circuit 13 controls this.

Although the switching circuits 12 ₁ and 12 ₂ are shown as contacts in FIG. 4, and the switching control circuit 13 is shown as a block, they are specifically constructed as shown in FIG. Here, 1 is a bit memory in which bank selection information is stored. 42 is the gate, 31, 32,
33 is an inverting gate, and different banks are selected depending on whether the access is from the transmission system or the controller. Note that 7 is a dual port memory divided into two banks A and B.

That is, when accessing the dual port memory 7 from the controller 10 or the transmission system,
The block number corresponding to that address is designated. This block number becomes the address of the bank selection information storage bit memory 1, and bank selection information for each block is output from the bank selection information storage bit memory 1. With this information, when accessing from the controller 10 side, for example, the inversion gate 32
In addition, when accessing from the transmission system, bank A or bank B is selected through gates 42, respectively. Bank switching is performed for each block by a switching command that is output when normal data is received or when transmission data writing is completed. That is, the contents of the bank selection information storage bit memory 1 are inverted by the inversion gate 31, but since this only switches the bank from A to B or from B to A, the contents of the memory 1 are inverted for each block. That alone is sufficient.

[Problem that the invention seeks to solve]

In this way, the timing at which the received data blocks are switched for received data and the timing at which data is accessed by the controller are completely asynchronous, so there is a problem that synchronization of the data accessed by the controller is not guaranteed. That is, for example, as shown in FIG. 6, if the bank is switched at the time when the controller has read the data of bank A up to Nm words, the controller will read the data of bank B. Therefore, for data that has meaning in N words, data up to N-m is data in bank A, and subsequent data m is data in bank B, and there is a problem that data identity or synchronization is not guaranteed. .

Therefore, an object of the present invention is to guarantee the identity of data sent from other controllers and data accessed by the own controller.

[Means for solving problems]

There is a first memory that stores selection information for selecting memory banks for each block, a second memory that stores bank switching information, and a first memory that stores selection information for selecting memory banks for each block. The first gate means stores the contents in the second memory, and the second gate means stores the contents in the second memory.
A second gate means is provided for storing the contents of the memory in the first memory, and a third gate means is provided for taking an exclusive OR of the first and second memory outputs.

[Effect]

By providing a bit memory for bank switching as well as a bit memory for bank selection, the normally received data for each block can be registered in this bank switching bit memory, and furthermore, the bank switching bit memory can be stored in response to a switching command from the controller. By inverting the contents and storing them in the bank selection bit memory, synchronization or identity between the transmitted data and the data accessed by the system side is ensured.

〔Example〕

FIG. 1 is a block diagram showing an embodiment of the present invention. As is clear from the figure, this is constructed by adding switching information storage bit memory 2, gate 41, exclusive OR (EOR) gate 5, NAND gates 61, 62, etc. to the one shown in FIG. be done.

The switching information storage bit memory 2 stores switching information for each block. At this time, the output of the bank selection information storage bit memory 1 is applied to the memory 2 via the gate 41, but this gate is opened only when data from the transmission system is normally received. The contents of memory 2 match the contents of memory 1 as long as they are received.
Now, for the sake of simplicity, if we focus only on a certain block in banks A and B, if the selection information for that block is "H", the content of memory 1 is "H",
At this time, the content of the memory 2 is "H" if the data corresponding to the block is received normally, and is "L" if the data is not received normally.

On the other hand, the output of memory 2 is given to memory 1 via an inverting gate 31;
is opened in response to a switching command from the controller, so when a switching command is given, the inverted contents of memory 2 are given to memory 1. That is, if memory 2 is "H", memory 1 is "L". The EOR circuit 5 performs an OR operation on each output of the memory 1 and the memory 2, and outputs "H" when they do not match, and outputs "L" when they match, closing the NAND gates 61 and 62. Prevent banks A and B from switching.

Therefore, when data is normally received and a switching command is given from the controller, the switching information in memory 2 is inverted and given to memory 1, and as a result, the outputs of memory 1 and memory 2 become inconsistent. , NAND gate 6 via EOR gate 5
1 and 62 are opened, bank switching is performed according to the contents of memory 1 in the same manner as in FIG. On the other hand, if data is not received normally, memory 1
Since the contents of the memory 2 match the contents of the memory 2, the output of the EOR gate 5 becomes "L" and the NAND gates 61 and 62 are not opened, so that no bank switching is performed.

FIG. 2 is an explanatory diagram for explaining the operation when reception is abnormal.

This is because data B ₁ was received normally as shown in A of the same figure, but when data B ₂ was received, the reception became abnormal and switching was not performed, and as a result, data B ₁ was transferred to the system side as shown in B. Indicates the case where it is used.

Figure 3 is for explaining the operation during reception. In this case, as shown in A of the figure, data is being received, so switching is not performed, and data B ₁ is used on the system side as shown in B. It shows the case.

As described above, by configuring as shown in Figure 1, switching will not be performed unless a switching command is issued from the system (controller) side, and even if a switching command is issued, if reception is abnormal, switching will not occur. This guarantees the identity of the data.

〔Effect of the invention〕

According to this invention, by configuring the memory for bank control to be divided into memory for storing bank selection information and memory for storing switching information, the bank switching timing can be commanded from the controller, and transmission data (from other controllers) can be commanded. This provides the advantage of being able to guarantee synchronization (identity) between the data sent (data sent) and the data accessed by the system.

[Brief explanation of drawings]

Fig. 1 is a configuration diagram showing an embodiment of this invention;
The figure is an explanatory diagram to explain the operation when reception is abnormal.
Fig. 3 is an explanatory diagram for explaining the operation during reception, Fig. 4 is a block diagram showing a conventional example of the data exchange method, and Fig. 5 is the dual port memory shown in Fig. 4, its switching circuit, and switching control. FIG. 6, a configuration diagram showing a specific example of the circuit, is an explanatory diagram for explaining a case where transmission data and data accessed by the own controller are asynchronous. Description of symbols: 1...Bank selection information storage bit memory, 2...Switching information storage bit memory, 31,
32, 33... Inversion gate, 41, 42... Gate, 5... EOR gate, 61, 62... NAND gate, 7... Dual port memory, 7a, 7
b...Boat (bank), 10...Controller,
11...control circuit, ₁₁₁ ...processor, ₁₁₂ ...ROM, ₁₁₃ ...RAM, ₁₂₁ ,
12 ₂ ...Switching circuit, 13...Switching control circuit, 1
4...Transmission system.

Claims (1)

[Scope of Claims] 1. A plurality of controllers are arranged in parallel via a transmission bus, and each controller is divided into blocks according to the number of controllers. A dual port memory having a two-bank configuration that can be accessed through a dual port memory, a switching circuit for alternately switching the banks of the dual port memory, and a switching control circuit for controlling the switching circuit are provided, respectively. In a data exchange method for transmitting and receiving data between a plurality of controllers via a port memory, each of the switching control circuits includes a first memory that stores selection information for selecting the memory bank for each block. a second memory for storing bank switching information; a first gate means for storing the contents of the first memory in a second memory only when data from another controller is normally received; A second memory for storing the contents of the second memory in the first memory according to a bank switching command.
and a third gate means for enabling or disabling bank switching in response to the first and second memory outputs. A data exchange method characterized in that bank switching is enabled only when a command is issued.