JPH04268288A - Semiconductor memory - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a technology that enables high-speed access thereof, such as dynamic random access memory (DRA).
(abbreviated as M).

0002

[Prior Art] DRAM, which is an example of a semiconductor memory device
Because it uses dynamic memory cells to store information, it requires refresh operations at regular intervals, but it is suitable for high integration because the number of elements per bit is small, and the cost is the same at the same level of integration. This is low compared to other RAMs. Such a DRAM basically has a memory cell array consisting of dynamic memory cells that can store information coupled to word lines and bit lines, as well as a memory cell array that enables word line selection based on row addresses. It includes peripheral circuits such as a word selection system that enables bit line selection based on column addresses, a column selection system that enables bit line selection based on column addresses, and a sense amplifier that amplifies memory cell information. In order to prevent this, the process is controlled by an internal clock and operates in a predetermined order and timing so as to follow the procedures of word selection, memory cell information detection, and column selection. In such a DRAM, there is an address multiplexing method as a method for reducing the number of address external terminals, which increases as the storage capacity increases.

[0003] In the address multiplex method, once a row address is latched into an internal latch circuit, there is no need to input that row address from an external terminal, and a column address is not required at the time the memory operation starts. Focusing on this, the row address and column address are fetched from the same external terminal with different timings, thereby reducing the number of address external terminals to half of what would otherwise be required.

Furthermore, 1 in the memory cell array
When a word line is selected, all memory cells coupled to it are activated and that memory cell's information appears on the respective bit lines. In a normal operation cycle, only one of these bit lines is selected by the column selection system, but information in any memory cell connected to the one word line can be read/read by activating the column selection system. It is writable, and there is a page mode as such an operation mode. In a normal operation cycle, each cycle requires a precharge period in which the row address strobe signal indicating the validity of the row address is negated, but in a page mode cycle, one word line Even if all the memory cells to be connected are read and written, the precharging process only needs to be performed once, and the actual cycle time is fast.

[0005] Examples of documents describing the above-mentioned DRAM and other semiconductor memory devices include
“LSI” published by Ohmsha Co., Ltd. on January 30th
There is a handbook.

[0006]

As described above, when one word line in a memory cell array is selected, all the memory cells connected to it are activated, and the information of that memory cell is transferred to each bit line. Therefore, according to the page mode, information in any memory cell connected to one word line can be read/written by activating the column selection system. However, DRAM
The inventor investigated the address selection time and found that even in the above page mode, there is no difference from the normal operation mode in that only one bit line can be selected in one cycle of the column address strobe signal, and the address selection time is It has been found that it is difficult to shorten this further.

SUMMARY OF THE INVENTION An object of the present invention is to provide a technique that can further shorten the address selection time, and thereby to provide a semiconductor memory device that can operate at high speed.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0009]

[Means for Solving the Problems] A brief overview of typical inventions disclosed in this application is as follows.

That is, a semiconductor memory device is constructed including a plurality of column selection systems that enable different bit line selections for a single word line selection. In order to reduce the number of external terminals at this time, it is preferable to provide data switching means to enable the data external terminals to be shared by the plurality of column selection systems. Further, in order to eliminate the need for forming such a data switching means and to lengthen the external output period of the same data, a corresponding data external terminal can be provided for each column selection system. By employing an address multiplexing method that allows the number of external terminals to be reduced, it is also possible to configure the row address and column address to be fetched over time from the same address external terminal. Further, as a specific aspect, a first column decoder for decoding a first column address, and a predetermined bit line of the memory cell array are selectively coupled to a common bit line based on a decode output of the first column decoder. a first column selection circuit for decoding a second column address taken in following the column address; and a second column decoder for decoding a second column address taken in following the column address; The column selection system may include a second column selection circuit for selectively coupling the bit line to the common bit line, and in this case, a first column selection circuit indicating the validity of the first column address. A controller that controls the capture of the first column address based on a column address strobe signal, and controls the capture of the second column address based on a second column address strobe signal indicating the validity of the second column address. can be provided.

[0011]

[Operation] According to the above-mentioned means, the plurality of column selection systems that enable mutually different bit line selections for a single word line selection can be used in a timing-wise manner as long as different column addresses are given to them. This makes it possible to select individual bit lines in an overlapping state, which makes it possible to shorten the address selection time for the semiconductor memory device as a whole and achieve high-speed operation.

0012

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a DRAM which is an embodiment of the present invention.

The DRAM shown in FIG. 1 is formed on a single semiconductor substrate, such as silicon, by a known semiconductor integrated circuit manufacturing technique, although this is not particularly limited.

In FIG. 1, reference numeral 5 denotes a memory cell array, and this memory cell array 5 includes a plurality of dynamic memory cells MS that can store information depending on the presence or absence of charge stored in a capacitor, a plurality of word lines WL, and a plurality of word lines WL. bit line DL. Word lines and bit lines are arranged in a lattice pattern, to which the dynamic memory cells are coupled. Note that there are types of dynamic memory cells such as 4-transistor cells, 3-transistor cells, 2-transistor cells, and 1-transistor cells, and any of them can be applied as the dynamic memory cell MS of this embodiment.

Reference numeral 6 denotes a sense amplifier, and the sense amplifier 6 has a function of detecting and amplifying the information stored in the dynamic memory cell MS, and includes, but is not particularly limited to, the following:
It includes a flip-flop circuit, etc. This sense amplifier 6 is particularly required when a one-transistor type cell with a small signal amount of several tens to hundreds of millivolts is used as the dynamic type memory cell MS.

TA is an address external terminal, and an address Ai can be taken in via this address external terminal TA. In this embodiment, an address multiplex method is adopted to reduce the number of address external terminals.
Address Ai input to address buffer 1 via address external terminal TA is distributed to word selection system 16 and column selection system 17 by address multiplexer (MPX) 2 at the subsequent stage. That is, in the address multiplex system, row addresses and column addresses are inputted over time, and a row address strobe signal RAS indicating the validity of the row address is input.
When * (* indicates that the signal is low active) is asserted to low level, the row address is transmitted to the word selection system 16 via the address MPX2, and also indicates the validity of the column address. When column address strobe signal CAS1* or CAS2* is asserted to low level, the column address is set to address MP.
The signal is transmitted to the column selection system 17 via X2. Such control is performed by a controller 9, which will be described later.

The word selection system 16 includes, but is not particularly limited to, a row address (X) decoder 3 for holding and decoding the row address input via the address MPX2, and a row address (X) decoder 3 for holding and decoding the row address inputted via the address MPX2, and a row address (X) decoder 3 for holding and decoding the row address inputted through the address MPX2, and a row address (X) decoder 3 for holding and decoding the row address inputted through the address MPX2, and a row address (X) decoder 3 for holding and decoding the row address inputted through the address MPX2, and a row address (X) decoder 3 for holding and decoding the row address inputted through the address MPX2. and a word driver 4 for driving a predetermined word line WL in the memory cell array 5 to a selection level. The X decoder 3 is usually formed by a NOR gate circuit or the like, but as described above, a latch circuit for holding the input row address is also formed.

The column selection system 17 has two selection systems, although not particularly limited, in order to enable mutually different bit line selections for a single word line selection by the word selection system 16. That is, when the first column address strobe signal CAS1* is asserted to a low level, the first column (Y) decoder holds the first column address input via the address MPX2 and decodes it. 8 or at a subsequent stage thereof, for selectively coupling a predetermined bit line DL to a common bit line (also referred to as a common bit line or common data line) (not shown) based on its decoded output. A first column selection system 17A including a first column (Y) selection circuit 7 and a second column address strobe signal CAS2* inputted via the address MPX2 when the second column address strobe signal CAS2* is asserted to a low level.
A second column (Y) decoder 11 for holding and decoding a column address (an address that is input following the first column address), and a second column (Y) decoder 11 disposed at a subsequent stage thereof and predetermined based on the decoded output thereof. A second column (Y) selection circuit 10 for selectively coupling the bit line DL of 1 to a common bit line (not shown).
The column selection system 17 in this embodiment is formed by the column selection system 17B.

Here, the first Y selection circuit 7 and the second Y selection circuit 10, the first Y decoder 8 and the second Y decoder 1
1 have basically the same configuration, but when the first column address strobe signal CAS1* is asserted to a low level, the first Y decoder 8 is activated by the controller 9 (meaning an operable state). On the other hand, the second column address strobe signal CAS2*
The difference is that the second Y decoder 11 is activated by the controller 9 when is asserted to a low level. Further, the first Y decoder 8 and the second Y decoder 11 are formed including a NOR gate circuit and a latch circuit for holding an input address, similarly to the X decoder 3. Furthermore, with such a configuration, as shown in FIG. 1, the first Y decoder 8 and the second Y decoder 11 share a column address transmission path, and their address input terminals are commonly connected to the output terminal of the address MPX2. However, between the first Y decoder 8, the second Y decoder 11, and the address MPX2, a multiplexer configured in the same manner as MPX2 is arranged, and thereby the first column address and the second column address are Sorting with addresses is considered effective in ensuring column address transmission.

Reference numeral 13 denotes a data input/output circuit. This data input/output circuit 13 allows data to be input/output via the data external terminal TD, and includes a data output buffer, a data input buffer, and the like. Between this data input/output circuit 13, the first Y selection circuit 7, and the second Y selection circuit 10, the first column selection system 17A and the second column selection system 17B are connected to the data input/output circuit 13 and the second Y selection circuit 10. In order to make it possible to share the data external terminal TD, a data multiplexer (MPX) 12 is arranged as data switching means that makes it possible to switch data transmission paths. The operations of the data MPX 12 and the data input/output circuit 13 are controlled by the controller 9. Especially the above data M
PX12 is the first column address strobe signal CAS
1* is asserted to a low level, the common bit line connected to the first Y selection circuit 7 and the data input/output circuit 13 are coupled, and the second column address strobe signal CAS2
It is controlled by the controller 9 so that the common bit line connected to the second Y selection circuit 10 and the data input/output circuit 13 are coupled when * is asserted to a low level. With such operation control, when the first column address strobe signal CAS1* is asserted to low level, based on the decoded output of the first Y decoder 8,
Data can be read and written via the first Y selection circuit 7, and the second column address strobe signal CAS2
When * is asserted to low level, the second Y selection circuit 1
It is possible to read and write data via 0.

TC is a plurality of control external terminals, and the row address strobe signal RAS*, the first column address strobe signal CAS1*, the second column address strobe signal CAS2*, and the write enable signal are transmitted through the control external terminal TC. It is possible to import WE*. Each of these control signals is input to the controller 9, and the controller 9 generates timing signals and operation control signals for each part of this embodiment based on the control signals input through the control external terminal. Note that when the write enable signal WE* is at a low level, this embodiment is enabled to write data to the memory cell under the control of the controller 9, and when the write enable signal WE* is at a high level, under the control of the controller 9. In this embodiment, data can be read from the memory cell MS.

FIG. 2 shows the operation timing of the main parts in this embodiment.

As shown in FIG. 2, by asserting the row address strobe signal RAS* to a low level, the row address R input from the address external terminal TA at that time is held in the X decoder 3, and the decode be done. A predetermined word line WL in memory cell array 5 is driven to a selection level based on the decoded output. And the row address strobe signal RA
During the period in which S* is asserted to low level, the first
When the column address strobe signal CAS1* is asserted to a low level, the first column address C1 is held in the first Y decoder 8 and decoded in synchronization with the assertion timing. Based on the decoded output, a predetermined bit line DL in the memory cell array 5 is selected.
is coupled to the common bit line in the first Y selection circuit 7. Further, the first column address strobe signal CAS
1*, the second column address strobe signal CAS2* is asserted to a low level, so that the second column address C2 is held in the second Y decoder 11 and decoded in synchronization with the assertion timing. Based on the decoded output, a predetermined bit line DL (valid except for the column address C1) in the memory cell array 5 is coupled to a common bit line in the second Y selection circuit 10.

Note that this column address strobe signal C
The order in which AS*1 and CAS*2 are asserted to low level is the same regardless of which one comes first.

When the write enable signal WE* is at a low level, input buffers and the like in the data input/output circuit 13 are activated to enable data writing, and the first column address strobe signal CAS1* is activated.
The data Din1 input from the data external terminal TB at the assertion timing of the data MPX12 and the first Y
It is transmitted to the memory cell array 5 via the selection circuit 7 and written into the memory cell MS specified by the row address R and the first column address C1, and at the timing of assertion of the second column address strobe signal CAS2*. The data Din2 input from the data external terminal TB is connected to the data MPX12 and the second Y selection circuit 1.
0 to the memory cell array 5 and written into the memory cell MS specified by the row address R and the second column address C2.

On the other hand, when the write enable signal WE* is at a high level, the output buffer in the data input/output circuit 13 is activated to enable data reading, and the first column address strobe signal C
At the timing when AS1* is asserted to low level,
The common bit line connected to the first Y selection circuit 7 is data MPX.
12 to the data input/output circuit 13, the data held in the memory cell MC specified by the row address R and column address C1 is transmitted to the data input/output circuit via the first Y selection circuit 7 and the data MPX12. 1
3 and is transmitted to Do via the output buffer in the input/output circuit 13 and the data external terminal TD.
It is output externally as ut1. Further, at the timing when the second column address strobe signal CAS2* is asserted to a low level, the common bit line connected to the second Y selection circuit 10 is connected to the data input/output circuit 1 via the data MPX12.
3, the data held in the memory cell MC specified by the row address R and column address C2 is transferred to the second Y selection circuit 10 and the data MPX12.
The data is transmitted to the data input/output circuit 13 via the input/output circuit 13, and is outputted to the outside as Dout2 via the output buffer within the input/output circuit 13 and the data external terminal TD.

Here, in the conventional DRAM, there is only one column selection system, so only one bit line can be selected in one cycle period of the column address strobe signal, whereas in the DRAM of this embodiment, there is only one column selection system. , has two column selection systems, making it possible to select individual bit lines with timing overlap.In other words, the first column address strobe signal C
The second column address strobe signal CAS2* can be asserted during the period when AS1* is asserted at a low level, so that, for example, the bit line selection time required for two column addresses C1 and C2 can be shortened compared to the conventional method. , it is possible to speed up read and write operations.

FIG. 3 shows the operation timing of the DRAM of this embodiment in the page mode.

During the period in which the row address strobe signal RAS* is asserted to a low level, the first column address strobe signal CAS1* and the second column address strobe signal CAS2* are each successively asserted. For example, in a write operation in which the write enable signal WE* is asserted to a low level, if column addresses are input in the order of C21, C12, and C22, the second column address strobe signal C
Input data D in synchronization with the assertion timing of AS2*
In21 can be written, input data Din12 can be written in synchronization with the assertion timing of the first column address strobe signal CAS1*, and input data Din12 can be written in synchronization with the assertion timing of the first column address strobe signal CAS1*. Data Din22 can be written. In this case, input data Din
21 and Din22 are made writable in synchronization with the assertion timing of the second column address strobe signal CAS2*, that is, they are made writable by having two column selection systems. When a conventional DRAM has only one column selection system, writing of the input data Din21 and Din22 at the timing shown in FIG. 3 is completely impossible. That is, the DRAM of this embodiment is capable of high-speed operation even in page mode.

According to the above embodiment, the following effects can be obtained.

(1) Since there are multiple column selection systems 17A and 17B that enable different bit line selections for a single word line selection, as long as different column addresses are given to them, , it is possible to select individual bit lines in a state where the timing overlaps, thereby making it possible to shorten the address selection time for the entire DRAM and speeding up data read/write operations. .

(2) Since the data MPX 12 is provided as a data switching means for enabling data external terminals to be shared by the plurality of column selection systems, an increase in the number of external terminals can be prevented.

(3) The effect of (1) above is also effective in page mode.

Another embodiment is shown in FIG.

The DRAM shown in FIG. 4 is different from that shown in FIG. 1 because each of the first column selection system 17A and the second column selection system 17B has a corresponding data external terminal TD.
1, which is a point with TD2. data input/output circuit 15,
16 includes a data input buffer and a data output buffer, similar to that shown in FIG. The common bit line connected to the first Y selection circuit 7 is connected to the data external terminal TD1 via the data input/output circuit 15, and the common bit line connected to the second Y selection circuit 10 is connected to the data external terminal TD2 via the data input/output circuit 16. is combined with In such a configuration, the data MPX12 as shown in FIG. 1 is unnecessary, and therefore, the controller 9A does not have the function of controlling the operation of the data MPX12, compared to the controller 9 of FIG. 1. Note that the other configurations are the same as those shown in FIG. 1, so detailed explanation thereof will be omitted.

FIG. 5 shows the operation timing of the main parts of the DRAM of the embodiment shown in FIG.

Each of the first column selection system 17A and the second column selection system 17B has a corresponding dedicated data external terminal T.
The embodiment shown in FIG. This method has the advantage that the data output time is not limited.

Regarding the write operation, the respective data can be written by asserting the write enable signal WE* to a low level, so a description thereof will be omitted. In addition, column address strobe signal CAS
If *1 and CAS*2 are operated simultaneously (at the same timing), it can be used as a conventional DRAM. Furthermore, by asserting the column address strobe signal CAS*1 or CAS*2 corresponding to the external input/output terminals that are not required to a high level, a mask operation (disabling data write and read data output operations) is performed. It is possible.

Although the invention made by the present inventor has been specifically explained based on examples, it goes without saying that the present invention is not limited thereto and can be modified in various ways without departing from the gist thereof. stomach.

For example, in the above embodiment, the case having two column selection systems 17A and 17B was explained.
Three or more such column selection systems may be provided.

Further, in the above embodiment, the first column address strobe signal CAS1* and the second column address strobe signal CAS2* are used, but the same applies to the case where one system of column address strobe signals is used. effect can be obtained. For example, as shown in FIG. 6, by using the falling edge and rising edge of the waveform of one column address strobe signal CAS*, the first column address C1 is captured in synchronization with the timing of the falling edge of the waveform. Even if the second column address signal C2 is taken in in synchronization with the timing of the rising edge of the waveform, the same effect as in the above embodiment can be obtained.

Furthermore, not only ×1 bit components but also ×
The same effect as the above embodiment can be obtained even in a memory of 2 bits or more.

[0043] In the above explanation, the invention made by the present inventor will be mainly explained in relation to the field of application, DRA, which is the background of the invention.
Although M has been described, the present invention is not limited thereto, and can be applied to read-only memories, other semiconductor storage devices, and even memories built into data processing devices such as single-chip microcomputers. The present invention can also be applied to.

The present invention can be applied to conditions including a memory cell array in which at least memory cells capable of storing information are coupled to word lines and bit lines.

[0045]

Effects of the Invention The effects obtained by typical inventions disclosed in this application are briefly explained below.

In other words, by using a plurality of column selection systems that enable mutually different bit line selections for a single word line selection, individual bit line selections can be made with timings overlapping. As a result, the address selection time of the semiconductor memory device as a whole can be shortened, so that high-speed operation can be achieved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a DRAM according to an embodiment of the present invention.

FIG. 2 is an operation timing diagram of main parts in the DRAM shown in FIG. 1;

FIG. 3 is an operation timing diagram of the DRAM shown in FIG. 1 in page mode.

FIG. 4 is a configuration block diagram of a DRAM according to another embodiment of the present invention.

FIG. 5 is an operation timing chart of main parts in the DRAM shown in FIG. 4;

FIG. 6 is an operation timing chart of main parts in a DRAM according to another embodiment of the present invention.

[Explanation of symbols]

1 Address buffer 2 Address MPX 3.X decoder 4 Word driver 5 Memory cell array 6 Sense amplifier 7 First Y selection circuit 8 First Y decoder 9 Controller 10 Second Y selection circuit 11 Second Y decoder 12 Data MPX 13 Data input/output circuit 16 Word selection system 17 Column selection system 17A 1st column selection system 17B 2nd column selection system TA address external terminal TC control external terminal TD data external terminal MS memory cell DL bit line WL word line

Claims (6)

[Claims] 1. A memory cell array comprising memory cells capable of storing information coupled to word lines and bit lines, wherein the memory cell array is configured by word line selection based on a row address and bit line selection based on a column address. In a semiconductor memory device that allows information to be written to or read from a cell, a plurality of operations that enable operations to select mutually different bit lines for a single word line selection at overlapping timings in whole or in part A semiconductor memory device characterized by comprising a systematic column selection system. 2. The semiconductor memory device according to claim 1, further comprising data switching means for enabling data external terminals to be shared by the plurality of column selection systems. 3. The semiconductor memory device according to claim 1, wherein a corresponding data external terminal is provided for each column selection system. 4. The semiconductor memory device according to claim 1, wherein the row address and the column address are taken in from the same address external terminal over time. 5. The column selection system includes a first column decoder for decoding a first column address, and a predetermined bit line of the memory cell array as a common bit line based on the decode output of the first column decoder. a first column selection circuit for selectively coupling; a second column decoder for decoding a second column address taken in following the first column address;
5. The semiconductor according to claim 1, further comprising a second column selection circuit for selectively coupling a predetermined bit line of said memory cell array to a common bit line based on a decoded output of a column decoder. Storage device. 6. Controlling the capture of the first column address based on a first column address strobe signal indicating the validity of the first column address, and a second column address indicating the validity of the second column address. 6. The semiconductor memory device according to claim 5, further comprising a controller that controls the acquisition of the second column address based on the strobe signal.