JPH04268737A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH04268737A
JPH04268737A JP3029738A JP2973891A JPH04268737A JP H04268737 A JPH04268737 A JP H04268737A JP 3029738 A JP3029738 A JP 3029738A JP 2973891 A JP2973891 A JP 2973891A JP H04268737 A JPH04268737 A JP H04268737A
Authority
JP
Japan
Prior art keywords
emitter
base
region
electrode
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3029738A
Other languages
Japanese (ja)
Inventor
Yoshizo Hagimoto
萩本　佳三
Masanori Yamamoto
山本　正徳
Toshiyuki Watanabe
敏幸 渡辺
Taku Inoue
卓 井上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP3029738A priority Critical patent/JPH04268737A/en
Publication of JPH04268737A publication Critical patent/JPH04268737A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • H10W72/07553—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting changes in shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/922—Bond pads being integral with underlying chip-level interconnections
    • H10W72/9226—Bond pads being integral with underlying chip-level interconnections with via interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/934—Cross-sectional shape, i.e. in side view

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To increase emitter regions without enlarging a chip size and to realize easily the improvement of the characteristics of an active element by a method wherein a fine metal wire is bonded on an emitter electrode pad on emitter electrodes and a base electrode. CONSTITUTION:An interlayer insulating film 7 is provide on the surface, which includes a base electrode (a base region) 5 and emitter electrodes 6, of an n-type silicon substrate 1, contact holes are respectively provided on the electrodes 6, a thick emitter electrode pad 8 of a less of 1.5 to 2.5mum is provided on the surface including the holes in connection with the electrodes 6 and a fine metal wire 9 is bonded on the pad 8.

Description

【発明の詳細な説明】[Detailed description of the invention]

【０００１】0001

【産業上の利用分野】本発明は半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device.

【０００２】0002

【従来の技術】最近のセットの小型・軽量化の動向に伴
い小さいパッケージで低いコレクタ・エミッタ間飽和電
圧ＶＣＥ（ＳＡＴ）　あるいは高い電流定格の製品の要
求がある。2. Description of the Related Art With the recent trend toward smaller and lighter sets, there is a demand for products with smaller packages and lower collector-emitter saturation voltage VCE (SAT) or higher current ratings.

【０００３】従来の半導体装置は、図３に示すように、
Ｎ型シリコン基板１の一主面にＰ型のベース領域２を設
け、Ｐ型ベース領域２内にＮ＋　型のエミッタ領域３を
設けてベース領域２及びエミッタ領域３を含む表面に酸
化シリコン膜４を設ける。次に、酸化シリコン膜４にコ
ンタクト孔を設け、コンタクト孔を含む表面にアルミニ
ウム層を選択的に形成してコンタクト孔のエミッタ領域
３と接続するエミッタ電極パッド１１を形成する。ここ
でエミッタ電極パッド１１は通常、エミッタ領域３及び
エミッタコンタクト孔以外の領域上に形成している。次
に、エミッタ電極パッド１１上に金属細線９をワイヤー
ボンディングして外部回路と接続する。A conventional semiconductor device, as shown in FIG.
A P type base region 2 is provided on one main surface of an N type silicon substrate 1, an N+ type emitter region 3 is provided within the P type base region 2, and a silicon oxide film 4 is formed on the surface including the base region 2 and emitter region 3. will be established. Next, a contact hole is provided in the silicon oxide film 4, and an aluminum layer is selectively formed on the surface including the contact hole to form an emitter electrode pad 11 connected to the emitter region 3 of the contact hole. Here, the emitter electrode pad 11 is usually formed on a region other than the emitter region 3 and the emitter contact hole. Next, a thin metal wire 9 is wire-bonded onto the emitter electrode pad 11 to connect it to an external circuit.

【０００４】0004

【発明が解決しようとする課題】この従来の半導体装置
は、エミッタ電極パッド上に金属細線をボンディングす
る際の衝撃でボンディングパッド下の絶縁膜やベース領
域にクラックを生じたり、ストレスによる特性劣化を生
ずる等の問題点があり、特にエミッタ領域上にパッドを
形成することは避けねばならなかった。[Problems to be Solved by the Invention] This conventional semiconductor device suffers from cracks in the insulating film and base region under the bonding pad due to impact when bonding a thin metal wire onto the emitter electrode pad, and characteristic deterioration due to stress. In particular, formation of pads on the emitter region had to be avoided.

【０００５】従って、コレクタ・エミッタ間飽和電圧Ｖ
ＣＥ（ＳＡＴ）　特性の低減や電流定格を向上させるた
めにエミッタ領域を拡大させようとすると、チップサイ
ズを拡大させなければならないという問題点があった。Therefore, the collector-emitter saturation voltage V
If an attempt is made to enlarge the emitter region in order to reduce the CE (SAT) characteristics or improve the current rating, there is a problem in that the chip size must be enlarged.

【０００６】[0006]

【課題を解決するための手段】本発明の半導体装置は、
一導電型半導体基板の一主面に設けた逆導電型のベース
領域と、前記ベース領域に設けた一導電型のエミッタ領
域と、前記ベース領域及びエミッタ領域を含む表面に設
けた絶縁膜と、前記絶縁膜に設けた第１のコンタクト孔
を介して前記ベース領域に接続したベース電極及び前記
エミッタ領域に接続したエミッタ電極と、前記ベース電
極及びエミッタ電極を含む表面に設けた層間絶縁膜と、
前記層間絶縁膜に設けた第２のコンタクト孔を介して前
記ベース電極又はエミッタ電極に接続し且つ前記ベース
電極及びエミッタ電極上に設けた厚い金属層の電極パッ
ドとを有する。[Means for Solving the Problems] A semiconductor device of the present invention includes:
a base region of an opposite conductivity type provided on one principal surface of a semiconductor substrate of one conductivity type; an emitter region of one conductivity type provided in the base region; an insulating film provided on a surface including the base region and the emitter region; a base electrode connected to the base region through a first contact hole provided in the insulating film, an emitter electrode connected to the emitter region, and an interlayer insulating film provided on a surface including the base electrode and emitter electrode;
and an electrode pad of a thick metal layer connected to the base electrode or emitter electrode through a second contact hole provided in the interlayer insulating film and provided on the base electrode and emitter electrode.

【０００７】[0007]

【実施例】次に、本発明について図面を参照して説明す
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

【０００８】図１は本発明の第１の実施例を示す半導体
チップの断面図である。FIG. 1 is a sectional view of a semiconductor chip showing a first embodiment of the present invention.

【０００９】図１に示すように、Ｎ型シリコン基板１の
一主面に選択的にＰ型のベース領域２を形成し、ベース
領域２の表面に選択的にＮ＋　型のエミッタ領域３を形
成する。次に、ベース領域２及びエミッタ領域３を含む
表面に酸化シリコン膜４を形成してベース領域２及びエ
ミッタ領域３の上の酸化シリコン膜４を選択的に開孔し
て第１のコンタクト孔を設ける。次に、第１のコンタク
ト孔を含む表面にアルミニウム層を０．７〜１．５μｍ
の厚さに堆積してパターニングし、ベース領域２と接続
したベース電極５及びエミッタ領域３と接続するエミッ
タ電極６を夫々形成する。次に、ベース電極５及びエミ
ッタ電極６を含む表面に窒化シリコン膜を１．２〜２．
５μｍの厚さに堆積して層間絶縁膜７を形成し、エミッ
タ電極６上の層間絶縁膜７を選択的に開孔して第２のコ
ンタクト孔を形成する。次に第２のコンタクト孔を含む
表面に選択的にアルミニウム層を１．５〜２．５μｍの
厚さに堆積して第２のコンタクト孔のエミッタ電極６と
接続するエミッタ電極パッド８を形成する。次に、エミ
ッタ電極パッド８の上に金属細線９をボンディングして
外部回路と接続する。As shown in FIG. 1, a P-type base region 2 is selectively formed on one principal surface of an N-type silicon substrate 1, and an N+-type emitter region 3 is selectively formed on the surface of the base region 2. do. Next, a silicon oxide film 4 is formed on the surface including the base region 2 and emitter region 3, and a first contact hole is formed by selectively opening the silicon oxide film 4 on the base region 2 and emitter region 3. establish. Next, a 0.7 to 1.5 μm thick aluminum layer is applied to the surface including the first contact hole.
The base electrode 5 is connected to the base region 2, and the emitter electrode 6 is connected to the emitter region 3. Next, a silicon nitride film is deposited on the surface including the base electrode 5 and emitter electrode 6 for 1.2 to 2 minutes.
The interlayer insulating film 7 is deposited to a thickness of 5 μm, and the interlayer insulating film 7 on the emitter electrode 6 is selectively opened to form a second contact hole. Next, an aluminum layer is selectively deposited on the surface including the second contact hole to a thickness of 1.5 to 2.5 μm to form an emitter electrode pad 8 connected to the emitter electrode 6 of the second contact hole. . Next, a thin metal wire 9 is bonded onto the emitter electrode pad 8 to connect it to an external circuit.

【００１０】図２は本発明の第２の実施例を示す半導体
チップの断面図である。FIG. 2 is a sectional view of a semiconductor chip showing a second embodiment of the present invention.

【００１１】図２に示すように、ベース電極５の上の層
間絶縁膜７を選択的に開孔して第２のコンタクト孔を設
け、第２のコンタクト孔を含む表面に厚さ１．５〜２．
５μｍのアルミニウム層からなるベース電極パッド１０
を選択的に設けた以外は第１の実施例と同様の構成を有
している。As shown in FIG. 2, a second contact hole is provided by selectively opening the interlayer insulating film 7 on the base electrode 5, and a thickness of 1.5 mm is formed on the surface including the second contact hole. ~2.
Base electrode pad 10 made of a 5 μm aluminum layer
It has the same structure as the first embodiment except that it is selectively provided.

【００１２】0012

【発明の効果】以上説明したように本発明は、能動素子
領域上に設けた層間絶縁膜上に厚い金属層からなるボン
ディングパッドを設けることにより、ワイヤーボンディ
ング時に生ずる絶縁膜のクラックや能動領域のストレス
を低減して信頼性を高め、チップサイズを拡大すること
なく能動素子の特性を向上させることができるという効
果を有する。As explained above, the present invention provides a bonding pad made of a thick metal layer on an interlayer insulating film provided on an active element region, thereby preventing cracks in the insulating film that occur during wire bonding and preventing damage to the active region. This has the effect of reducing stress, increasing reliability, and improving the characteristics of active elements without increasing chip size.

【図面の簡単な説明】[Brief explanation of the drawing]

【図１】本発明の第１の実施例を示す半導体チップの断
面図である。FIG. 1 is a cross-sectional view of a semiconductor chip showing a first embodiment of the present invention.

【図２】本発明の第２の実施例を示す半導体チップの断
面図である。FIG. 2 is a cross-sectional view of a semiconductor chip showing a second embodiment of the present invention.

【図３】従来の半導体装置の一例を示す半導体チップの
断面図である。FIG. 3 is a cross-sectional view of a semiconductor chip showing an example of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

１　　　　Ｎ型シリコン基板 ２　　　　ベース領域 ３　　　　エミッタ領域 ４　　　　酸化シリコン膜 ５　　　　ベース電極 ６　　　　エミッタ電極 ７　　　　層間絶縁膜 ８，１１　　　　エミッタ電極パッド ９　　　　金属細線 １０　　　　ベース電極パッド 1 N-type silicon substrate 2 Base area 3 Emitter area 4 Silicon oxide film 5 Base electrode 6 Emitter electrode 7 Interlayer insulation film 8, 11 Emitter electrode pad 9 Thin metal wire 10 Base electrode pad

Claims (3)

【特許請求の範囲】[Claims] 【請求項１】　　一導電型半導体基板の一主面に設けた
逆導電型のベース領域と、前記ベース領域に設けた一導
電型のエミッタ領域と、前記ベース領域及びエミッタ領
域を含む表面に設けた絶縁膜と、前記絶縁膜に設けた第
１のコンタクト孔を介して前記ベース領域に接続したベ
ース電極及び前記エミッタ領域に接続したエミッタ電極
と、前記ベース電極及びエミッタ電極を含む表面に設け
た層間絶縁膜と、前記層間絶縁膜に設けた第２のコンタ
クト孔を介して前記ベース電極又はエミッタ電極に接続
し且つ前記ベース電極及びエミッタ電極上に設けた厚い
金属層の電極パッドとを有することを特徴とする半導体
装置。1. A base region of an opposite conductivity type provided on one principal surface of a semiconductor substrate of one conductivity type, an emitter region of one conductivity type provided in the base region, and a base region provided on a surface including the base region and the emitter region. a base electrode connected to the base region through a first contact hole provided in the insulating film; an emitter electrode connected to the emitter region; It has an interlayer insulating film, and an electrode pad of a thick metal layer connected to the base electrode or emitter electrode through a second contact hole provided in the interlayer insulating film and provided on the base electrode and emitter electrode. A semiconductor device characterized by: 【請求項２】　　電極パッドがアルミニウム層からなる
請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein the electrode pad is made of an aluminum layer. 【請求項３】　　層間絶縁膜が窒化シリコン膜からなる
請求項１記載の半導体装置。3. The semiconductor device according to claim 1, wherein the interlayer insulating film is made of a silicon nitride film.
JP3029738A 1991-02-25 1991-02-25 Semiconductor device Pending JPH04268737A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3029738A JPH04268737A (en) 1991-02-25 1991-02-25 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3029738A JPH04268737A (en) 1991-02-25 1991-02-25 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH04268737A true JPH04268737A (en) 1992-09-24

Family

ID=12284451

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3029738A Pending JPH04268737A (en) 1991-02-25 1991-02-25 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH04268737A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6242813B1 (en) * 1999-03-05 2001-06-05 Taiwan Semiconductor Manufacturing Company Deep-submicron integrated circuit package for improving bondability

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59177937A (en) * 1983-03-28 1984-10-08 Toko Inc Manufacture of semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59177937A (en) * 1983-03-28 1984-10-08 Toko Inc Manufacture of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6242813B1 (en) * 1999-03-05 2001-06-05 Taiwan Semiconductor Manufacturing Company Deep-submicron integrated circuit package for improving bondability

Similar Documents

Publication Publication Date Title
JPS5921034A (en) Semiconductor device
JP7280261B2 (en) Semiconductor elements and semiconductor devices
JP2006173437A (en) Semiconductor device
US4161740A (en) High frequency power transistor having reduced interconnection inductance and thermal resistance
JP5154000B2 (en) Semiconductor device
JP2021040058A (en) Semiconductor device and semiconductor element
JP2956786B2 (en) Synthetic hybrid semiconductor structure
JP2009164288A (en) Semiconductor element and semiconductor device
JP2001044414A (en) Semiconductor device
JPH06177242A (en) Semiconductor integrated circuit device
JPH04268737A (en) Semiconductor device
JP4837939B2 (en) Semiconductor device and manufacturing method of semiconductor device
JP3226082B2 (en) Semiconductor device
EP0405501B1 (en) Semiconductor device
JPH01262654A (en) Semiconductor device
JP3213507B2 (en) Semiconductor device
JP2664911B2 (en) Semiconductor device
JPH07202202A (en) Power MOS device chip and package assembly
JP2642000B2 (en) MOS integrated circuit device
JP7180842B2 (en) semiconductor equipment
JP2559102B2 (en) Semiconductor device
JP3133425B2 (en) Semiconductor device and manufacturing method thereof
JPH01102969A (en) compound semiconductor device
JP2680869B2 (en) Semiconductor device
KR19990061338A (en) Semiconductor device with bonding pads

Legal Events

Date Code Title Description
A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 19961126