JPH04270445A - Threshold value logic circuit with reverse propagation learning function - Google Patents

Threshold value logic circuit with reverse propagation learning function

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Publication number
JPH04270445A
JPH04270445A JP3031075A JP3107591A JPH04270445A JP H04270445 A JPH04270445 A JP H04270445A JP 3031075 A JP3031075 A JP 3031075A JP 3107591 A JP3107591 A JP 3107591A JP H04270445 A JPH04270445 A JP H04270445A
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JP
Japan
Prior art keywords
threshold
value
function
differential
weight
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3031075A
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Japanese (ja)
Inventor
Yutaka Harada
豊 原田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Japan Science and Technology Agency
Original Assignee
Research Development Corp of Japan
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Filing date
Publication date
Application filed by Research Development Corp of Japan filed Critical Research Development Corp of Japan
Priority to JP3031075A priority Critical patent/JPH04270445A/en
Publication of JPH04270445A publication Critical patent/JPH04270445A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To obtain the threshold value logic circuit with a highspeed learning function by introducing a new method to execute current learning while referring to the learnt result in the past into the learning method. CONSTITUTION:For the calculation of a differential product 9C3AE/9C3AUi, multipliers 50kj and 60kj calculates the product of differential values 9C3AE/9C3 AUk, weight Wkj and threshold value differential coefficient f(Ui) by the weight adding sum of an error function to be reversely propagated, and a holding part 30j of the differential value 9C3AE/9C3AUi cumulatively adds the value. A weight Wji is updated by a weight update part 70ji. The weight update part 70ji is composed of a differential holding part 71ji, change amount holding part 72ji, multiplier 73ji, subtracter 74ji and dividers 75ji and 76ji.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【発明の利用分野】本発明は学習機能付しきい値論理回
路、特にバックプロパゲーション法により学習を行なう
学習機能付しきい値論理回路網に係わる。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a threshold logic circuit with a learning function, and particularly to a threshold logic circuit network with a learning function that performs learning by a backpropagation method.

【0002】0002

【発明の背景】従来の計算機はANDまたはOR回路を
組み合わせた論理回路システムで構築されている。これ
らの計算機は極めて高速に動作し、人間の計算能力を遙
かに上回る性能を発揮し、社会に貢献していることは周
知の事実である。しかし、従来の計算機は、人間が日常
行なっている認識動作、判断動作には不適当であること
も次第に明らかになってきた。このため、認識、判断に
好適な計算機を構築する目的で、人間の脳細胞(ニュー
ロン)を手本にしたしきい値論理回路に学習機能を持た
せたニューロン回路と、それを使った計算機システム技
術が例えば、甘利俊一「神経回路網の数理」産業図書、
昭和53年、L.D.Jacklel, R.E.Ho
ward, H.P.Graf, B.Straugh
n, and J.D.Denker, ”Artif
icial neural networls for
 computing”, Journal of V
acuum Society Technology 
B4(1), Jan/Feb. 1986, pp.
61−63に開示されている。
BACKGROUND OF THE INVENTION Conventional computers are constructed with logic circuit systems combining AND or OR circuits. It is a well-known fact that these computers operate at extremely high speeds, exhibit performance that far exceeds human computing ability, and contribute to society. However, it has become increasingly clear that conventional computers are unsuitable for the recognition and judgment operations that humans perform on a daily basis. For this reason, in order to construct a computer suitable for recognition and judgment, we have created a neuron circuit that has a learning function on a threshold logic circuit modeled after human brain cells (neurons), and a computer system using this circuit. For example, the technology is Shunichi Amari's ``Mathematics of Neural Networks'' industrial book,
In 1978, L. D. Jackel, R. E. Ho
ward, H. P. Graf, B. Straugh
n, and J. D. Denker, “Artif
cial neural networks for
“computing”, Journal of V
acum Society Technology
B4(1), Jan/Feb. 1986, pp.
61-63.

【0003】以下に、しきい値論理回路の動作説明を行
い、本発明の位置付けを明らかにする。図2はしきい値
論理回路の動作を示す図である。しきい値論理回路はし
きい部10、重み部20、複数個の入力端子101、入
力線102と少なくとも1個の出力線103を持つ回路
である。しきい値論理回路では、複数の入力端子に信号
Xiが印加され、その信号Xiの重み加算和ΣWiXi
がしきい値θを超えれば出力は“1”に、それ以外は“
0”になる論理動作を行なう。ここで、Wiは重みを表
わす。しきい値論理回路の特徴は学習機能にある。即ち
、学習により、重みWiを変化させ、最終的に目的に適
応した回路システムを構築する。従って、しきい値論理
回路を構成するには、入力信号の重み加算を行ない素子
をスイッチさせる機能だけでなく、重みWi、しきい値
θを変化させる学習機能を持たなければならない。通常
、この重みを制御端子104から入力する重み制御信号
で制御する。
The operation of the threshold logic circuit will be explained below to clarify the positioning of the present invention. FIG. 2 is a diagram showing the operation of the threshold logic circuit. The threshold logic circuit is a circuit having a threshold section 10, a weight section 20, a plurality of input terminals 101, an input line 102, and at least one output line 103. In the threshold logic circuit, a signal Xi is applied to a plurality of input terminals, and a weighted sum of the signals Xi ΣWiXi
If exceeds the threshold θ, the output becomes “1”, otherwise “
0''.Here, Wi represents the weight.The feature of the threshold logic circuit is its learning function.In other words, by learning, the weight Wi is changed and the circuit finally adapts to the purpose. Build a system. Therefore, in order to configure a threshold logic circuit, it is necessary to have not only a function to perform weighted addition of input signals and switch elements, but also a learning function to change the weight Wi and threshold value θ. Normally, this weight is controlled by a weight control signal input from the control terminal 104.

【0004】通常、複雑な論理関数を実現するには図2
に示すしきい値論理回路を多段に複雑に組み合わせる。 該重みを更新する学習は、論理関数の出力信号とその時
に期待される出力信号(教師信号)を比較して、その誤
差を基に重みを変える学習方法が用いられる。図3は図
2のしきい値論理回路を接続した論理関数の構造例を示
しており、3個のしきい部10と2個の重み部20から
構成されている。ここで、j番目のしきい部の入力重み
加算和ΣWijyi としきい値θj の差をUj と
し、しきい関数をf(Uj ) 、出力信号yj とす
る。本特許での着目点は重みを変更する学習法にある。 いくつかある学習方法の内でバックプロパゲーション法
は最も有効な手段として認められている。このバックプ
ロパゲーション法は例えば、中野  馨「ニューロコン
ピュータの基礎」コロナ社(1990年4月)他に詳し
く記載されている。バックプロパゲーション法では、(
1)式(以下の全ての式が発明の詳細な説明の欄の最終
部にまとめて表示されている)に示される、各種入力パ
ターンにおける論理関数の出力信号と教師信号の誤差の
2乗和(誤差関数)Eを最小にするように重みを変える
[0004] Normally, to realize a complex logical function, the method shown in FIG.
The threshold logic circuits shown in the figure are combined in multiple stages in a complex manner. For learning to update the weights, a learning method is used in which the output signal of the logical function is compared with the output signal (teacher signal) expected at that time, and the weights are changed based on the error. FIG. 3 shows an example of the structure of a logic function in which the threshold logic circuit of FIG. 2 is connected, and is composed of three threshold sections 10 and two weight sections 20. Here, let Uj be the difference between the input weighted sum ΣWijyi of the j-th threshold section and the threshold value θj, let f(Uj) be the threshold function, and let the output signal yj be the difference. The focus of this patent is on a learning method that changes weights. Among several learning methods, backpropagation is recognized as the most effective method. This backpropagation method is described in detail in, for example, Kaoru Nakano, "Basics of Neurocomputer", Corona Publishing (April 1990), and others. In the backpropagation method, (
1) The sum of squares of the error between the output signal of the logic function and the teacher signal for various input patterns, as shown in the formula (all formulas below are displayed together at the end of the Detailed Description of the Invention column) (Error function) Change the weight to minimize E.

【0005】ここで、yz は論理関数の出力信号であ
り、ψz はその時の教師信号である。従来のバックプ
ロパゲーション法では、重みやしきい値の変更は最急降
下法により(2)式で表わされる様に変化させる。ここ
でεは収束の度合を決めるパラメータである。従来の方
法で、複雑に接続されている回路網に関し(2)式の∂
E/∂Wji、∂E/∂θj は、例えば(3)(4)
(5)式に示す方法で求めることができる。
[0005] Here, yz is the output signal of the logic function, and ψz is the teacher signal at that time. In the conventional backpropagation method, weights and threshold values are changed using the steepest descent method as expressed by equation (2). Here, ε is a parameter that determines the degree of convergence. In the conventional method, ∂ in equation (2) for a complexly connected circuit network is
E/∂Wji, ∂E/∂θj are, for example, (3) (4)
It can be determined by the method shown in equation (5).

【0006】特に(5)式から分かるように∂E/∂U
j はニューロン回路システムの出力側から入力側に逆
方向に計算出来ることを示している。このため、(3)
式から(5)式に示される方法で学習する方法をバック
プロパゲーション(逆伝搬法)と呼ぶ。この従来方法に
よる、(2)式による学習方法では最急降下法による収
束を行なうため学習効率が悪く、特に目的とする収束点
に近づくに連れて収束速度が遅くなる欠点があった。ま
た、収束の度合を決めるパラメータεは理論的、解析的
に決められる値でないため、その値を決めるのは極めて
曖昧である。しかもεの値によって収束の度合が決まり
、最悪の場合収束せず発散することも起こりうることか
ら、従来の方法は多くの欠点を持っていた。
In particular, as can be seen from equation (5), ∂E/∂U
j indicates that calculation can be performed in the reverse direction from the output side to the input side of the neuron circuit system. For this reason, (3)
The method of learning using the method shown in equation (5) from equation (5) is called backpropagation. This conventional learning method using equation (2) performs convergence using the steepest descent method, which has poor learning efficiency, and has the disadvantage that the convergence speed becomes slower as the target convergence point is approached. Furthermore, since the parameter ε that determines the degree of convergence is not a value that can be determined theoretically or analytically, it is extremely ambiguous to determine its value. Moreover, the degree of convergence is determined by the value of ε, and in the worst case, it may not converge and diverge, so conventional methods have many drawbacks.

【0007】[0007]

【発明の目的】本発明の目的は、バックプロパゲーショ
ン法による重みの更新方法で、学習の収束性を良くし、
パラメータの曖昧さを無くし、学習効率の高い方法を提
供し、高速に重みを変えられるしきい値論理回路の学習
方法を提供することにより、しきい値論理回路を使った
高速かつ多機能の学習を行なう認識、判断機能に優れた
計算機を実現することにある。
[Object of the invention] The object of the present invention is to improve the convergence of learning by using a weight updating method using the backpropagation method.
By eliminating parameter ambiguity, providing a method with high learning efficiency, and providing a learning method for threshold logic circuits that can quickly change weights, we have achieved high-speed and multifunctional learning using threshold logic circuits. The objective is to realize a computer with excellent recognition and judgment functions.

【0008】[0008]

【発明の概要】この目的の為に、本発明ではバックプロ
パゲーション法による学習機能を有するしきい値論理回
路網で、学習方法に過去の学習結果を参照しながら現在
の学習を実行する方法を新しく導入する。本発明で取り
扱う学習方法は第(1)式に示される誤差関数を最小に
する最適化問題に帰着する。従って従来から使われてい
る最適化手法は基本的にここに上げた問題に適用できる
。本発明では誤差関数の微分値に着目し、該値が高速で
零になるような、具体的にはニュートン・ラプソン法に
よる方程式の解法に類似した方法を学習方法として採用
する。
[Summary of the Invention] For this purpose, the present invention uses a threshold logic circuit network having a learning function using the backpropagation method, and uses a method of executing current learning while referring to past learning results as a learning method. Newly introduced. The learning method handled by the present invention results in an optimization problem that minimizes the error function shown in equation (1). Therefore, conventional optimization methods can basically be applied to the problems raised here. The present invention focuses on the differential value of the error function, and employs as a learning method a method similar to the Newton-Raphson method for solving equations, in which the value quickly becomes zero.

【0009】[0009]

【発明の実施例】以下に実施例を用いて本発明を説明す
る。まず本発明による重みやしきい値の変更方法を以下
に説明する。誤差関数の微分∂E/∂Wji、∂E/∂
θj を入力信号の重み加算和Uj に着目して展開し
、(3)式、(4)式、で表わす。従って、誤差関数の
微分∂E/∂Wji、∂E/∂θj は(5)式に従っ
てバックプロパゲーション法によって誤差が計算される
。一方、重み及びしきい値はイテレーションによって何
回も更新される。ここで、本発明では、各イテレーショ
ンの過程で、前回の計算結果を使って次の回の値を更新
する方法を提案する。学習は∂E/∂Wij、∂E/∂
θj 、を零にするようにWij、θj を更新するこ
とに帰着する。これは方程式の根を求める方法に一致す
る。方程式の根を求める方法には各種方法があるが、例
えばニュートン・ラプソン法が収束度が速く優れた方法
として知られている。この方法は関数f(x)=0の解
を求めるのにxの値を(6)式に従って更新する方法で
ある。ここでf’ (x)は導関数である。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be explained below using examples. First, a method of changing weights and thresholds according to the present invention will be explained below. Differential of error function ∂E/∂Wji, ∂E/∂
θj is developed focusing on the weighted sum Uj of the input signals, and is expressed by equations (3) and (4). Therefore, the error of the differentials ∂E/∂Wji and ∂E/∂θj of the error function is calculated by the backpropagation method according to equation (5). On the other hand, the weights and thresholds are updated many times through iteration. Here, the present invention proposes a method of updating the next value in the process of each iteration using the previous calculation result. Learning is ∂E/∂Wij, ∂E/∂
The result is to update Wij and θj so that θj becomes zero. This corresponds to the method of finding the roots of equations. There are various methods for finding the roots of an equation, but for example, the Newton-Raphson method is known as an excellent method with a fast convergence rate. In this method, the value of x is updated according to equation (6) in order to find a solution to the function f(x)=0. Here f' (x) is a derivative.

【0010】本発明の係わっている学習方法では、一般
に誤差関数の関数形が明らかにされないため(6)式の
分母にある微分関数を決める事ができない。このため、
本発明では該微分関数を近似関数で代用する。近似関数
として1次関数を採用した場合の重みの更新方法は(7
)式、(8)式で表わされる。ここで、∂E− /∂W
ij、ΔWij− 、∂E− /∂θj 、Δθj −
 は前回の計算結果を表わす。これらの値は前回のイテ
レーションの際に記憶素子に蓄積される。(7)式、(
8)式は∂E/∂Wij、∂E/∂θj 、を零にする
ようにWij、θj を更新する式であり、各式の分母
は∂E/∂Wij、、∂E/∂θj 、の微係数の1次
近似式となっている。図1は(7)式、(8)式で示さ
れる学習法を実行するニューロン回路のセル構成図を示
している。図1は2個のニューロンセルj、kをつなげ
た構成である。図1の実施例では、各ニューロン回路は
重み部20ji、しきい値部25j、しきい部10jと
誤差関数の重み加算和による微分値∂E/∂Uj の保
持部30j、しきい値微係数部40j、乗算器50ji
、乗算器60kj、重み更新部70ji、しきい値更新
部80jから構成される。微分値∂E/∂Uj の計算
は、乗算器50kjと乗算器60kjが逆伝搬される誤
差関数の重み加算和による微分値∂E/∂Uk 、重み
Wkj、しきい値微係数f’(Uj ) の積を計算し
、その値を微分値∂E/∂Uj の保持部30jが累積
加算することにより実行される。重みWjiの更新は重
み更新部70jiにおいて行なわれる。重み更新部70
jiは、微分値保持部71ji、変化量保持部72ji
、乗算器73ji、減算器74ji、割り算器75ji
、割り算器76jiから構成される。該微分値保持部7
1ji、変化量保持部72jiは前回のイテレーション
で計算した微分値∂E/∂Wjiおよび重み変化量ΔW
ijを記憶する記憶素子である。この重み更新部70j
iでは、(3)式に従って乗算器73jiで計算された
微分値∂E/∂Wjiと更新値保持部72jiに記憶さ
れていた前回の微分値∂E/∂Wji− の差を減算器
74jiで計算し、その差を変化量保持部72jiの値
で割り算を行なう。この値で該微分値∂E/∂Wjiを
割れば(7)式に従った重み変化量ΔWjiは割り算器
76jiで計算される。この重み変化量ΔWijを使っ
て重みWijを更新する。微分値∂E/∂Wjiと重み
変化量ΔWijは計算終了時に該微分値保持部71ji
、変化量保持部71jiに記憶される。しきい値更新部
80jも重み更新部70jiと同様な構成であり、微分
値保持部81j、変化量保持部82j、減算器84j、
割り算器85j、割り算器86jから構成される。しき
い値更新部82jでは、(4)式に従って計算された微
分値∂E/∂θj と更新値保持部82jに記憶されて
いた前回の微分値∂E/∂θj − の差を減算器84
jで計算し、その差を変化量保持部82jの値で割り算
を行なう。この値で該微分値∂E/∂θj を割れば(
8)式に従ったしきい値変化量Δθj は割り算器86
jで計算される。
In the learning method to which the present invention relates, the functional form of the error function is generally not made clear, and therefore the differential function in the denominator of equation (6) cannot be determined. For this reason,
In the present invention, the differential function is replaced by an approximate function. The weight updating method when a linear function is adopted as the approximation function is (7
) and (8). Here, ∂E− /∂W
ij, ΔWij−, ∂E− /∂θj, Δθj−
represents the previous calculation result. These values are stored in the storage elements during the previous iteration. Equation (7), (
8) Equation is an equation that updates Wij, θj so that ∂E/∂Wij, ∂E/∂θj, becomes zero, and the denominator of each equation is ∂E/∂Wij,, ∂E/∂θj, This is a first-order approximation formula for the differential coefficient of . FIG. 1 shows a cell configuration diagram of a neuron circuit that executes the learning method shown by equations (7) and (8). FIG. 1 shows a configuration in which two neuron cells j and k are connected. In the embodiment of FIG. 1, each neuron circuit includes a weight section 20ji, a threshold section 25j, a threshold section 10j, a holding section 30j for the differential value ∂E/∂Uj based on the weighted sum of the error function, and a threshold differential coefficient unit 40j, multiplier 50ji
, a multiplier 60kj, a weight updating section 70ji, and a threshold updating section 80j. Calculation of the differential value ∂E/∂Uj is performed using the differential value ∂E/∂Uk, the weight Wkj, and the threshold differential coefficient f'(Uj ), and the holding unit 30j of the differential value ∂E/∂Uj cumulatively adds the value to the differential value ∂E/∂Uj. The weight Wji is updated in the weight update section 70ji. Weight update unit 70
ji are the differential value holding unit 71ji and the variation holding unit 72ji.
, multiplier 73ji, subtracter 74ji, divider 75ji
, a divider 76ji. The differential value holding section 7
1ji, and the change amount holding unit 72ji stores the differential value ∂E/∂Wji and the weight change amount ΔW calculated in the previous iteration.
This is a memory element that stores ij. This weight updating unit 70j
At i, the subtracter 74ji calculates the difference between the differential value ∂E/∂Wji calculated by the multiplier 73ji according to equation (3) and the previous differential value ∂E/∂Wji− stored in the updated value holding unit 72ji. The difference is divided by the value of the change amount holding section 72ji. By dividing the differential value ∂E/∂Wji by this value, the weight change amount ΔWji according to equation (7) is calculated by the divider 76ji. The weight Wij is updated using this weight change amount ΔWij. The differential value ∂E/∂Wji and the weight change amount ΔWij are stored in the differential value holding unit 71ji at the end of the calculation.
, are stored in the change amount holding unit 71ji. The threshold value updating section 80j has the same configuration as the weight updating section 70ji, and includes a differential value holding section 81j, a change amount holding section 82j, a subtracter 84j,
It is composed of a divider 85j and a divider 86j. The threshold updating unit 82j uses a subtracter 84 to calculate the difference between the differential value ∂E/∂θj calculated according to equation (4) and the previous differential value ∂E/∂θj − stored in the updated value holding unit 82j.
j, and the difference is divided by the value of the change amount holding unit 82j. If we divide the differential value ∂E/∂θj by this value, we get (
8) The amount of threshold change Δθj according to the formula is calculated by the divider 86.
Calculated by j.

【0011】(7)式、(8)式は近似関数として1次
関数を採用したが、他に高次の多項式関数を利用するこ
とも可能である。この場合、多項式を得るのにラグラン
ジェ補間を利用する事が出来る。例えば、一連のイテレ
ーションで、前回、前々回の微分値を∂E− /∂Wj
i、∂E−−/∂Wjiとし、その時のWjiの値をW
ji−、Wji−−とすれば∂E/∂Wjiの関数式と
して(9)式で近似できる。
Although equations (7) and (8) employ a linear function as an approximation function, it is also possible to use a higher-order polynomial function. In this case, Lagrange interpolation can be used to obtain the polynomial. For example, in a series of iterations, the differential value of the previous time and the time before the previous time is expressed as ∂E− /∂Wj
i, ∂E−−/∂Wji, and the value of Wji at that time is W
ji-, Wji--, it can be approximated by equation (9) as a functional expression of ∂E/∂Wji.

【0012】従って、∂E/∂Wjiの微分係数は(1
0)式で近似される。(10)式を(6)式の分母に採
用する事によって2次の多項式で近似できる。以上説明
したごとく、学習機能を有するしきい値論理回路を1個
の単位として規定する事ができ、該しきい値論理回路を
多数個直列並列に並べて実現した論理関数の高速な学習
法を実現できる。本発明では学習機能を有するしきい値
論理回路をハードウエア実現でき、高速かつ効率の良い
学習が実現できる。
Therefore, the differential coefficient of ∂E/∂Wji is (1
0) is approximated by Eq. By adopting equation (10) as the denominator of equation (6), it can be approximated by a second-order polynomial. As explained above, a threshold logic circuit with a learning function can be defined as one unit, and a high-speed learning method for logic functions is realized by arranging a large number of threshold logic circuits in series and parallel. can. According to the present invention, a threshold logic circuit having a learning function can be realized in hardware, and high-speed and efficient learning can be realized.

【0013】以上の説明では、ハードウエアによるしき
い値論理回路とその学習方法を説明したが、ソフトウエ
アで本方法を実行できることは明らか。
In the above description, the threshold logic circuit and its learning method using hardware have been described, but it is clear that this method can be implemented using software.

【0014】[0014]

【本発明の効果】以上説明したごとく、本発明を用いれ
ば、高速の学習機能を有する、しきい値論理回路を構成
できる。従って、本発明により、しきい値論理回路を使
った、認識判断を実行するのに好適な高速計算機を実現
できる。故に、本発明はこの高度の認識判断を行なう高
速計算機の実現に必要不可欠である。
[Effects of the Invention] As explained above, by using the present invention, a threshold logic circuit having a high-speed learning function can be constructed. Therefore, according to the present invention, it is possible to realize a high-speed computer suitable for executing recognition judgment using a threshold logic circuit. Therefore, the present invention is indispensable for realizing a high-speed computer that performs this sophisticated recognition judgment.

【0015】[0015]

【数1】[Math 1]

【0016】[0016]

【数2】[Math 2]

【0017】[0017]

【数3】[Math 3]

【0018】[0018]

【数4】[Math 4]

【0019】[0019]

【数5】[Math 5]

【0020】[0020]

【数6】[Math 6]

【0021】[0021]

【数7】[Math 7]

【0022】[0022]

【数8】[Math. 8]

【0023】[0023]

【数9】[Math. 9]

【0024】[0024]

【数10】[Math. 10]

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】本発明による学習機能付しきい値論理回路の実
施例。
FIG. 1 shows an embodiment of a threshold logic circuit with a learning function according to the present invention.

【図2】しきい値論理回路の動作説明図。FIG. 2 is an explanatory diagram of the operation of a threshold logic circuit.

【図3】しきい値論理回路の接続例を示す図。FIG. 3 is a diagram showing a connection example of a threshold logic circuit.

【符号の説明】[Explanation of symbols]

10  しきい部 20  重み部 25  しきい値部 30  誤差関数の微分値保持部 40  しきい値関数微係数部 50  乗算器 60  乗算器 70  重み更新部 71  微分値保持部 72  変化量保持部 73  乗算器 74  減算器 75,76  割り算器 80  しきい値更新部 81  微分値保持部 82  変化量保持部 84  減算器 85,86  割り算器 101  入力端子 102  入力線 103  出力線 104  制御端子 10 Threshold part 20 Weight part 25 Threshold section 30 Error function differential value holding unit 40 Threshold function differential coefficient part 50 Multiplier 60 Multiplier 70 Weight update section 71 Differential value holding section 72 Change amount holding section 73 Multiplier 74 Subtractor 75, 76 Divider 80 Threshold update section 81 Differential value holding section 82 Change amount holding section 84 Subtractor 85, 86 Divider 101 Input terminal 102 Input line 103 Output line 104 Control terminal

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】  入力信号の重み加算和と該重み加算和
をしきい値と比較して予め定められたしきい値関数に従
って出力信号を出力するしきい値論理回路であって、該
重み値と該しきい値を更新する手段を有し、該手段が過
去の更新結果を使って最新の更新内容を作製する機能を
有するしきい値論理回路を複数個接続したことを特徴と
する逆伝搬学習機能付しきい値論理回路網。
1. A threshold logic circuit that compares a weighted sum of input signals and the weighted sum with a threshold value and outputs an output signal according to a predetermined threshold function, wherein the weight value and a means for updating the threshold, the means connecting a plurality of threshold logic circuits each having a function of creating the latest update content using past update results. Threshold logic network with learning function.
【請求項2】  特許請求の範囲第1項の逆伝搬学習機
能付しきい値論理回路網であって、該しきい値論理回路
網は誤差信号の該重み加算和による微分値を保持する機
能と該しきい値関数の微分値を出力する機能を有し、後
段の誤差信号の重み加算和による微分値と重み値と自己
の該しきい値関数の微分値の積を自己の該誤差信号の重
み加算和による微分値に累積加算する機能を有するしき
い値論理回路を複数個接続したことを特徴とする逆伝搬
学習機能付しきい値論理回路網。
2. A threshold logic network with a back-propagation learning function according to claim 1, wherein the threshold logic network has a function of holding a differential value of an error signal based on the weighted sum. It has a function of outputting the differential value of the threshold function, and outputs the product of the differential value of the weighted sum of the subsequent error signal, the weight value, and the differential value of the threshold function of the self as the error signal of the self. 1. A threshold logic circuit network with a back propagation learning function, characterized in that a plurality of threshold logic circuits each having a function of cumulatively adding a differential value based on a weighted sum of are connected.
【請求項3】  特許請求の範囲2項の逆伝搬学習機能
付しきい値論理回路網であって、該しきい値論理回路網
は誤差関数の該重み値に関する微分値と誤差関数のしき
い値に関する微分値の過去の計算結果、さらにその時の
重み値、しきい値を記録する機能を有し、該過去の計算
結果を使って該重み値、しきい値の更新値を作製するこ
とを特徴とする逆伝搬学習機能付しきい値論理回路網。
3. A threshold logic network with a backpropagation learning function according to claim 2, wherein the threshold logic network is configured to calculate a differential value of an error function with respect to the weight value and a threshold of the error function. It has a function to record past calculation results of differential values regarding values, as well as weight values and threshold values at that time, and can create updated values of the weight values and threshold values using the past calculation results. Features a threshold logic network with backpropagation learning function.
【請求項4】  特許請求の範囲第3項の逆伝搬学習機
能付しきい値論理回路網であって、該重み値、しきい値
の更新方法が誤差関数の該重み値に関する微分値および
誤差関数のしきい値に関する微分値を零にすることを特
徴とする逆伝搬学習機能付しきい値論理回路網。
4. The threshold logic circuit network with a backpropagation learning function according to claim 3, wherein the method for updating the weight value and the threshold value is based on the differential value and error of an error function with respect to the weight value. A threshold logic circuit network with a backpropagation learning function is characterized in that the differential value of a function with respect to a threshold value is made zero.
【請求項5】  特許請求の範囲第4項の逆伝搬学習機
能付しきい値論理回路網であって、該重み値、しきい値
の更新に、誤差関数の該重み値に関する微分値および誤
差関数のしきい値に関する微分値の微分値を過去の誤差
関数の該重み値に関する微分値および誤差関数のしきい
値に関する微分値を使って近似計算し、該誤差関数の該
重み値に関する微分値および誤差関数のしきい値と該近
似値の商に比例した値で更新することを特徴とする逆伝
搬学習機能付しきい値論理回路網。
5. A threshold logic circuit network with a back-propagation learning function according to claim 4, wherein the weight value and the threshold value are updated by updating a differential value of an error function with respect to the weight value and an error. Approximately calculate the differential value of the differential value with respect to the threshold value of the function using the differential value of the past error function with respect to the weight value and the differential value of the error function with respect to the threshold value, and calculate the differential value of the error function with respect to the weight value. and a threshold logic circuit network with a backpropagation learning function, wherein the threshold logic circuit network is updated with a value proportional to the quotient of the threshold value of the error function and the approximate value.
【請求項6】  特許請求の範囲第5項の逆伝搬学習機
能付しきい値論理回路網であって、該近似計算値に、着
目時と前回の該誤差関数の該重み値に関する微分値およ
び誤差関数のしきい値に関する微分値の差とその時の重
み値、しきい値の差の商を使うことを特徴とする逆伝搬
学習機能付しきい値論理回路網。
6. A threshold logic circuit network with a back-propagation learning function according to claim 5, wherein the approximate calculated value includes a differential value with respect to the weight value of the error function at the time of focus and the previous time; A threshold logic circuit network with a back-propagation learning function, characterized in that it uses a difference between differential values of an error function with respect to a threshold value, a weight value at that time, and a quotient of the difference between the threshold values.
【請求項7】  特許請求の範囲5項の逆伝搬学習機能
付しきい値論理回路網であって、近似計算に、過去の複
数の計算結果を多項式で近似することを特徴とする逆伝
搬学習機能付しきい値論理回路網。
7. The threshold logic circuit network with a back-propagation learning function according to claim 5, wherein the back-propagation learning is characterized in that in the approximate calculation, a plurality of past calculation results are approximated by a polynomial. Functional threshold logic network.
JP3031075A 1991-02-26 1991-02-26 Threshold value logic circuit with reverse propagation learning function Pending JPH04270445A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3031075A JPH04270445A (en) 1991-02-26 1991-02-26 Threshold value logic circuit with reverse propagation learning function

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3031075A JPH04270445A (en) 1991-02-26 1991-02-26 Threshold value logic circuit with reverse propagation learning function

Publications (1)

Publication Number Publication Date
JPH04270445A true JPH04270445A (en) 1992-09-25

Family

ID=12321321

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3031075A Pending JPH04270445A (en) 1991-02-26 1991-02-26 Threshold value logic circuit with reverse propagation learning function

Country Status (1)

Country Link
JP (1) JPH04270445A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06246520A (en) * 1993-02-26 1994-09-06 Japan Steel Works Ltd:The Calibration method of camera type reference hole drilling machine

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06246520A (en) * 1993-02-26 1994-09-06 Japan Steel Works Ltd:The Calibration method of camera type reference hole drilling machine

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