JPH04273155A - Manufacture of hybrid integrated circuit for power service - Google Patents

Manufacture of hybrid integrated circuit for power service

Info

Publication number
JPH04273155A
JPH04273155A JP3053606A JP5360691A JPH04273155A JP H04273155 A JPH04273155 A JP H04273155A JP 3053606 A JP3053606 A JP 3053606A JP 5360691 A JP5360691 A JP 5360691A JP H04273155 A JPH04273155 A JP H04273155A
Authority
JP
Japan
Prior art keywords
wiring board
integrated circuit
hybrid integrated
semiconductor power
solder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3053606A
Other languages
Japanese (ja)
Other versions
JP2674336B2 (en
Inventor
Shizuo Okuda
静男 奥田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP3053606A priority Critical patent/JP2674336B2/en
Publication of JPH04273155A publication Critical patent/JPH04273155A/en
Application granted granted Critical
Publication of JP2674336B2 publication Critical patent/JP2674336B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/30Die-attach connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/30Die-attach connectors
    • H10W72/381Auxiliary members

Landscapes

  • Die Bonding (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE:To obtain a manufacturing method for power hybrid integrated circuit which cuts down heat history for a semiconductor power device and prevents characteristic deterioration. CONSTITUTION:A wiring board 2 is mounted on a heat dissipation board 1 wherein a soldering layer 4 is formed on a metallized layer 3 on both sides of the wiring board 2. A metal disk 5 is further mounted on the soldering layer. A semiconductor power device 7 is further integrated thereon by way of a sheet-shaped solder piece 6. Then, by a single reflow process, the soldering layers 4 and 6 are molten thereon in one lot in a reducing atmosphere so that the heat dissipation board 1, the wiring board 2, and the semiconductor power device 7 may be sealed.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は混成集積回路の製造方法
に関し、特にパワー用混成集積回路の製造方法に関する
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a hybrid integrated circuit, and more particularly to a method for manufacturing a power hybrid integrated circuit.

【0002】0002

【従来の技術】従来のパワー用混成集積回路、特にパワ
ートランジスタを絶縁性基板に搭載した上でこれらを放
熱性基体に搭載した集積回路の製造方法は、先ず、図2
(a)に示すように、銅材表面に金メッキを施した金属
ディスク5の上に、 240℃程度の融点を有するシー
ト状半田片6を用いて 280℃〜 300℃に加熱し
たヒーター上で半田片6を溶融させ、パワートランジス
タ7を固着させる。次に、図2(b)に示すように、ア
ルミナセラミックス等によりなる絶縁性配線基板2の上
部に形成されたメタライズ層3に半田層4を形成してお
き、この絶縁性配線基板2に前工程でパワートランジス
タ7を搭載した金属ディスク5を半田層4により溶融固
着させる。その後、図2(c)に示すように、絶縁性配
線基板2と放熱性基体1を接着層8で接着させている。
[Prior Art] A conventional method for manufacturing a power hybrid integrated circuit, particularly an integrated circuit in which a power transistor is mounted on an insulating substrate and then mounted on a heat dissipating substrate, is first shown in FIG.
As shown in (a), a sheet-shaped solder piece 6 having a melting point of about 240°C is soldered onto a metal disk 5 whose surface is gold-plated on a copper material on a heater heated to 280°C to 300°C. Piece 6 is melted and power transistor 7 is fixed. Next, as shown in FIG. 2(b), a solder layer 4 is formed on the metallized layer 3 formed on the top of the insulating wiring board 2 made of alumina ceramics, etc. In the process, the metal disk 5 on which the power transistor 7 is mounted is melted and fixed by the solder layer 4. Thereafter, as shown in FIG. 2(c), the insulating wiring board 2 and the heat dissipating base 1 are bonded together with an adhesive layer 8.

【0003】0003

【発明が解決しようとする課題】このような従来のパワ
ー用混成集積回路の製造方法は、半導体電力素子を搭載
するために、2回以上の半田溶融工程、即ち高温を加え
る工程を施しているため、半導体電力素子に対する熱履
歴が多くなり、混成集積回路の特性劣化が生じ易いとい
う問題がある。本発明の目的は、熱履歴を削減して特性
劣化を防止したパワー用混成集積回路の製造方法を提供
することにある。
[Problems to be Solved by the Invention] In the conventional manufacturing method of power hybrid integrated circuits, in order to mount a semiconductor power device, two or more solder melting steps, that is, a step of applying high temperature are performed. Therefore, there is a problem in that the thermal history of the semiconductor power element increases, and the characteristics of the hybrid integrated circuit are likely to deteriorate. An object of the present invention is to provide a method for manufacturing a power hybrid integrated circuit that reduces thermal history and prevents characteristic deterioration.

【0004】0004

【課題を解決するための手段】本発明の製造方法は、放
熱性基体上に、予めその両面のメタライズ層に半田層が
形成された配線基板を載せ、その上に金属ディスクを載
せ、更にシート状半田片を介して半導体電力素子を重ね
、その上で還元雰囲気中で一回のリフロー処理により前
記半田を一括して溶融して放熱性基体、配線基板、半導
体電力素子を固着する。
[Means for Solving the Problems] The manufacturing method of the present invention includes placing a wiring board on which a solder layer has been previously formed on the metallized layer on both sides of the heat-dissipating substrate, placing a metal disk on top of the wiring board, and then placing a metal disk on top of the wiring board. Semiconductor power devices are stacked with solder pieces interposed therebetween, and then the solder is melted all at once in a reducing atmosphere to fix the heat dissipating substrate, the wiring board, and the semiconductor power device.

【0005】[0005]

【実施例】次に、本発明について図面を参照して説明す
る。図1は本発明方法で製造したパワー用混成集積回路
の断面図である。以下、製造工程に従って説明する。先
ず、絶縁性配線基板2の表裏に形成されたメタライズ層
3に予め半田層4,4を形成しておく。そして、放熱性
基体1上に前記絶縁性配線基板2を載せ、更にその上に
銅材で作られた金属ディスク5を載せ、この上にシート
状半田片6を介してパワートランジスタ7を載せる。こ
の状態で位置ずれを防止するための図外の治具をセット
して前記各部品の相互位置を固定関係とした上で、全体
を還元性雰囲気リフロー炉に通す。これにより、前記半
田層4,4とシート状半田片6が一括して溶融され、そ
の後固化したときに放熱性基体1、絶縁性配線基板2、
パワートランジスタ7を一体的に固定する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. FIG. 1 is a sectional view of a power hybrid integrated circuit manufactured by the method of the present invention. The manufacturing process will be explained below. First, solder layers 4 are formed in advance on the metallized layer 3 formed on the front and back surfaces of the insulating wiring board 2. Then, the insulating wiring board 2 is placed on the heat-dissipating base 1, and a metal disk 5 made of copper is placed on top of it, and a power transistor 7 is placed on top of this with a sheet-like solder piece 6 interposed therebetween. In this state, a jig (not shown) is set to prevent misalignment so that the mutual positions of the parts are fixed, and the whole is passed through a reflow oven in a reducing atmosphere. As a result, the solder layers 4, 4 and the sheet-like solder piece 6 are melted all at once, and when solidified, the heat dissipating base 1, the insulating wiring board 2,
The power transistor 7 is integrally fixed.

【0006】尚、前記実施例では、パワートランジスタ
の搭載例を示したが、複数の半導体電力素子を同時に搭
載することも可能であり、本方法によれば高機能を有す
る混成集積回路が実現できる。
[0006] In the above embodiment, an example of mounting a power transistor was shown, but it is also possible to mount a plurality of semiconductor power devices at the same time, and according to this method, a hybrid integrated circuit with high functionality can be realized. .

【0007】[0007]

【発明の効果】以上説明したように本発明は、放熱性基
体上に、予めその両面のメタライズ部に半田層が形成さ
れた配線基板と、金属ディスクと、シート状半田片を介
して半導体電力素子を順次重ね、その上で還元雰囲気中
で一回のリフロー処理により半田を一括して溶融してこ
れらを固着するので、半導体電力素子の熱履歴を1回に
抑えることができ、特性劣化を抑制したパワー用混成集
積回路を製造することが可能となる。
As explained above, the present invention provides a wiring board on which a solder layer is previously formed on the metallized portions on both sides of a heat dissipating substrate, a metal disk, and a semiconductor power supply via a sheet-like solder piece. The devices are stacked one on top of the other, and then the solder is melted all at once in a reflow process in a reducing atmosphere to fix them together, making it possible to limit the thermal history of the semiconductor power device to just one cycle and prevent characteristic deterioration. It becomes possible to manufacture hybrid integrated circuits for suppressed power.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】本発明の製造方法により製造された集積回路の
断面図である。
FIG. 1 is a cross-sectional view of an integrated circuit manufactured by the manufacturing method of the present invention.

【図2】(a)乃至(c)は従来の製造方法を工程順に
示す断面図である。
FIGS. 2(a) to 2(c) are cross-sectional views showing a conventional manufacturing method in the order of steps.

【符号の説明】[Explanation of symbols]

1  放熱性基体 2  絶縁性配線基板 3  メタライズ層 4,4  半田層 5  金属ディスク 6  シート状半田 1 Heat dissipating base 2 Insulating wiring board 3 Metallized layer 4,4 Solder layer 5 Metal disc 6 Sheet solder

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】  少なくとも半導体電力素子が金属ディ
スクを介してメタライズ基板に搭載され、これらが放熱
性基体に固着されてなるパワー用混成集積回路の製造方
法において、放熱性基体上に、予めその両面のメタライ
ズ層に半田層が形成された配線基板を載せ、その上に金
属ディスクを載せ、更にシート状半田片を介して半導体
電力素子を重ね、その上で還元雰囲気中で一回のリフロ
ー処理により前記半田を一括して溶融し、前記放熱性基
体、配線基板、半導体電力素子を固着することを特徴と
するパワー用混成集積回路の製造方法。
1. A method for manufacturing a power hybrid integrated circuit in which at least a semiconductor power element is mounted on a metallized substrate via a metal disk, and these are fixed to a heat dissipating base, in which both sides of the heat dissipating base are preliminarily mounted. A wiring board with a solder layer formed on it is placed on the metallized layer, a metal disk is placed on top of it, a semiconductor power device is placed on top of it via a sheet of solder, and then a single reflow process is performed in a reducing atmosphere. A method for manufacturing a power hybrid integrated circuit, characterized in that the solder is melted all at once to fix the heat dissipating base, the wiring board, and the semiconductor power device.
JP3053606A 1991-02-27 1991-02-27 Method for manufacturing hybrid integrated circuit for power Expired - Lifetime JP2674336B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3053606A JP2674336B2 (en) 1991-02-27 1991-02-27 Method for manufacturing hybrid integrated circuit for power

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3053606A JP2674336B2 (en) 1991-02-27 1991-02-27 Method for manufacturing hybrid integrated circuit for power

Publications (2)

Publication Number Publication Date
JPH04273155A true JPH04273155A (en) 1992-09-29
JP2674336B2 JP2674336B2 (en) 1997-11-12

Family

ID=12947551

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3053606A Expired - Lifetime JP2674336B2 (en) 1991-02-27 1991-02-27 Method for manufacturing hybrid integrated circuit for power

Country Status (1)

Country Link
JP (1) JP2674336B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0846080A (en) * 1994-07-28 1996-02-16 Nippondenso Co Ltd Hybrid integrated circuit device and manufacturing method thereof

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60146349U (en) * 1984-03-07 1985-09-28 三菱電機株式会社 Semiconductor device heat sink soldering structure

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60146349U (en) * 1984-03-07 1985-09-28 三菱電機株式会社 Semiconductor device heat sink soldering structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0846080A (en) * 1994-07-28 1996-02-16 Nippondenso Co Ltd Hybrid integrated circuit device and manufacturing method thereof

Also Published As

Publication number Publication date
JP2674336B2 (en) 1997-11-12

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