JPH04274504A - Power supply voltage dropping circuit - Google Patents

Abstract

PURPOSE:To switch the voltage of an internal power source to the voltage of an external power source by providing a control circuit which makes a current mirror amplifier circuit inactive in response to a control signal and another control circuit which suppresses the voltage drop of a voltage dropping transistor to nearly the minimum level. CONSTITUTION:This power supply voltage dropping circuit 102 is provided with a reference voltage generation circuit 71, current mirror amplifier circuit 72, voltage dropping transistor Q707, inverter circuit INV21 which is the 1st control circuit, and n-channel FET Q201 which is the 2nd control circuit. When a control signal TE is at an 'H' level, the output of the inverter INV21 becomes an 'L' level and the circuit 72 is inactivated. Then the FET Q201 is turned on and the voltage drop of the transistor Q707 becomes the minimum. As a result, the voltage of an internal power source Vint becomes almost equal to that of an external power source Vcc. When the control signal TE is at an 'L' level, on the other hand, the voltage of the power source Vint becomes almost equal to that of a reference power source Vref.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply step-down circuit.

0002

2. Description of the Related Art Conventionally, as the channels of FETs have become shorter, it has become difficult to ensure reliability of FETs at a power supply voltage of 5V. For this reason, power supply step-down circuits that step down the power supply voltage have been used in semiconductor integrated circuits.

FIG. 7 shows an example of a conventional power supply step-down circuit. The power supply step-down circuit 602 includes a reference voltage generation circuit 71, a current mirror amplifier circuit 72, and a step-down transistor Q707.
It consists of and.

[0004] The reference voltage generation circuit is a p-channel type FET.
Q701, n diodes D701 to D70n,
including. The external power supply Vcc is connected to the source of Q701, and the gate is grounded to GND. Therefore, n diodes D70 are connected to the drain of the transistor Q701.
A forward current flows through 1 to D70n. The forward voltage of each diode is approximately 0.7V, and if the number of these diodes is 5, a voltage of approximately 0.8 x 5 = 4.0V is applied to the anode of diode D701 as the reference voltage Vref. arise. Therefore, a substantially constant reference voltage is output from the reference voltage generation circuit 71.

This reference voltage Vref is input to the gate of transistor Q703 of the current mirror amplifier circuit. This current mirror amplifier circuit uses a p-channel FET
Q705, Q706 and n-channel FET Q702
, Q703, and Q704. n-type transistor Q
The gate of FETQ702 is connected to external power supply Vcc, and a substantially constant current flows between the source and drain of n-channel FETQ702. The reduced internal power supply Vint is input to the gate of the transistor Q704, and this internal power supply V
When int becomes higher than reference voltage Vref, the current flowing through transistor Q704 increases, and conversely, the current flowing through transistor Q703 decreases. Therefore, the potential of the source of transistor Q703 increases, and the drain voltage of step-down transistor Q707, that is, the voltage of internal power supply Vint, decreases. On the other hand, the internal voltage Vint is the reference voltage V
When it becomes lower than ref, the potential of the source of transistor Q703 drops and the voltage of internal power supply Vint rises. Therefore, the voltage of the internal power supply Vint is the reference voltage Vr
is kept equal to ef.

FIG. 8 shows the voltage characteristics of the external power supply Vcc and the internal power supply Vint in the above power supply step-down circuit. When the voltage of external power supply Vcc exceeds 4.0V, internal power supply Vin
The voltage at t is dropped to 4.0V.

Note that if the reference voltage Vref generated by the reference voltage generation circuit 71 is used as the internal voltage Vint, the circuit configuration will be simpler, but such a configuration is generally not used. The reason for this is that the reference voltage generation circuit 7
The current consumption of the p-channel FET 701 is proportional to the channel width of the p-channel FET 701. If the reference voltage generation circuit 71 is used as a direct step-down power supply, the channel width of the p-channel FET 701 must be increased to cover the current consumed as the internal power supply Vint. It won't happen. However, p-channel FET7
01 will also significantly increase the reactive current passing through the diode arrays D701 to D70n. In order to prevent this increase in reactive current, the step-down transistor Q70
7 is provided separately from the reference voltage generation circuit 71 to separate the reactive current from the current consumption of the internal power supply Vint.

[0008]

[Problems to be Solved by the Invention] However, since the conventional power supply step-down circuit 602 does not have a function of switching the voltage of the internal power supply Vint to the voltage of the external power supply Vcc, the power supply step-down circuit 602 does not have the function of switching the voltage of the internal power supply Vint to the voltage of the external power supply Vcc. From 602, the internal power supply Vint is lower than the external power supply Vcc.
There was a problem in that if an attempt was made to supply the external power supply Vcc to the memory circuit 603, a complicated circuit would have to be added.

That is, after diffusion and assembly of semiconductor integrated circuits, an aging test called a burn-in test is performed before an electrical selection test. This burning test is performed, for example, at a temperature of 125° C. and an external power supply voltage of 7.0V. On the other hand, the voltage of the external power supply Vcc is 4.5V to 5.5V under normal usage conditions. The reason why a voltage higher than this voltage range is applied as the external power supply Vcc is to increase the voltage stress applied to elements such as FETs constituting the semiconductor integrated circuit and enhance the aging effect.

However, in the semiconductor integrated circuit 601 using the conventional power supply voltage step-down circuit 602 shown in FIG.
not exceed. For this reason, it has been difficult to obtain an aging effect by applying voltage stress to the semiconductor integrated circuit.

[0011]

SUMMARY OF THE INVENTION Therefore, the present invention realizes the function of switching the voltage of the internal power supply Vint to the voltage of the external power supply Vcc in a power supply step-down circuit with a simple circuit configuration, and also realizes the above switching operation in a power supply step-down circuit. The purpose of this invention is to provide a power supply step-down circuit that also facilitates a control method for switching operations from the outside.

The present invention also provides a power supply step-down circuit that can apply voltage stress to a semiconductor integrated circuit and obtain an aging effect by increasing the voltage of the internal power supply Vint higher than the reference voltage Vref. Its purpose is to provide.

[0013]

[Means for Solving the Problems] A power supply step-down circuit according to the present invention includes a reference voltage generation circuit that generates a constant voltage signal, a current mirror amplification circuit that supplies the constant voltage signal to a reference input node, and a current mirror amplification circuit that supplies the constant voltage signal to a reference input node. In a power supply step-down circuit having a step-down transistor to which an output of the circuit is supplied and which supplies a variable voltage signal to a variable input node of a current mirror amplifier circuit, the current mirror amplifier circuit is deactivated in response to a control signal. The present invention is characterized in that it includes a first control circuit and a second control circuit that responds to the control signal to substantially minimize the voltage drop generated in the step-down transistor.

[0014]

According to the present invention, the constant voltage generating circuit generates a constant voltage signal, and this constant voltage signal is supplied to the reference input node of the current mirror amplifier circuit. When the current mirror amplifier circuit is in an active state, the output of the current mirror amplifier circuit is supplied to the step-down transistor, the mutual conductance of the step-down transistor changes according to the output, and the output voltage of the step-down transistor also changes. This change in output voltage is supplied as a variable voltage signal to a variable input node of the current mirror amplifier circuit. Therefore, the current mirror amplifier circuit and the step-down transistor control the other through their respective inputs and outputs, and the fluctuating voltage signal generates a preset voltage drop and changes only within a certain fluctuation range.

Next, when the first control circuit responds to the control signal, the current mirror amplifier circuit is deactivated and no longer responds to the varying voltage signal. When the second control circuit responds to the control signal, the step-down transistor substantially minimizes the voltage drop. Therefore, the preset voltage drop does not occur, and the power drop circuit generates an output voltage close to the power supply voltage.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A power supply step-down circuit according to the present invention will be described below with reference to embodiments.

FIGS. 1 to 6 are for explaining one embodiment of the present invention.

FIG. 1 shows a power supply step-down circuit 102 according to a first embodiment of the present invention. This power supply step-down circuit 102 includes a reference voltage generation circuit 71, a current mirror amplifier circuit 72,
The step-down transistor Q707, the first control circuit, and the second
and a control circuit.

The reference voltage generation circuit 71, current mirror amplifier circuit 72, and voltage step-down transistor Q707 are the same as those in the power voltage step-down circuit 502 according to the prior art described above, so a detailed explanation will be omitted. The first control circuit consists of an inverter circuit INV21, to which a control signal TE is input, and an inverted signal ITE of the control signal TE is output from an output node and input to the gate of a transistor Q701. The second control circuit includes an n-channel FETQ201, the drain and source of which are connected to the gate of the p-channel FETQ707 and the ground node GND, respectively.

Next, the operation of this power supply step-down circuit 102 will be explained. First, when the control signal is at the "L" level, the output of the inverter INV21 is at the "H" level, current flows through the n-channel type FETQ702, and the current mirror amplifier circuit 72 is activated. In addition, n-channel type F
ETQ201 is cut off by control signal TE. Therefore, the operation of this power supply step-down circuit 102 is the same as that of the conventional power supply step-down circuit 602, and the internal power supply Vint
is controlled to be a voltage substantially equal to the reference voltage Vref.

On the other hand, when the control signal TE is at the "H" level, the output of the inverter INV21 is at the "L" level, the current flowing through the n-channel FETQ702 is cut off, and the current mirror amplifier circuit 72 is inactivated. . Further, the n-channel type FET Q201 is turned on in response to the control signal TE, and the node 21 becomes "L" level. Therefore, the step-down transistor Q707 operates in the saturation region, and the voltage drop is minimized.
The voltage of internal power supply Vint becomes approximately equal to external power supply Vcc.

FIG. 2 shows the voltage characteristics of the external power supply Vcc and the internal power supply Vint in the above power supply step-down circuit. A graph 301 shows the characteristics when the control signal TE is at the "L" level, and this plot 301 has the same characteristics as the characteristics shown in FIG. Plot 302 shows the characteristics when the control signal is at "H" level, and the voltage of external power supply Vcc is 4.0V.
Even when the voltage exceeds 4, the voltage of the internal power supply Vint is 4
It becomes approximately equal to the voltage of external power supply Vcc.

FIG. 3 shows the power supply step-down circuit 102 in FIG.
1 shows a block of a semiconductor memory integrated circuit 101 using a semiconductor memory integrated circuit 101. When the control signal TE is at “L” level, the internal power supply V
The voltage of int is approximately 4.0V, and this voltage is supplied to the memory circuit 603. During a burn-in test of the semiconductor memory integrated circuit 101, the control signal TE is set to "H" level. The voltage of the internal power supply Vint is the external power supply Vcc
For example, if the voltage of the external power supply Vcc is 7.0V, the voltage of the internal power supply Vint is also approximately 7.0V.
．． It becomes 0V. Therefore, the memory circuit has an internal power supply of 7
．． Since 0V is supplied, an aging effect due to voltage stress can be obtained, and it is possible to inspect whether the memory cell is good or bad before shipping.

FIG. 4 shows a power voltage step-down circuit 402 according to a second embodiment of this embodiment. Control signal NC is diode 50
1, and its cathode side is connected to the anode of diode D502. Diode D5
The cathode of 01 is connected to the source of p-channel FETQ501. This p-channel type FETQ50
The gate of FET 1 is connected to the external power supply Vcc, and the drain of FET Q502 is connected to the drain of n-channel type FETQ502. The gate of the n-channel FETQ502 is grounded to the external power supply Vcc, and the source is grounded to GND. n-channel type F
The drain of ETQ502 is connected to the input terminal of inverter INV51, and the output terminal of inverter INV51 is connected to the input terminal of inverter INV52. The output signal of this inverter INV52 is the same as the control signal TE of the power supply step-down circuit according to the first embodiment.
It is supplied to the input terminal of V21 and the gate of n-channel FETQ201.

In the case of this embodiment, the diodes D501, D
The forward ON voltage of 502 is approximately 0.8V, and p
The threshold voltage of channel FETQ501 is 0.7V. Therefore, if the voltage at node 51 exceeds Vcc+0.7V, that is, the control signal NC becomes Vcc+2.3V.
When the voltage exceeds V, the p-channel FETQ501 becomes O.
It becomes N. When the transistor size of n-channel type FETQ502 is made larger than that of n-channel type FET, when FETQ501 is turned on, the voltage at node 52 increases and FETQ502 is cut off. If the threshold value of n-channel FETQ502 is also 0.7V,
The voltage at node 52 is approximately Vcc + 0.7V, and this voltage is changed to Vc by inverters INV51 and INV52.
It is converted to a voltage equal to c. Therefore, inverter IN
The output of V52 becomes “H” level, and the inverter INV
Since the output of 21 becomes "L" level, the current mirror circuit becomes inactive, and the step-down transistor Q201 makes the voltage of the internal power supply Vint approximately equal to the voltage of the external power supply Vcc, similarly to the operation of the first embodiment. do.

The voltage at node 51 is Vcc+0.7V
In other words, if the control signal exceeds Vcc+2.3V
If lower, p-channel FET Q501 is O
Becomes FF. When FETQ501 turns OFF, node 52
The voltage at falls and FETQ502 turns ON. When the voltage at the node 52 becomes approximately equal to GND, the control signal TE becomes "L" level, and the internal power supply V
The voltage of int becomes approximately equal to the reference voltage Vref.

FIG. 5 shows the power supply step-down circuit 102 in FIG.
4 shows a block of a semiconductor memory integrated circuit 401 using. When the control signal NC is at “L” level, the internal power supply V
The voltage of int is approximately 4.0V, and this voltage is supplied to the memory circuit 603. During a burn-in test of the semiconductor memory integrated circuit 401, the control signal NC is set to Vcc+.
Apply a voltage greater than 2.3V. , internal power supply Vint
The voltage of is approximately equal to the voltage of external power supply Vcc. For example, if the voltage of external power supply Vcc is 7.0V, the voltage of internal power supply V
The voltage of int is also 7.0V. Therefore, the memory circuit is supplied with an internal power supply of 7.0V, and an aging drop in voltage stress is obtained. In the normal use state of this semiconductor memory integrated circuit 401, the control signal N
Since a voltage higher than the external power supply Vcc is not supplied to the external terminal of C, it is possible to prevent the voltage of the internal power supply Vint from becoming the voltage of the external power supply Vcc by mistake.

[0028]

[Effects of the Invention] As described above, according to the present invention, the function of switching the voltage of the internal power supply Vint to the voltage of the external power supply Vcc can be easily achieved in a power supply step-down circuit with a simple circuit configuration and switching operation. You can get the effect of being able to do it.

Furthermore, by forming the power effect circuit according to the present invention in a semiconductor integrated circuit, the voltage of the internal power supply Vint can be made higher than the reference voltage Vref, applying voltage stress to the semiconductor integrated circuit and reducing aging effects. can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a power supply step-down circuit according to a first embodiment of the present invention.

FIG. 2 is a characteristic diagram of the power voltage step-down circuit according to the first embodiment of the present invention.

FIG. 3 is a block diagram of a semiconductor memory integrated circuit using a power voltage step-down circuit according to the first embodiment of the present invention.

FIG. 4 is a circuit diagram of a power supply step-down circuit according to a second embodiment of the present invention.

FIG. 5 is a block diagram of a semiconductor memory integrated circuit using a power voltage step-down circuit according to a second embodiment of the present invention.

FIG. 6 is a semiconductor memory integrated circuit using a power voltage step-down circuit according to the prior art.

FIG. 7 is a circuit diagram of a power supply step-down circuit according to the prior art.

FIG. 8 is a characteristic diagram of a power supply step-down circuit according to the prior art.

[Explanation of symbols]

102 Power supply step-down circuit 402 Power supply step-down circuit 71 Reference voltage generation circuit 72 Current mirror amplifier circuit Q707
Step-down transistor TE Control signal NC Control signal INV21 Inverter (second control circuit) INV51
Inverter (second control circuit) INV52 Inverter (second control circuit) D501 Diode (second control circuit) D502 Diode (second control circuit) Q5
01 p-channel FET (second control circuit) Q50
2 n-channel FET (second control circuit) Q201
n-channel FET (first control circuit) 502
n-channel type FET Q501 p-channel type FET

Claims (3)

[Claims] 1. A reference voltage generation circuit that generates a constant voltage signal, a current mirror amplification circuit that supplies the constant voltage signal to a reference input node, and a current mirror amplification circuit that is supplied with the output of the current mirror amplification circuit and outputs a fluctuating voltage signal. a first control circuit that deactivates the current mirror amplifier circuit in response to a control signal in a power supply step-down circuit having a step-down transistor supplied to a variable input node of the circuit;
A power supply step-down circuit comprising: a second control circuit that substantially minimizes a voltage drop occurring in the step-down transistor in response to the control signal. 2. The power step-down circuit according to claim 1, wherein the power step-down circuit is included in a semiconductor integrated circuit, and the first control signal is supplied from an external terminal during a function test of the semiconductor integrated circuit. 3. The first control circuit includes a diode string connected to the external terminal, a p-channel transistor and an n-channel transistor connected between the anode of the diode string and a ground terminal, and having a gate connected to a power supply. and a first inverter string connected to a common drain of the p-channel transistor and the n-channel transistor, and the second control circuit includes a diode string, an anode of the diode string, and a ground terminal. a series connection body of a p-channel transistor and an n-channel transistor whose gates are connected to a power source; a second inverter array connected to a common drain of the p-channel transistor and the n-channel transistor; 3. A grounding transistor connected between the gate of the step-down transistor and a grounding terminal and controlled by the output of the second inverter column, wherein the control signal is a signal with a voltage exceeding the power supply voltage. Power supply step-down circuit.