JPH0428111B2 - - Google Patents

Info

Publication number
JPH0428111B2
JPH0428111B2 JP58052109A JP5210983A JPH0428111B2 JP H0428111 B2 JPH0428111 B2 JP H0428111B2 JP 58052109 A JP58052109 A JP 58052109A JP 5210983 A JP5210983 A JP 5210983A JP H0428111 B2 JPH0428111 B2 JP H0428111B2
Authority
JP
Japan
Prior art keywords
pixel
level
signal
state
character
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58052109A
Other languages
Japanese (ja)
Other versions
JPS59178091A (en
Inventor
Sukeyuki Yokoyama
Sanemitsu Teraoka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP58052109A priority Critical patent/JPS59178091A/en
Publication of JPS59178091A publication Critical patent/JPS59178091A/en
Publication of JPH0428111B2 publication Critical patent/JPH0428111B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N9/00Details of colour television systems
    • H04N9/64Circuits for processing colour signals
    • H04N9/68Circuits for processing colour signals for controlling the amplitude of colour signals, e.g. automatic chroma control circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Processing Of Color Television Signals (AREA)

Description

【発明の詳細な説明】[Detailed description of the invention]

〔本発明の技術分野〕 本発明は、キヤラクタ信号をNTSC信号に変換
するためのキヤラクタ信号変換回路の改良に関す
る。 〔発明の技術的背景とその問題点〕 近年、パーソナルコンピユータの普及に伴な
い、このコンピユータから出力されるカラーキヤ
ラクタ信号(R,G,Bの3信号)を一般的なテ
レビジヨン受像機に供給して表示させることが多
く行なわれている。ところが、テレビジヨン受像
機はNTSC方式を採用しており、この方式では信
号の帯域を4.5MHz以下に制限しているため、帯
域幅が7MHz以上と高いキヤラクタ信号をそのま
まテレビジヨン受像機に供給して表示させるには
無理がある。 そこで、従来では、例えば第1図に示す如き
NTSC変換回路を設けてキヤラクタ信号の変換を
行なつている。すなわち、パーソナルコンピユー
タ1から出力されたR,G,Bの3信号RS,
GS,BSを、それぞれ先ず遅延回路2a,2b,
2cに導びいてここでその画素幅を水平方向およ
び垂直方向にそれぞれ拡大し、しかるのち信号変
換回路3で信号変換してR−Y,B−Y,Yの各
信号RS′,BY′,YSを作成する。そして、上記各
信号のうちR−Y,B−Y信号RS′,BS′をそれ
ぞれカツトオフ周波数が500kHzの低域通過フイ
ルタ4a,4bを通したのち平衡変調回路5a,
5bに導びき、この回路5a,5bで3.58MHzの
正弦波を振幅変調してその変調出力を合成回路6
で合成し、しかるのち重畳回路7で上記合成出力
を前記信号変換回路3からの輝度信号YS′に重畳
してその出力を図示しないテレビジヨン受像機に
供給するようにしている。 しかしながら、この従来の変換回路は、次のよ
うな欠点があつた。 () キヤラクタ信号RS,GB,BSの画素幅
を遅延回路2a,2b,2cで拡大することに
よりNTSC方式に適合させるようにしているた
め、表示分解能が劣化して細かい文字を明瞭に
表示することができない。 () 一般にキヤラクタ信号は、水平方向の周
波数成分に比べて垂直方向の周波数成分が高い
ため、水平および垂直各方向の画素幅をそれぞ
れ拡大しても、低域通過フイルタ4a,4bを
通過させることにより水平方向に比べて垂直方
向の信号レベルが著しく低レベルとなる。この
結果文字は縦線が薄く横線のみが強調された極
めて不自然なものになる。このことは、特にグ
ラフ等を表示する場合に、縦線がほとんど表示
されないことになり、非常に好ましくない。 一方、縦方向を強調するために、キヤラクタ
信号をIH遅延線を通すものも提唱されている
が、このような回路では例えば点のように縦方
向に連続性のない文字の場合にはその効果が得
られず、依然として明瞭な表示を得ることがで
きなかつた。 〔発明の目的〕 本発明は、縦横各輝線の方向また文字の形態に
よらず明るさが均一で明瞭な表示を行なわせるこ
とができるキヤラクタ信号変換回路を提供するこ
とを目的とする。 〔発明の概要〕 本発明は、上記目的を達成するために、キヤラ
クタ信号の画素幅をNTSC信号に適合するように
拡大し、この画素幅を拡大したキヤラクタ信号の
各画素毎に、当該画素の前および後に各々位置す
る複数の画素を含む画素列を抽出し、この画素列
を構成する各画素のうち特定の信号レベルの画
素、例えば“1”の画素の配列状態が、孤立して
存在している第1の状態か、1画素おきに存在し
ている第2の状態か、あるいは連続して存在して
いる第3の状態かを少なくとも判定し、この判定
結果に従つて上記当該画素の信号レベルを、上記
第2の状態では所定の第2のレベルに、上記第1
の状態では上記第2のレベルよりも高い第1のレ
ベルに、かつ上記第3の状態では上記第2のレベ
ルよりも低い第3のレベルに少なくともそれぞれ
可変設定するようにしたものである。 〔発明の実施例〕 第2図は、本発明の一実施例におけるキヤラク
タ信号変換回路の要部である信号レベル制御回路
の回路構成図で、前記第1図における遅延回路2
a,2b,2cに代わつて設けられるものであ
る。なお、信号レベル制御回路は、R,G,Bの
各信号RS,GS,BS毎に設けられるが、各回路
とも同一構成なので第2図ではそのうちひとつの
みを示す。 この信号レベル制御回路は、キヤラクタ信号
(例えばR信号RS)の画素幅を水平方向に拡大す
る遅延回路11と、この遅延回路11から出力さ
れた遅延キヤラクタ信号RDSを画素毎にクロツ
ク信号CKに同期してシフト入力する5ビツトの
シフトレジスタ12と、このシフトレジスタ12
の並列出力が供給される判定回路13と、この判
定回路13の判定出力をラツチするラツチ回路1
4と、信号レベル可変回路15とから構成されて
いる。 判定回路13は、リード・オンリー・メモリか
らなり、シフトレジスタ12からの並列出力をア
ドレス信号として導びき、このアドレス信号によ
り指定された記憶領域に記憶されている判定値を
それに対応する端子D1,D2,D3,D4から出力す
るものである。ここで、上記ROMの記憶内容は
次表のように設定してある。
[Technical Field of the Invention] The present invention relates to an improvement in a character signal conversion circuit for converting a character signal into an NTSC signal. [Technical background of the invention and its problems] In recent years, with the spread of personal computers, color character signals (three signals of R, G, and B) output from these computers have been transmitted to general television receivers. It is often done to supply and display the data. However, television receivers use the NTSC system, which limits the signal band to 4.5MHz or less, so high character signals with a bandwidth of 7MHz or more cannot be directly supplied to the television receiver. It is impossible to display it. Therefore, in the past, for example, as shown in Figure 1,
An NTSC conversion circuit is provided to convert character signals. That is, the three signals RS of R, G, and B output from the personal computer 1,
GS and BS are first connected to delay circuits 2a, 2b, and
2c, where the pixel width is expanded in the horizontal and vertical directions, and then the signal is converted by the signal conversion circuit 3 to produce the R-Y, BY, Y signals RS', BY', Create YS. Of the above-mentioned signals, the R-Y and B-Y signals RS' and BS' are passed through low-pass filters 4a and 4b with a cutoff frequency of 500 kHz, respectively, and then balanced modulation circuits 5a and 4b.
5b, amplitude modulates the 3.58MHz sine wave in circuits 5a and 5b, and sends the modulated output to synthesis circuit 6.
Thereafter, a superimposing circuit 7 superimposes the synthesized output on the luminance signal YS' from the signal converting circuit 3, and the output is supplied to a television receiver (not shown). However, this conventional conversion circuit has the following drawbacks. () Since the pixel width of the character signals RS, GB, and BS is expanded by delay circuits 2a, 2b, and 2c to make it compatible with the NTSC system, the display resolution deteriorates and fine characters cannot be displayed clearly. I can't. () In general, character signals have higher frequency components in the vertical direction than frequency components in the horizontal direction, so even if the pixel widths in each of the horizontal and vertical directions are expanded, they cannot be passed through the low-pass filters 4a and 4b. As a result, the signal level in the vertical direction becomes significantly lower than that in the horizontal direction. As a result, the characters become extremely unnatural, with thin vertical lines and only emphasized horizontal lines. This is extremely undesirable, especially when displaying a graph or the like, since almost no vertical lines are displayed. On the other hand, in order to emphasize the vertical direction, it has been proposed to pass the character signal through an IH delay line, but in such a circuit, for example, in the case of characters that are not continuous in the vertical direction, such as dots, the effect is was not obtained, and it was still not possible to obtain a clear display. [Object of the Invention] An object of the present invention is to provide a character signal conversion circuit that can display a clear display with uniform brightness regardless of the direction of vertical and horizontal bright lines or the form of characters. [Summary of the Invention] In order to achieve the above object, the present invention expands the pixel width of a character signal to match the NTSC signal, and for each pixel of the character signal with the expanded pixel width, A pixel string including a plurality of pixels located before and after each is extracted, and among the pixels constituting this pixel string, a pixel with a specific signal level, for example, a pixel of "1", is arranged in an isolated state. At least determine whether the pixel is in the first state, the second state exists every other pixel, or the third state exists continuously, and based on this determination result, the pixel is The signal level is set to a predetermined second level in the second state, and the signal level is set to a predetermined second level in the second state.
In the above state, the level is variably set to a first level higher than the second level, and in the third state, at least a third level lower than the second level is variably set. [Embodiment of the Invention] FIG. 2 is a circuit configuration diagram of a signal level control circuit which is a main part of a character signal conversion circuit in an embodiment of the present invention.
This is provided in place of a, 2b, and 2c. Note that a signal level control circuit is provided for each of the R, G, and B signals RS, GS, and BS, but since each circuit has the same configuration, only one of them is shown in FIG. This signal level control circuit includes a delay circuit 11 that expands the pixel width of a character signal (for example, an R signal RS) in the horizontal direction, and a delayed character signal RDS output from this delay circuit 11 that is synchronized with a clock signal CK for each pixel. and a 5-bit shift register 12 for shifting and inputting, and this shift register 12.
a determination circuit 13 to which the parallel outputs of are supplied, and a latch circuit 1 that latches the determination output of this determination circuit 13
4 and a signal level variable circuit 15. The judgment circuit 13 is composed of a read-only memory, and guides the parallel output from the shift register 12 as an address signal, and outputs the judgment value stored in the storage area designated by this address signal to the corresponding terminal D 1 . , D 2 , D 3 , and D 4 . Here, the storage contents of the ROM are set as shown in the following table.

【表】【table】

〔発明の効果〕〔Effect of the invention〕

以上詳述したように本発明は、遅延キヤラクタ
信号の各キヤラクタ毎に、この画素の前および後
に各々位置する複数の画素を含む画素列を抽出
し、この画素列を構成する各画素のうち特定の信
号レベルの画素、例えば“1”の画素の配列状態
が、孤立して存在している第1の状態か、1画素
おきに存在している第2の状態か、あるいは連続
して存在している第3の状態かを少なくとも判定
し、この判定結果に従つて上記当該画素の信号レ
ベルを、上記第2の状態では所定の第2のレベル
に、上記第1の状態では上記第2のレベルよりも
高い第1のレベルに、かつ上記第3の状態では上
記第2のレベルよりも低い第3のレベルに少なく
ともそれぞれ可変設定するようにしたものであ
る。 したがつて本発明によれば、縦横各輝線の方向
や文字の形態によらず、明るさが均一で明瞭な表
示を行なわせ得るキヤラクタ信号変換回路を提供
ることができる。
As described in detail above, the present invention extracts, for each character of a delayed character signal, a pixel string including a plurality of pixels located before and after this pixel, and identifies a The arrangement state of pixels with a signal level of , for example, pixels of "1", is the first state that exists in isolation, the second state that exists every other pixel, or the arrangement state that exists continuously. According to the result of this determination, the signal level of the pixel is set to a predetermined second level in the second state, and to a predetermined second level in the first state. The first level is higher than the first level, and in the third state, the third level is lower than the second level. Therefore, according to the present invention, it is possible to provide a character signal conversion circuit that can provide a clear display with uniform brightness regardless of the direction of vertical and horizontal bright lines or the form of characters.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来におけるキヤラクタ信号変換回路
のブロツク構成図、第2図は本発明の一実施例に
おけるキヤラクタ信号変換回路の要部構成を示す
回路図、第3図は第2図に示した回路の作用説明
に用いるための信号波形図である。 11……遅延回路、12……シフトレジスタ、
13……判定回路(ROM)、14……ラツチ回
路、15……信号レベル可変回路、16……論理
回路。
FIG. 1 is a block diagram of a conventional character signal conversion circuit, FIG. 2 is a circuit diagram showing the main part configuration of a character signal conversion circuit according to an embodiment of the present invention, and FIG. 3 is the circuit shown in FIG. FIG. 3 is a signal waveform diagram for use in explaining the action of FIG. 11...Delay circuit, 12...Shift register,
13...Determination circuit (ROM), 14...Latch circuit, 15...Signal level variable circuit, 16...Logic circuit.

Claims (1)

【特許請求の範囲】 1 キヤラクタ信号をNTSC信号に変換するキヤ
ラクタ信号変換回路において、 キヤラクタ信号の各画素をNTSC信号に適合す
る時間幅に拡大する手段と、 この手段から出力されるキヤラクタ信号の各画
素毎に当該画素の前および後に各々位置する複数
の画素を含む画素列を抽出し、この画素列を構成
する各画素のうち特定の信号レベルを有する画素
の配列状態が、孤立して存在している第1の状態
か、1画素おきに存在している第2の状態か、あ
るいは連続して存在している第3の状態かを少な
くとも判定する手段と、 この手段による判定結果に従つて前記当該画素
の信号レベルを、前記第2の状態では所定の第2
のレベルに、前記第1の状態では前記第2のレベ
ルよりも高い第1のレベルに、かつ前記第3の状
態では前記第2のレベルよりも低い第3のレベル
に少なくともそれぞれ可変設定する信号レベル可
変手段とを具備したことを特徴とするキヤラクタ
信号変換回路。
[Scope of Claims] 1. In a character signal conversion circuit that converts a character signal into an NTSC signal, means for enlarging each pixel of the character signal to a time width compatible with the NTSC signal, and each of the character signals output from this means. For each pixel, a pixel string including a plurality of pixels located before and after the pixel is extracted, and among the pixels composing this pixel string, an array state of pixels having a specific signal level exists in isolation. means for at least determining whether the first state is present at every other pixel, the second state is present at every other pixel, or the third state is continuously present; The signal level of the pixel is set to a predetermined second level in the second state.
a first level higher than the second level in the first state, and a third level lower than the second level in the third state. A character signal conversion circuit comprising level variable means.
JP58052109A 1983-03-28 1983-03-28 Character signal converting circuit Granted JPS59178091A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58052109A JPS59178091A (en) 1983-03-28 1983-03-28 Character signal converting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58052109A JPS59178091A (en) 1983-03-28 1983-03-28 Character signal converting circuit

Publications (2)

Publication Number Publication Date
JPS59178091A JPS59178091A (en) 1984-10-09
JPH0428111B2 true JPH0428111B2 (en) 1992-05-13

Family

ID=12905691

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58052109A Granted JPS59178091A (en) 1983-03-28 1983-03-28 Character signal converting circuit

Country Status (1)

Country Link
JP (1) JPS59178091A (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56108185U (en) * 1980-01-18 1981-08-22

Also Published As

Publication number Publication date
JPS59178091A (en) 1984-10-09

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