JPH04281524A - Floating point arithmetic processor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a floating-point arithmetic processing device that performs floating-point addition processing on digital data of predetermined bits, and more particularly to a floating-point arithmetic processing device that increases arithmetic precision without increasing the width of a bus for data transmission.

0002

2. Description of the Related Art Conventionally, when performing digital operations, the number of data bits that can be handled has been limited by the bus width of an input/output data bus. In other words, if the data bus is 8 bits, the input data will also be 8 bits.
The output result of the operation is also 8 bits. Therefore, when performing decimal point calculations, floating point calculations are often performed in order to increase the number of effective bits (number of effective digits) as much as possible. In such floating point calculations, if the size of the data to be handled is approximately the same, calculations can be performed with fairly high precision.

0003

However, if the positions of the decimal points of the data to be subjected to arithmetic processing differ greatly, there may be cases where floating point arithmetic cannot perform effective arithmetic. For example, in a digital filter, an operation is used in which the results obtained by multiplying by the same coefficient are sequentially added to obtain the total sum. In the case of such an operation, the numbers added each time are small, but when these numbers are cumulatively added, the cumulatively added value becomes a considerably large number. Then, since the current addition value, which is a small value, is added to the previous addition result, which has a large value, the numbers are added with considerably different decimal point positions. Therefore, when such addition is performed, there is a problem that the error becomes large depending on the floating point calculation.

On the other hand, in order to solve such problems, it is necessary to increase the bus width and increase the number of effective digits. However, increasing the bus width increases the circuit scale of the data processing device and also increases power consumption.

SUMMARY OF THE INVENTION An object of the present invention is to provide a floating point arithmetic processing device that can improve the precision of floating point arithmetic operations without increasing the bus width.

[0006]

[Means for Solving the Problems] A floating point arithmetic processing device according to the present invention is a floating point arithmetic processing device that calculates a sum by sequentially adding floating point numbers to a predetermined number sequence, and which calculates a sum by sequentially adding points. A sum calculation section, a subtraction section that subtracts the previous addition result from the current addition result obtained by this sum calculation section to obtain the rounded addition value actually added by floating point addition, and a subtraction section that calculates the rounded addition value actually added by floating point addition. An error calculation unit that calculates the rounding error in the current operation by subtracting the rounded addition value obtained by the subtraction unit from the added value, and a cumulative error calculation unit that calculates the cumulative error by adding the rounding errors of this error calculation unit. and a correction section that adds an accumulated error to the calculation result of the addition section and corrects the addition result.

[0007]

[Operation] As described above, in the present invention, the sum calculation section calculates the sum by integrating the addition values sequentially supplied as in the conventional case. The sum calculated by this sum calculation unit is based on floating point arithmetic and is rounded due to the limit on the number of significant digits. By subtracting the previous addition result from the result obtained by the summation calculation section, the summation calculation section can calculate the rounded addition value that was actually added this time. Here, the rounding error in the current addition operation is calculated by finding the difference between the rounded addition value and the current addition value. The value of this rounding error is always smaller than the added value. Therefore, even if this rounding error is cumulatively calculated, the cumulative error does not become a very large number. Therefore, the error calculation section performs a highly accurate cumulative error calculation.

[0008] Therefore, by adding this cumulative error to the sum which is the final result of the sum calculation section, a highly accurate cumulative calculation value can be obtained. All of these operations can be performed without increasing the bus width, and highly accurate operations can be achieved without increasing the bus width.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a floating point arithmetic processing device according to the present invention, particularly one that performs addition of the formula S=Σai i=0 to n, will be described with reference to the drawings.

FIG. 1 is a block diagram showing the overall structure of the embodiment, which includes a sum calculation section 10, a subtraction section 12, an error calculation section 14,
It consists of a cumulative error calculation section 16 and a correction section 18. The total sum calculation unit 10 has an adder 10a, and the input addition value ai and the output Si− from the adder 10a
Add 1. Here, this addition operation is performed every clock, but since this operation causes a delay of one clock, the output of the adder 10a is returned to the input as it is, so that the adder 10a sequentially adds the addition value ai. It happens.

That is, in this sum calculation section 10, the calculation Si=Si-1+ai is performed.

Next, this addition result Si is sent to the subtractor 12
sent to. The subtracter 12 is composed of a subtracter 12a and a delayer 12b, and the subtracter 12a subtracts the signal for the addition result from the sum calculation unit 10 and the signal for the previous addition result that is delayed once, and rounds the result. Post-added value ti
seek. This rounded addition value ti is calculated by the sum calculation unit 10
This is a subtraction of the two actual rounded addition values output in , and represents the addition value actually added in the floating point operation.

That is, in this subtraction section 12, t
The calculation i = Si - Si-1 is performed.

Next, the rounded addition value ti, which is the calculation result of the subtraction unit 12, is supplied to the error calculation unit 14. This error calculation section 14 includes a subtracter 14a and two delay devices 14b.
, 14c. Then, the rounded addition value ti
is input as is to the subtractor 14a, and the current addition value ai
is input to the subtracter 14a via two delay devices 14b and 14c. Here, the rounded addition value ti is input to the adder 14a via the two adders 10a and 12a, so it is delayed by two clocks. Therefore, the addition values ai and ti inputted to the subtracter 14a via the two delay devices 14b and 14c are both related to the current addition. Therefore, the difference between the value ti actually added in the floating point operation and the added value ai to be added is obtained in the subtracter 14a.

That is, the error calculation unit 14 performs the calculation αi =ai −ti.

The rounding error αi calculated by the error calculating section 14 is supplied to a cumulative error calculating section 16 which cumulatively adds the rounding errors. The cumulative error calculation unit 16 includes an adder 16a that cumulatively adds rounding errors αi.
For this purpose, the output of the adder 16a is returned to the input side. Since the output of this adder 16a is also delayed by one clock, the calculation βi = βi-1 + αi is performed in this adder 16a.

The output of the sum calculation section 10 and the output of the cumulative error calculation section 16 described above are supplied to a correction section 18. This correction section 18 includes an adder 18a, and includes the above-mentioned sum calculation section 10, subtraction section 12, and error calculation section 14.
, the calculation is performed only when all the calculations in the cumulative error calculating section 16 are completed. That is, when the input of the addition value ai is completed and all calculations regarding it are completed, the cumulative values that are the results of calculations in the adders 10a and 16a at that time are added.

That is, the calculation Si=Si+βi is performed.

[0019] Here, all such operations are performed via buses having the same bit width. However, the value of the cumulative error in the cumulative error calculating section 16 is quite small, and the cumulative calculation is performed with sufficient accuracy. Therefore, the addition result S after correction outputted by the correction unit 18
Regarding *, the error is very small. Therefore, highly accurate cumulative addition operations can be achieved without increasing the bus width.

Various types of equipment are controlled using microcomputers and the like, but in such processing, specific arithmetic processing is often performed by a specific gate array or the like without using the CPU. This is because the load on the CPU is reduced and the gate array that performs only predetermined specific calculations allows high-speed and highly accurate calculations. If the configuration of this embodiment is utilized in such an arithmetic processing section, the configuration of the gate array can be simplified and highly accurate arithmetic operations can be performed.

[0021]

As described above, according to the floating point arithmetic processing device of the present invention, high-precision cumulative addition operations can be performed without increasing the bus width.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the overall configuration of a floating-point arithmetic processing device according to the present invention.

[Explanation of symbols]

10 Total sum calculation section 12 Subtraction section 14 Error calculation section 16 Cumulative error calculation section 18 Correction section

Claims (1)

[Claims] 1. A floating-point arithmetic processing device that calculates a sum by sequentially adding floating-point numbers to a predetermined sequence of numbers, comprising: a sum calculation unit that sequentially adds points and calculates the sum; A subtraction unit subtracts the previous addition result from the addition result to obtain the rounded addition value actually added by floating-point addition, and a rounded addition value obtained by the subtraction unit from the value added in the current operation. An error calculation section that calculates the rounding error in the current operation by subtracting, a cumulative error calculation section that adds the rounding error of this error calculation section to calculate the cumulative error, and a cumulative error calculation section that adds the cumulative error to the calculation result of the addition section. A floating point arithmetic processing device comprising: a correction section that corrects a result.