JPH04282931A - Clock selection distribution section - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock selection/distribution section for a synchronous transmission system in a synchronous network, which inputs clocks from the 0 system and 1 system, selects the normal one, and outputs it.

FIG. 6 is a diagram showing an example of clock supply in a synchronous network, and FIG. 7 is an example of a clock supply system diagram. In recent years, transmission devices have been transitioning from stuffed multiplex transmission systems to synchronous multiplex transmission systems. The feature of this synchronous multiplex transmission system is that all networks are synchronized with the main master clock and the signals are multiplexed.The source of the master clock is located in Tokyo-Osaka in Japan, and normally the master clock in Tokyo is the source of the master clock. The synchronization network is operated using a clock, and in the event of a failure, it switches to the Osaka master clock to ensure the quality of the synchronization network.

Furthermore, the slave station 61 in FIG. 6 extracts a clock from the signal transmitted from the transmitting section 66 of the master station 60 having a master clock supplying section 63 in the clock extracting section 69 of the receiving section, and supplies the clock. The slave station 62 extracts the clock from the signal transmitted from the transmitting unit 67 of the slave station 61 in the clock extracting unit 70 of the receiving unit, and outputs the clock to the clock supplying unit 65. Each device operates in synchronization with this clock.

[0004] Therefore, if the clock supply from the clock supply sections 64 and 65 is cut off, there will be no clock inside the device, and the operation will stop. Therefore, as shown in FIG.
Using two systems of clocks from 1, the clock receiving section 82
, 83, and transmits the respective clocks to the clock selection/distribution sections 84, 85.The clock selection/distribution sections 84, 85 select the clocks, so that even if one system fails, the other system's clock is supplied to the inside of the device. We are trying to improve reliability.

Since the clock receiving sections 82, 83 and clock selection/distributing sections 84, 85 shown in FIG. 7 are the heart of the device, they are generally constructed from independent panels, etc., and are replaceable in the event of a failure. Connected with a connector.

[0006]

2. Description of the Related Art FIG. 4 is a block diagram of a conventional clock receiving section and a clock selection/distribution section, and FIG. 5 is a time chart of each section in FIG. In the case where the clock is turned off later than the uninstalled information shown in the table, (B) shows the case where the clock is turned off before the uninstalled information when the clock receiver is removed, and (A) and (B) a to g corresponds to points a to g in FIG.

In FIG. 4, clock receivers 40 and 41 that receive and output clocks of the 0 and 1 systems have the same configuration, so the explanation will be based on the clock receiver 40. The clock receiving sections 40 and 41 are connected to the clock selection and distribution section 42 through connectors, and points b and d are shown in FIGS. 5A and 5B.
) is at L level as shown in b and d of FIG.

[0008] Also, the connector is connected to, for example, the clock receiving section 40.
If you pull out the , you will usually see the implementation of the unplugged one,
The pin on the side of point b, which is not mounted, is removed first, and the pin on the clock supply side of point a is removed later.

[0009] Furthermore, when the disconnection detecting section 43 of the clock receiving section 40 detects a disconnection of the clock, the output, which is normally at the ground level, is set to the open level. The selectors 47 and 48 of the clock selection and distribution section 42 are supplied with 0-system and 1-system clocks from the clock reception sections 40 and 41, and the reset terminal and set terminal of a flip-flop (hereinafter referred to as FF) 49 are Usually b in Figure 5(A)(B)
, d is inverted by the NOT circuits 51 and 52, and the H level shown in FIG. 5 (A
) The H level shown in e of (B) is output and input to the FF 50.

From the output Q of FF50, FIG. 5(A)
The H level shown at f in (B) is output and the selector 47
to select the 0 system clock and output it as shown in g in FIGS. 5(A) and (B), and output the L level from the inverted output *Q of the FF 50, input it to the selector 48, and select the 1 system clock. It is selected and inputted to the clock terminal of FF50.

For example, if the clock receiving section 40 is pulled out by mistake, the level at point b becomes H level as shown in b in FIGS. 5(A) and 5(B), and the level of the output Q of the FF 49 becomes As shown in e of B), it becomes L level and FF50
The output Q of FIG. 5(A) is as shown in f of FIG.
) L at the rising point of the 1st system clock shown in c of (B)
level, the inverted output *Q of FF 50 becomes H level, the selector 47 selects the 1 system clock, and as shown in FIG.
A) Output the clock as shown in g in (B) and selector 4
8 selects the 0 system clock.

If the clock receiving unit 40 is pulled out here, the pin at point b, which indicates whether it is mounted or not, is pulled out first and the level becomes H level as shown in FIG. 5(A)b, and then the pin at point a When the pin is pulled out and the clock is cut off as shown in FIG. 5(A) a, the switching output is switched without clock loss as shown in FIG. 5(A) g.

Furthermore, if the 0 system clock is disconnected without pulling out the clock receivers 40 and 41, the disconnection detector 4
The output of 3 is open, and the output of EX-OR (exclusive OR circuit) 45 becomes H level, and the level change shown in b of FIGS. You can switch without any omissions.

In FIG. 4, R3 to R6 are bull-up resistors, 44 is an disconnection detection section, and 46 is an EX-OR.

[0015]

[Problem to be Solved by the Invention] However, depending on the angle of the connector when pulling out the clock receiving section, a
In some cases, the pin at point B goes out first and the pin at point B goes out later, and in this case, as shown in a and b in Fig. 5(B), the clock at point a goes out before the level at point b becomes H level. There is a problem in that the clock is cut off as shown in FIG. 5(B)g, and an error occurs in the data of the main signal.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a clock selection/distribution section that can switch the clock without causing clock loss even when the clock receiving section is pulled out from the connector at an angle or when the clock is disconnected.

[0017]

[Means for Solving the Problems] FIG. 1 is a block diagram of the principle of the present invention. As shown in FIG. 1, the clock selection and distribution section inputs clocks from the 0 system and 1 system, selects one of them, and selects and outputs the other clock when the selected clock is disconnected. The 0 system clock is input to the clock output OR circuit 3 via the first AND circuit 1, the 1 system clock is input to the clock output OR circuit 3 via the second AND circuit 2, Further, the output and the inverted output of FF4 are input to the first and second AND circuits 1 and 2, respectively, and clocks are input from the 0 system and 1 system to monitor each other, so that the clock of the 0 system When the FF becomes disconnected, the corresponding FF
The level of the first trigger signal input to the reset terminal of FF4 is inverted within 1/2 cycle of the clock, and when the first system clock is cut off, the level of the first trigger signal input to the set terminal of FF4 is inverted.
A disconnection detection/level conversion means 5 is provided for inverting the level of the trigger signal within 1/2 cycle of the clock.

[0018]

[Operation] According to the present invention, for example, the output Q of FF4 outputs an H level, the inverted output *Q outputs an L level, and the 0 system clock is sent from the AND circuit 1 via the OR circuit 3. Assume that the AND circuit 2 prohibits the output.

When the 0-system clock is disconnected due to the clock receiving section being pulled out, or when the 0-system clock is disconnected, the 1-system monitoring the 0-system clock of the disconnection detection/level conversion means 5 is activated. 1/1 of the clock
Within two cycles, the level of the first trigger signal input to the reset terminal of FF4 is inverted, the output Q is set to L level, the inverted output *Q is set to H level, and the AND circuit 1 is set to an output inhibited state, The AND circuit 2 outputs the 1st system clock, and the 1st system clock is outputted via the OR circuit 3.

In other words, when the 0-system clock is cut off, the clock switches to the 1-system clock within 1/2 of the clock cycle.
Even if the clock is disconnected due to the withdrawal of the clock receiving section or the clock is disconnected, switching can be performed without causing any missing clock.

[0021] In this case, the connector between the clock receiving section and the clock selection distribution section does not use mounted or unmounted pins, so the pins may have the same normal length, and the clock receiving section It may be something that receives and outputs.

[0022]

[Embodiment] FIG. 2 is a block diagram of a clock selection distribution section according to an embodiment of the present invention, and FIG. 3 is a time chart of each section in FIG.
A to r correspond to points a to r in FIG. 2 .

R1 and R2 in FIG. 2 are pull-up resistors,
The H level is fixedly input to the inputs of FFs 12 to 17. The clock receiving units 82 and 83 receive and output clocks of the 0 system and 1 system, respectively, and the buffer 1
The 0-system clock shown in FIG. 3a that has passed through 0 is supplied to the AND circuit 1 and the clock terminals of FFs 12 and 15, and passes through the NOT circuit 20, delay circuit DLY3, and differentiation circuit 26, and is then
It becomes a pulse as shown in e, and is supplied to the reset terminal of FF13, and is also supplied to the NOT circuit 21 and delay circuits DLY4 and DL.
Y5 passes through the differentiating circuit 27, becomes a pulse as shown in FIG. 3i, and is supplied to the reset terminal of the FF 14.

The 1-system clock shown in FIG. 3b that has passed through the buffer 11 is supplied to the AND circuit 2 and the clock terminals of FFs 13 and 15, and is also supplied to the NOT circuit 22, delay circuit DLY6,
It passes through the differentiating circuit 28 and becomes a pulse as shown in FIG. 3k,
It is supplied to the reset terminal of FF15, and also the knot circuit 19.
, passes through delay circuits DLY1, DLY2, and differentiation circuit 26,
The pulse becomes a pulse as shown in FIG. 3c, and is supplied to the reset terminal of the FF 12.

In this case, the amount of delay caused by the delay circuit is as follows. DLY1+DLY2=DLY4+DLY5<1/2 cycle of clock DLY3=DLY6 DLY1+DLY2>DLY3
DLY4+DLY5>DLY6 In normal case, the output of FF12 is reset to L level by the pulse of the differentiating circuit 25 shown in FIG. 3c, as shown in FIG. 3d, and goes to H level at the rising edge of the 0 system clock shown in FIG. 3a. is supplied to the clock terminal of FF16, and the output of FF16 is at H level as shown in Figure 3h.
It is input to the reset terminal of F4.

On the other hand, the output of the FF 14 is as shown in FIG. 3j.
It is reset by the pulse of the differentiating circuit 27 shown in FIG.
At the rising edge of the 1st system clock shown in FIG. 3b, the signal becomes H level and is supplied to the clock terminal of FF17, and the output of FF17 is at H level as shown in FIG. 3n.
It is input to the set terminal of FF4.

Therefore, the output Q of FF4 is input to the AND circuit 1 at H level as shown in FIG. 3o, and is inputted to the AND circuit 1 as shown in FIG.
The system clock is outputted via the OR circuit 3 as shown in FIG. 3r.

On the other hand, the inverted output *Q of FF4 is input to the AND circuit 2 at L level, and the output of the 1-system clock is prohibited as shown in FIG. 3q. The pulse shown in FIG. 3c of the differentiating circuit 25 is inverted by the NOT circuit 23 and inputted to the NAND circuit 29, and the output of the FF 13 is reset by the pulse shown in FIG. 3e of the differentiating circuit 26 and becomes L as shown in FIG. 3f. At the rising edge of the 1st system clock, the signal becomes H level and is supplied to the NAND circuit 29, and the output of the NAND circuit 29 becomes H level as shown in FIG. 3g.

Further, the pulse shown in FIG. 3i of the differentiating circuit 27 is inverted by the NOT circuit 24 and inputted to the NAND circuit 30, and is also input to the F
As shown in FIG. 3l, the output of F15 is reset to the L level by the pulse shown in FIG. 3k of the differentiating circuit 28, and becomes 0.
At the rising edge of the system clock, the signal becomes H level and is supplied to the NAND circuit 30, and the output of the NAND circuit 30 becomes H level as shown in FIG. 3m.

Therefore, for example, at the point of disconnection in FIG. 3a, 0
When the system clock is disconnected, the output of the differentiating circuit 26 is as shown in Fig. 3e.
As shown in Figure 3, the output of FF13 becomes H level.
The NAND circuit 29 outputs a pulse from the differentiating circuit 25 as shown in FIG. 3g, and the FF
16 is reset and the output is set to L level as shown in FIG. 3h.

Further, the output of the differentiating circuit 27 remains at the H level as shown in FIG. 3i, and the output of the FF 14 remains at the H level as shown in FIG. 3j. Also, since no clock is input to the clock terminal of the FF 15, the output Q remains at the L level as shown in FIG. 3l and is applied to the NAND circuit 30, and the output of the NAND circuit 30 remains at the H level as shown in FIG. 3m.
The output of the FF 17 also remains at H level as shown in FIG. 3n.

Therefore, the output Q of FF4 becomes L level as shown in FIG. 3o, the inverted output *Q becomes H level, AND circuit 1 prohibits output as shown in FIG. 3p, and AND circuit 2 inhibits output as shown in FIG. 3q. Outputs the clock of Gotoku 1 system,
A switching clock with no gaps is outputted via the OR circuit 3 as shown in FIG. 3r.

In other words, even when the clock receiving section is pulled out from the connector at an angle, since the mounted and unmounted pins are not used, there will be a delay after the 0 system clock is disconnected, just like when the 0 system clock is disconnected. Since the clock is switched to the 1st system clock within 1/2 cycle of the clock of the delay of the circuit DLY1+DLY2, the clock is switched and output without missing a beat.

[0034]

As described in detail above, according to the present invention, even when the clock receiving section is pulled out from the connector at an angle, the clock signal is halved after the clock is cut off, just as when the clock is cut off. Since the clock is switched to the other system's clock within the cycle, there is an effect that the clock can be switched without causing clock gaps.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the principle of the present invention.

FIG. 2 is a block diagram of a clock selection distribution section according to an embodiment of the present invention;

[Figure 3] is a time chart of each part in Figure 2,

FIG. 4 is a block diagram of a conventional clock receiving section and a clock selection distribution section,

[Figure 5] is a time chart of each part in Figure 4,

[Figure 6] is 1
A diagram showing the clock supply of an example synchronous network,

FIG. 7 is an example clock supply system diagram.

[Explanation of symbols]

1 and 2 are AND circuits, 3 is OR circuits, 4, 12 to 17,
49, 50 are flip-flops, 5 is disconnection detection/level conversion means, 10, 11 are buffers, 19 to 24, 51, 5
2 is a knot circuit, 25 to 28 are differentiating circuits, 29, 30 are NAND circuits, 40, 41, 82, 83 are clock receiving sections, 43, 44 are disconnection detection sections, 45, 46 are exclusive OR circuits, 47 , 48 is a selector, 60 is a master station, 61, 62 are slave stations, 63 is a master clock supply section, 64, 65 are clock supply sections, 66, 67, 68 are transmitters, 69, 70 are clock extraction sections, 80 , 81 is a clock supply unit, 84,
Reference numeral 85 indicates a clock selection distribution section.

Claims (1)

[Claims] 1. A clock selection and distribution section that inputs clocks from the 0 system and 1 system, selects one of them, and selects and outputs the other clock when the selected clock is cut off. The system clock is the first AND circuit (1)
is input to the OR circuit (3) for clock output via
The system clock is input to the clock output OR circuit (3) via the second AND circuit (2), and the first and second AND circuits (1, 2) are connected to a flip-flop (4). The output and inverted output of the flip-flop (4) are respectively input, and clocks are input from the 0 system and 1 system to monitor each other, and when the clock of the 0 system is cut off, the clock is input to the reset terminal of the flip-flop (4). The level of the first trigger signal to be input to the set terminal of the flip-flop (4) is inverted within 1/2 period of the clock, and when the first system clock is disconnected, the level of the second trigger signal input to the set terminal of the flip-flop (4) is inverted. A clock selection/distribution section characterized in that it is provided with an interruption detection/level conversion means (5) that inverts at 1/2 cycle or less of a clock.