JPH04282970A - Deflection correction waveform generating circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a deflection correction waveform generation circuit used in monitor receivers and the like.

0002

2. Description of the Related Art In a deflection correction waveform generating circuit used in a monitor receiver or the like, a device has been proposed that generates a sawtooth wave, a parabolic wave, etc. as a correction waveform using the count value of a horizontal synchronizing signal. However, conventionally proposed devices are based on so-called hard logic such as analog circuits,
It consisted of digital adders and subtracters.

On the other hand, as cathode ray tubes become larger and flatter,
Requirements for image distortion accuracy are becoming stricter, and higher-order deflection correction waveforms are becoming necessary. In that case, conventionally proposed analog circuits and digital adders/subtracters
It has become difficult to obtain sufficient accuracy.

Furthermore, when forming a so-called multi-standard receiver, conventional analog circuits and digital adders/subtracters require adjustment for each system. Furthermore, the values of parameters adjusted for each of these systems must be held, and a memory or the like is required to store these values, resulting in problems such as an increase in circuit scale.

[0005]

[Problem to be Solved by the Invention] The problem that the invention aims to solve is that it is difficult to obtain high-order deflection correction waveforms due to the increase in size and flatness of cathode ray tubes with conventional devices composed of analog circuits and digital adders/subtracters. This is difficult to implement because the circuit scale increases when implementing multi-standardization.

[0006]

[Means for Solving the Problems] The present invention provides a multiplier (7)
The horizontal A count value (X) obtained by counting the synchronization signals is supplied, and a desired high-order formula [YSAW = (CX3 +DX2
+X)B+A:YPARA=(GX4 +X2 +HX
) FB2 +E], and the deflection correction waveform generation circuit multiplies the above count value by a predetermined coefficient (K1) to perform multi-standardization.

[0007]

[Operation] According to this, multi-standardization can be performed by multiplying the count value by a predetermined coefficient, and various desired correction waveforms can be obtained according to each system with a simple configuration. .

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows the configuration of the main parts of a deflection correction waveform generation circuit. In this figure, for example, twice the horizontal frequency (2f
The instruction address generator 1 is supplied with a 4 MHz clock signal and a 4 MHz clock signal. The value generated by this generator 1 is the instruction (I)
This ROM and RAM are supplied to ROM and RAM2.
The output of 2 is supplied to the address inputs of ROM 3 and RAM 4 for data, and to an instruction decoder 5.

The output of this ROM 3 is supplied to a multiplier 7 and a register 8 via a bus line 6. Also RAM4
The output of is supplied to the multiplier 7. The outputs of these multiplier 7 and register 8 are selected by selector 9 and sent to adder 10.
is supplied to Furthermore, the output of this adder 10 is supplied to first and second accumulators (ACC) 11 and 12. The output of the accumulator 12 is supplied to the adder 10, and the output of the accumulator 11 is supplied to the RAM 4, the multiplier 7, and the register 8 via the bus line 6. Further, the output of the accumulator 11 is supplied to the first and second output registers 13 and 14 via the bus line 6.

Furthermore, the operations of these multiplier 7, register 8, selector 9, adder 10, accumulators 11, 12, and output registers 13, 14 are controlled by signals from instruction decoder 5.

[0011] Then, for example, a horizontal frequency of 2
Count value (X
), this circuit generates a correction waveform consisting of a desired higher-order equation, such as a sawtooth wave [YSAW =
(CX3 +DX2 +X)B+A] and parabolic wave [Y
PARA=(GX4 +X2 +HX)FB2 +E]
is taken out. However, in these formulas, A is vertical shift, B is vertical size, C is S-curve correction, D is linearity,
E is the horizontal size, F is the pin amplifier, G is the pin phase, and H is the corner pin parameter. In addition, the output of the correction waveform is, for example, the value (
YSAW, YPARA) are taken out to output registers 13 and 14, and the outputs thereof are supplied to an output amplifier (not shown) of a horizontal deflection circuit, etc. through D/A converters 15 and 16.

Furthermore, the calculation of the above-mentioned correction waveform is performed, for example, as follows. That is, the following Table 1 is a program list for calculating the sawtooth wave [YSAW = (CX3 +DX2 +X)B+A] using the above-mentioned circuit.

[0013]

[Table 1]

In Table 1, the calculation is YSAW = (
((CX+D)X+1)X+0)B+A. Although the calculation is performed with 16-bit accuracy, the above-described circuit takes into account that the multiplier 7 has an 8×8-bit capability.

Therefore, in Table 1, column a is the address of the instruction ROM and RAM 2, and operations are performed in the order of these addresses. Column b indicates the type of instruction, where M is a multiplication instruction, L is a load instruction, and J is a jump instruction. Column c indicates the type of load instruction, where K>Y is memory and register, and X>Y register and register. Column d shows the calculation formula of the adder 10. The e column shows the register of X, where A is the upper 8 bits of accumulators 11 and 12, and B is the lower 8 bits. Note that this column e indicates the register to be multiplied in the multiplication instruction. The f column shows the register of Y, R is register 8, 1 is output register 13, and 2 is output register 14. The g column shows the addresses of ROM3 and RAM4. Note that this column g indicates the address of the coefficient in the multiplication instruction. The h column shows memory selection (ROM, RAM).

As a result, in the process of address 79, a value is loaded from address 0D of RAM 4 to register 8. Note that the above-mentioned supplied count value (X) is stored at this address 0D.

Next, in the processing at address 7a, a value is loaded from address 14 of RAM 4 to register 8, and 0 and the value of register 8 are added. The addition result is supplied to the accumulator 11. Please note that address 14
A linearity coefficient (D) is stored in .

Further, in the processing of address 7b, the lower 8 bits of accumulator 11 are multiplied by the contents of address 12 of RAM 4, and addition of 0 and the value of register 8 is performed in parallel. The addition result is supplied to accumulator 12. Further, the previous value of the accumulator 11 is retained. Note that address 12 contains the S-curve correction coefficient (
C) is stored. In this process of address 7b, C
A product-sum operation of X (lower) and 0+D is performed.

In addition, in the processing of address 7c, the upper 8 bits of accumulator 11 are multiplied by the contents of address 12 of RAM 4, and the value of accumulator 12 (
D) and C obtained by processing address 7b from multiplier 7
Addition of the value of X (lower)+D shifted to the lower 8 bits (selected by the selector 9) is performed in parallel. In the processing of address 7c, a product-sum operation of CX (upper) and CX (lower)+D is performed.

In the processing at address 7d, the value is loaded from address 16 of ROM 3 to register 8 in preparation for the next operation, and the value of accumulator 12 (
CX (lower) + D) and the CX (upper) value obtained by processing address 7c from multiplier 7 are performed in parallel. By processing this address 7d, CX (upper) + CX (
A product-sum operation of (lower) +D is performed, and the value of CX+D is supplied to the accumulator 11.

[0021] These processes are repeated sequentially, and the processing of address 80 produces (CX+D)X+1, the processing of address 84 produces ((CX+D)X+1)X, and the processing of address 89 produces (((CX+D)X+1)X+0 )B+A
=YSAW is supplied to the accumulator 11. This value YSAW is then supplied to the output register 13 by processing address 8a.

[0022] The following Table 2 shows the parabolic waves [YPARA
This is a program list for performing the calculation of =(GX4 +X2 +HX)FB2 +E] using the above-mentioned circuit.

[0023]

[Table 2]

Therefore, in this Table 2, the same processing as described above is repeated in order, and the processing of address 61 results in GX+0, the processing of address 65 results in (GX)X+1, and the processing of address 69 results in ((GX)X+1)X+H. , in the processing of address 6d, (((GX)X+1)X+H)X+0, in the processing of address 70, (((GX)X+1)X+H)XF
, in the processing of address 73 (((GX)X+1)X+H)
In the processing of XFB, address 77, (((GX)X+1)X
+H)XFB2 +E=YPARA value is supplied to accumulator 11. Then, by processing address 78, this value YPARA is supplied to output register 14.

Note that these processes are performed, for example, for each timing signal of twice the horizontal frequency (2fH) based on the count value (X) at that time.

In this circuit, consider a system in which the vertical frequencies are 60 Hz and 50 Hz, for example. In this case, the count value (X) obtained by counting the timing signal twice the horizontal frequency (2fH) mentioned above has a vertical frequency of 60Hz.
The waveform changes from 0 to 525 in the case of , and from 0 to 625 in the case of 50 Hz, and the waveform becomes as shown in FIG. However, in this case, if we consider the screen displayed on the cathode ray tube,
The screens of one field displayed are equal to each other. On the other hand, the correction waveforms of the sawtooth wave and the parabolic wave described above, for example, correspond to absolute positions on the screen.

Considering the count value (X) based on the screen, it becomes as shown by solid lines and broken lines in FIG. 3 for systems with vertical frequencies of 60 Hz and 50 Hz, respectively. That is, as is clear from this figure, the respective count values (X) are in a proportional relationship at their absolute positions on the screen. Therefore, if the count value used for calculation is The amount of image distortion with respect to the absolute position on the screen is constant regardless of the system, and there is no need to change parameters etc. for each system. Note that X* = K1
can be calculated by the multiplier 7.

Thus, according to the above-mentioned device, the count value (X
) by a predetermined coefficient (K1), multi-standardization can be performed, and with a simple configuration, various desired correction waveforms (YS
AW, YPARA).

Furthermore, in so-called HDTV, the screen aspect ratio is set at 16:9. However, such a monitor receiver for displaying HDTV is expensive. Therefore, it is conceivable to display such an HDTV signal on a conventional monitor receiver having an aspect ratio of 4:3. In that case, for example, the number of horizontal scanning lines in one frame is 52.
It has been considered to down-convert to 5 or 625 lines and display the vertical deflection width reduced, as shown in FIG. 4, for example.

When performing such a display, considering the count value (X), the aspect ratio is 4:3 and 1.
The case of 6:9 is shown by a solid line and a broken line in the figure, respectively. That is, as is clear from this figure, the respective count values (X) are in a proportional relationship at their absolute positions on the screen. Therefore, let the count value used for calculation be X**, and add a predetermined coefficient (K2 = 0.75
) by multiplying (X**=K2 X* ),
Even in such a display, various desired correction waveforms (YS
AW, YPARA) can be obtained.

Note that FIG. 5 shows the coefficient (K
1, K2) is shown. Note that the calculation of X**=K2 X* can also be performed by the multiplier 7. Also, as shown in the above figure, 16:
9 in the vertical center of the screen, add the distance C from the top of the screen to X** (X**=K2
+C). This addition calculation can be performed by the adder 10.

[0032]

[Effects of the Invention] According to the present invention, multi-standardization can be performed by multiplying the count value by a predetermined coefficient, and various desired correction waveforms can be obtained according to each system with a simple configuration. Now I can do it.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of an example of a deflection correction waveform generation circuit according to the present invention.

FIG. 2 is a diagram for explanation.

FIG. 3 is a diagram for explanation.

FIG. 4 is a diagram for explanation.

FIG. 5 is a diagram for explanation.

[Explanation of symbols]

1 Instruction address generator 2 Instruction ROM and RAM 3 ROM for data 4 RAM for data 5 Instruction decoder 6 Bus line 7 Multiplier 8 Register 9 Selector 10 Adder 11, 12 Accumulator 13, 14 Output register 15, 16 D/A converter

Claims (1)

[Claims] Claim 1: A multiplier, an adder, a memory storing data and coefficients, and a control means for controlling the operations of the multiplier, adder, and memory, and counting horizontal synchronization signals. A numerical value is supplied, and by repeatedly performing calculations from this counted value using the multiplier and adder described above, a correction waveform consisting of a desired higher-order formula is obtained with a simple configuration, and a predetermined coefficient is added to the counted value. Deflection correction waveform generation circuit that performs multi-standardization by multiplication.