JPH04287326A - Semiconductor device and its manufacture - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a dummy pattern is provided close to a rough portion of an integrated circuit pattern.

0002

2. Description of the Related Art Among fine patterns constituting an integrated circuit, a dummy pattern is sometimes placed close to a pattern (isolated pattern) that is located alone apart from other patterns. This is to ensure that the upper surface of the insulating layer deposited on these patterns is as flat as possible from the dense patterns to the isolated patterns. In other words, if a dummy pattern is not provided, a steep step will occur on the upper surface of the insulating layer near the isolated pattern, and wiring etc. formed on this insulating layer will easily break at the step. The purpose is to prevent problems such as

0003

By the way, in order to increase the speed of integrated circuits, it is required to reduce the wiring capacitance as much as possible. However, conventionally, the dummy patterns provided close to the isolated wiring patterns as described above were formed by patterning the same conductive layer as the wiring patterns. Therefore, the wiring pattern has stray capacitance between it and the semiconductor substrate, upper layer wiring, etc. via this dummy pattern, and thus the wiring capacitance increases. FIG. 2 is a schematic cross-sectional view showing a conventional isolated wiring 2 and a dummy pattern 1 provided close to it, and C1 is the capacitance between the dummy pattern 1 and the wiring 2;
C2 indicates a stray capacitance between the semiconductor substrate 3 and C3, and C3 indicates a stray capacitance between the upper layer electrode 4 including wiring. In the figure, numerals 5 and 6 are insulating layers. The present invention aims to reduce these capacitances, thereby making it possible to improve the operating speed of integrated circuits.

0004

[Means for Solving the Problems] The above object consists of a wiring pattern formed on one surface of a semiconductor substrate, and an insulating layer having an upper surface substantially at the same height as the wiring pattern, and the wiring pattern is A dummy pattern formed on the surface of the semiconductor substrate near a predetermined portion, an insulating layer made of a material different from the dummy pattern and covering the wiring pattern and the dummy pattern, and a conductive layer formed on the insulating layer. A semiconductor device according to the present invention, characterized in that it has
Alternatively, a wiring pattern is formed on one surface of the semiconductor substrate, a first insulating layer having substantially the same layer thickness as the wiring pattern is formed on the surface of the semiconductor substrate, and the first insulating layer is patterned. A dummy pattern is formed close to a predetermined portion of the wiring pattern, and a second dummy pattern is formed on the surface of the semiconductor substrate on which the wiring pattern and the dummy pattern are formed.
This is achieved by the method for manufacturing a semiconductor device according to the present invention, which includes the steps of: forming an insulating layer, and forming a conductive layer on the second insulating layer.

[0005]

[Operation] As shown in FIG. 1, the dummy pattern 11 is formed by forming the dummy pattern 11 placed close to the isolated wiring 2 using an insulating layer having the same layer thickness as the wiring 2. It is possible to reduce the wiring capacitance generated through the wiring. The other parts in FIG. 1 are the same as in FIG. 2.

[0006]

Embodiment The steps of an embodiment of the present invention will be explained with reference to FIG. As shown in Figure (a), an insulating layer 5 made of PSG (phosphosilicate glass) with a thickness of about 0.4 to 1.0 μm is formed on a semiconductor substrate 3 made of, for example, a silicon wafer, and then an insulating layer 5 is formed. A conductive layer made of aluminum with a thickness of approximately 1 μm is deposited on layer 5, and is patterned to form a wiring pattern. Wiring 2 in the same diagram
indicates an isolated one of the wiring patterns.

Next, as shown in the same figure (b),
An insulating layer 10 is formed on a semiconductor substrate 3. The insulating layer 10 may be formed of a well-known insulator such as polyimide resin or PSG using a well-known method such as spin coating or CVD (chemical vapor deposition). Next, the insulating layer 10 is etched back until the wiring 2 is exposed, and then the insulating layer 10 is patterned to form a dummy pattern 11 made of the insulating layer 10, as shown in FIG. 2(c). This patterning may be performed by, for example, a well-known lithographic technique using a resist mask and dry etching. When the insulating layer 10 is made of resin, dry etching using oxygen-containing gas as an etchant may be applied. In the case of the insulating layer 10 made of polyimide resin, wet etching using hydrazine as an etchant can be used. In this way, the dummy pattern 11 having an upper surface approximately at the same height as the wiring 2 is placed close to the wiring 2.

Next, as shown in FIG. 2D, an insulating layer 6 made of, for example, PSG is formed on the semiconductor substrate 3 to cover the wiring 2 and the dummy pattern 11. By providing the dummy pattern 11 close to each other, the upper surface of the insulating layer 6 is flattened from above the wiring 2 to the vicinity thereof. A conductive layer (not shown) is deposited on this insulating layer 6 and patterned to form upper layer wiring or electrodes.

[0009] In the above, the dummy pattern 11
It goes without saying that the wiring pattern including the wiring 2 may be formed first and then the wiring pattern including the wiring 2.

0010

[Effects of the Invention] According to the present invention, since the dummy pattern provided close to the fine wiring arranged isolated from the dense patterns in a high-density integrated circuit is composed of an insulating layer, the dummy pattern is made of an insulating layer. This has the effect of reducing the capacitance of the wiring formed through the wires, thereby making it possible to speed up the integrated circuit.

[Brief explanation of the drawing]

[Figure 1] Diagram explaining the principle of the present invention

[Figure 2] Illustration of conventional problems

[Figure 3] Process explanatory diagram of one embodiment of the present invention

[Explanation of symbols]

1, 11 Dummy pattern 2 Wiring 3 Semiconductor substrate 4 Upper layer electrode 5, 6, 10 Insulating layer

Claims (2)

[Claims] 1. A semiconductor substrate comprising a wiring pattern formed on one surface of a semiconductor substrate, and an insulating layer having an upper surface substantially at the same height as the wiring pattern, and in close proximity to a predetermined portion of the wiring pattern. A dummy pattern formed on the surface of the substrate, an insulating layer made of a material different from the dummy pattern and covering the wiring pattern and the dummy pattern, and a conductive layer formed on the insulating layer. Semiconductor equipment. 2. Forming a wiring pattern on one surface of a semiconductor substrate; forming a first insulating layer having substantially the same layer thickness as the wiring pattern on the surface of the semiconductor substrate; forming a second insulating layer on the surface of the semiconductor substrate on which the wiring pattern and the dummy pattern are formed; A method for manufacturing a semiconductor device, comprising the step of forming a conductive layer on the second insulating layer.