JPH0429988B2 - - Google Patents
Info
- Publication number
- JPH0429988B2 JPH0429988B2 JP57113201A JP11320182A JPH0429988B2 JP H0429988 B2 JPH0429988 B2 JP H0429988B2 JP 57113201 A JP57113201 A JP 57113201A JP 11320182 A JP11320182 A JP 11320182A JP H0429988 B2 JPH0429988 B2 JP H0429988B2
- Authority
- JP
- Japan
- Prior art keywords
- test
- storage
- tested
- yield
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000012360 testing method Methods 0.000 claims description 108
- 239000004065 semiconductor Substances 0.000 claims description 11
- 238000005259 measurement Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000002950 deficient Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Description
【発明の詳細な説明】
本発明は半導体集積回路等の試験装置に関す
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a testing device for semiconductor integrated circuits and the like.
最近の半導体集積回路は大規模化がめざまし
く、これに伴い試験装置は高機能化、複雑化、高
価格化しており、また試験項目数および試験時間
は非常に増大してきているので、試験コストはど
んどん大きくなりつつある。 Recently, the scale of semiconductor integrated circuits has increased dramatically, and with this, test equipment has become more sophisticated, complex, and expensive.Also, the number of test items and test time have increased significantly, so test costs are increasing. It's getting bigger and bigger.
一般に半導体集積回路等を試験・検査するには
試験装置が使用され、個々の品種に応じて、試験
条件、試験項目あるいは試験の順序、流れを定義
する試験プログラムが準備される。半導体集積回
路等の被試験物は通常全数、試験・検査をなされ
るが、その際試験プログラムが試験装置に入力さ
れ、試験装置は試験プログラムに基ずき、被試験
物を試験し良、不良の判定を行う。 Generally, test equipment is used to test and inspect semiconductor integrated circuits, etc., and test programs are prepared that define test conditions, test items, test order, and flow depending on each product type. Normally, all devices under test such as semiconductor integrated circuits are tested and inspected. At that time, a test program is input to the test equipment, and the test equipment tests the products under test and determines whether they are good or bad based on the test program. Make a judgment.
しかしながら、前述したように試験装置は高価
格化し一方被試験物の試験項目数は増大し、試験
時間が増大しているために、試験装置の処理量は
低下し、試験コストの増大をまねいている。 However, as mentioned above, testing equipment has become more expensive, the number of test items for test objects has increased, and testing time has increased, resulting in a decrease in the throughput of testing equipment and an increase in testing costs. There is.
本発明はこのような問題点を解決する試験装置
を提供するものである。 The present invention provides a testing device that solves these problems.
従来、半導体集積回路等の試験は第１図の流れ
図に示すように良品については第１テストから第
Ｎテストまで全項目についてなされてきた。とこ
ろが、半導体集積回路等の製造技術の進歩は著し
く非常に高い歩留りを示すようになつてきたこ
と、また、半導体集積回路等の製造プロセスは基
本的にバツチ処理であり、同一ロツト内の半導体
集積回路等は同様の特性を示すことにより、第１
テストから第Ｎテストのいくつかのテストについ
ては、テスト結果がすべて良ということが、しば
しばである。 Conventionally, semiconductor integrated circuits and the like have been tested for all items from the first test to the Nth test for non-defective products, as shown in the flowchart of FIG. However, advances in manufacturing technology for semiconductor integrated circuits, etc., have led to extremely high yields, and the manufacturing process for semiconductor integrated circuits, etc. is basically batch processing, which means that semiconductor integrated circuits within the same lot are By showing similar characteristics, the circuit etc.
It is often the case that all of the test results from test to Nth test are good.
本発明はこの点に注目し試験コストの低減を目
的としたものである。 The present invention focuses on this point and aims to reduce test costs.
テスト結果がすべて良であるテストについては
試験を省略することが可能であり、テスト結果が
すべて良であると予想されるテストについては、
前述の理由により、試験を省略することが可能と
判断される。 For tests where all test results are good, the test can be omitted, and for tests where all test results are expected to be good, the test can be omitted.
For the reasons mentioned above, it is judged that the test can be omitted.
以下、本発明について説明する。 The present invention will be explained below.
本発明の一実施例を第２図に示す。１は中央処
理装置（以下CPUと略す）で、試験装置の制御
を行う、２は測定部、３は被試験物、４は記憶部
でこの中には試験プログラムの格納部５、第１テ
ストから第Ｎテストまでのそれぞれのテスト結果
の格納部６1，６2，６3，…，６N，第１テストか
ら第Ｎテストまでのそれぞれのテストの基準歩留
り格納部７1，７2，７3，…，７N、全テストにつ
いて試験する被試験物の個数格納部８を含む。動
作を説明すれば以下のようになる。１ロツトの被
試験物ｐ個を試験するにあたり、あらかじめ第１
図に示すような被試験物の試験プログラムが試験
プログラム格納部５に格納され被試験物ｐ個中、
全テストについて試験する被試験物の個数ｑが格
納部８に格納され、ｑ個のテスト結果に応じて、
テストの省略可否の判断基準となる基準歩留りが
各テストについて格納部７1，７2，７3，…，７N
に格納され、テスト結果格納部６1，６2，６3，
…，６Nが初期化される。試験が開始されると、
CPU1は試験プログラム格納部５の内容を順次読
み出し、その内容に準ずる測定部２を起動し、被
試験物３を試験し、各テストのテスト結果を格納
部６1，６2，６3，…，６Nに格納する。CPU1は
格納部８の内容つまりｑを読み出し、試験個数と
ｑの大小比較を行い、試験個数がｑを越えていな
ければ、試験プログラムの内容に基ずき、全テス
トについて試験し、各テストのテスト結果つまり
各テストの歩留りを格納部６1，６2，６3，…，
６Nに格納することを繰り返す。次いで、試験個
数がｑを越えるとCPU1は各テストの前にテスト
結果と基準歩留りとを読み出し、大小比較をしテ
スト結果が基準歩留り以上であるならばテストを
省略し、つまりこのテストは良と判定し、次のテ
ストへ進む。例えば第１テストの前にテスト結果
格納部６1の内容、つまりｑ個についての第１テ
ストの歩留りと、第１テストの基準歩留り格納部
７1の内容とを読み出し、大小比較をしテスト結
果が基準歩留り以上であるならば、第１テストを
省略し第２テストへと進む。またテスト結果が基
準歩留りを下まわるならば、そのテストを試験す
るということを第Ｎテストまで行う。ここで基準
歩留り格納部７1，７2，７3，…，７Nには任意の
値を設定可能であるが、テスト結果がすべて良で
あることを条件とする場合歩留り100％に相当す
る数値を格納しておけばよい。 An embodiment of the present invention is shown in FIG. 1 is a central processing unit (hereinafter abbreviated as CPU), which controls the test equipment; 2 is a measurement section; 3 is a test object; 4 is a storage section; this includes a storage section 5 for test programs; storage units 6 1 , 6 2 , 6 3 , . . . , 6 N for the test results from the first test to the Nth test, reference yield storage units 7 1 , 7 2 , for the test results from the first test to the Nth test, respectively. 7 3 ,...,7 N , including a storage unit 8 for the number of test objects to be tested for all tests. The operation is explained as follows. When testing p test items in one lot, the first
A test program for the test object as shown in the figure is stored in the test program storage section 5, and among the p test objects,
The number q of test objects to be tested for all tests is stored in the storage unit 8, and according to the q test results,
The standard yield, which is the criterion for determining whether or not to omit a test, is stored in the storage units 7 1 , 7 2 , 7 3 , ..., 7 N for each test.
are stored in the test result storage units 6 1 , 6 2 , 6 3 ,
..., 6 N is initialized. Once the exam begins,
The CPU 1 sequentially reads the contents of the test program storage section 5, starts the measurement section 2 according to the contents, tests the test object 3, and stores the test results of each test in the storage sections 61 , 62 , 63 , ..., 6 Store in N. CPU 1 reads the contents of storage section 8, that is, q, compares the number of test pieces with q, and if the number of test pieces does not exceed q, tests all tests based on the contents of the test program, and The test results, that is, the yield of each test, are stored in the storage units 6 1 , 6 2 , 6 3 , ...,
6 Repeat storing in N. Next, when the number of test pieces exceeds q, CPU 1 reads the test result and the standard yield before each test, compares the size, and if the test result is greater than or equal to the standard yield, the test is omitted, that is, this test is passed. Then, proceed to the next test. For example, before the first test, the contents of the test result storage unit 6 1 , that is, the yield of the first test for q items, and the contents of the reference yield storage unit 7 1 of the first test are read out, compared in size, and the test results are determined. If the yield is equal to or higher than the standard yield, the first test is omitted and the process proceeds to the second test. Furthermore, if the test result is lower than the standard yield, that test is repeated up to the Nth test. Here, any value can be set for the standard yield storage parts 7 1 , 7 2 , 7 3 ,..., 7 N , but if all test results are good, the yield corresponds to 100%. All you have to do is store the numerical value.
以上説明したように、本発明によれば１ロツト
総数ｐ個中、ｑ個についてのみ全テストを実施
し、残り（ｐ−ｑ）個についてはいくつかのテス
トは省略されるわけで、１ロツトの試験時間は大
幅に短縮され、高価な試験装置の処理量を大幅に
向上させることができる。 As explained above, according to the present invention, out of the total number of p pieces in one lot, all tests are performed on only q pieces, and some tests are omitted for the remaining (p-q) pieces. test time can be significantly reduced, and the throughput of expensive test equipment can be significantly increased.
第１図は試験プログラムの流れ図、第２図は本
発明の一実施例を示すブロツク図である。
なお図において、１……中央処理装置、２……
測定部、３……被試験物、４……記憶部、５……
試験プログラムの格納部、６1，６2，６3，…，
６N……テスト結果の格納部、７1，７2，７3，
…，７N……基準歩留り格納部、８……個数格納
部、である。
FIG. 1 is a flowchart of a test program, and FIG. 2 is a block diagram showing an embodiment of the present invention. In the figure, 1... central processing unit, 2...
Measuring section, 3... Test object, 4... Storage section, 5...
Test program storage section, 6 1 , 6 2 , 6 3 ,...,
6 N ...Test result storage unit, 7 1 , 7 2 , 7 3 ,
..., 7 N ...Reference yield storage section, 8... Number storage section.
Claims (1)
半導体集積回路装置の測定を行う測定部、ならび
に記憶部を具備し、該記憶部には試験プログラム
の格納部、第１テストから第Ｎテストまでのそれ
ぞれのテスト結果の格納部、第１テストから第Ｎ
テストまでのそれぞれのテストの基準歩留り格納
部および全テストについて試験する被試験半導体
集積回路装置の個数格納部を有し、あらかじめ任
意に設定された数量については全テスト項目を試
験し、残りの数量については、前記全テスト項目
を試験した数量についての各テストのテスト結果
があらかじめ任意に設定された各テストの基準歩
留り以上であるテスト項目のみを試験しないよう
にしたことを特徴とする半導体装置の試験装置。1. Equipped with a central processing unit that controls the test equipment, a measurement section that measures the semiconductor integrated circuit device under test, and a storage section, and the storage section includes a storage section for test programs and a section for storing test programs from the first test to the Nth test. storage unit for each test result, from the first test to the Nth test
It has a standard yield storage area for each test up to the test and a storage area for the number of semiconductor integrated circuit devices to be tested for all tests. The semiconductor device is characterized in that only those test items for which the test results for the quantities tested for all the test items are equal to or higher than a reference yield for each test arbitrarily set in advance are not tested. Test equipment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57113201A JPS593371A (en) | 1982-06-30 | 1982-06-30 | Testing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57113201A JPS593371A (en) | 1982-06-30 | 1982-06-30 | Testing method of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS593371A JPS593371A (en) | 1984-01-10 |
| JPH0429988B2 true JPH0429988B2 (en) | 1992-05-20 |
Family
ID=14606111
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57113201A Granted JPS593371A (en) | 1982-06-30 | 1982-06-30 | Testing method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS593371A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000515662A (en) * | 1996-08-07 | 2000-11-21 | マイクロン、テクノロジー、インコーポレーテッド | System for optimizing test and repair times of defective integrated circuits |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59228729A (en) * | 1983-06-09 | 1984-12-22 | Toshiba Corp | Method and device for measuring semiconductor |
| JPH01197674A (en) * | 1988-02-03 | 1989-08-09 | Mitsubishi Electric Corp | Article inspecting method |
| JPH0252446A (en) * | 1988-08-17 | 1990-02-22 | Nec Kyushu Ltd | Testing apparatus for integrated circuit |
| JP2806748B2 (en) * | 1993-07-22 | 1998-09-30 | 日本電気株式会社 | Wafer inspection method |
| JPH10214870A (en) * | 1997-01-29 | 1998-08-11 | Hitachi Ltd | Method for manufacturing semiconductor device |
-
1982
- 1982-06-30 JP JP57113201A patent/JPS593371A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000515662A (en) * | 1996-08-07 | 2000-11-21 | マイクロン、テクノロジー、インコーポレーテッド | System for optimizing test and repair times of defective integrated circuits |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS593371A (en) | 1984-01-10 |
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