JPH0430235B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a reference signal generation circuit for color signal processing.The present invention relates to a reference signal generation circuit for color signal processing. It is used when converting to a predetermined frequency for purposes such as.

[Technical background of the invention]

For example, in a teletext broadcasting system using television signals, digital data such as characters and graphics are superimposed on a portion of a video signal and transmitted. On the receiver side, the digital data is sampled and stored in the image data memory, and when the data necessary for display is collected, the data is read out from the image data memory.
A process of converting it into a display signal is performed. The data read from the image data memory includes:
There is pattern data and color signal data. Color signal data is a binary signal representing the components of three primary color signals in order to express a specified color, and by modulating a color width carrier wave with this color signal data, a carrier color signal is generated. I'm trying to get it.

FIG. 1 shows a conventional color signal data demodulation system, and this system uses a phase detection circuit. In FIG. 1, 11 is a video signal input terminal, and a character signal reproduction processing circuit 12
It is connected to the. In the character signal reproducing circuit 12, the transmitted pattern data and color signal data are sampled from the video signal and stored in an image data memory, for example, processing for storing one field's worth of data is performed. The image data memory includes a pattern data memory and a color signal data memory, and the color signal data read from the color signal data memory is input to the synthesis circuit 13. Address signals for reading data are generated by counting display clock pulses that determine the accuracy of the display screen. The read color signal data is sent to the synthesis circuit 13.
, the output from the voltage controlled oscillator 18 (frequency _SC = 3.58MHz) is modulated. Therefore, from the synthesis circuit 13, a carrier color signal (3.58MHz) based on the color signal is outputted to the output terminal 14, which is as follows.
The signal is input to the color demodulation circuit of a color television receiver.

The oscillation frequency of the voltage controlled oscillator 18 is always phase-synchronized with the burst signal in the video signal sent from the transmitting side. That is, a burst signal is separated and extracted from the video signal at the input terminal 15 in the burst separation circuit 16.
The separated and extracted burst signals are applied to one input terminal of the synchronous phase detector 17. The oscillation output of the voltage controlled oscillator 18, that is, the continuous color width carrier signal (3.58 MHz) is input to the other input terminal of the synchronous phase detector 17. The synchronous phase detector 17 obtains a phase difference detection output of both input signals, which is input to a low-pass filter 19 to be smoothed. This smoothed output is then applied to the control terminal of the voltage controlled oscillator 18, whereby the oscillation output of the voltage controlled oscillator 18 becomes a burst signal (3.58MHz).
The phase will be synchronized to

Here, the specific circuit of the synchronous phase detector 17 is formed as shown in FIG. In FIG. 2, transistors Q5, Q6, Q7, Q8
constitute a differential amplifier, and a constant current source _I0 is connected between each common emitter and a reference ground potential. and,
A differential pair of transistors Q1 and Q, whose common emitters are connected to the common collectors of transistors Q5 and Q6.
2. The common collector of transistors Q7 and Q8 is a pair of transistors Q with a common emitter connected.
3, Q4, forming a multiplier. The common base of transistors Q2 and Q3 receives an opposite phase color width carrier signal ( _sc ) via an input terminal 20.
is inputted, and a positive phase color width carrier wave signal ( _sc ) is inputted to the common base of the transistors Q1 and Q4 via the input terminal 21. Next, transistor Q5,
Each base of Q8 has input terminals 23 and 22, respectively.
A positive phase carrier color signal ( _sc ) and a negative phase carrier color signal ( _ch ), which are in an antiphase relationship with each other, are inputted via the input signal. Furthermore, a keying pulse ( ) is input to the common base of the transistors Q6 and Q7 via the input terminal 24, and this pulse is at a low level during the burst period and at a high level during other periods. Note that 29 is a power supply terminal.

The above transistors Q1 to Q8 and constant current source _I0 are:
It constitutes a phase detector, and its detection output is
The signal is input from the terminal of the load resistor R ₀ to the low-pass filter 27 via the transfer get circuit 25 . A keying pulse () is inputted to the transfer gate circuit 25 from the input terminal 24 via the inverter 26, and the transfer gate circuit 25 conducts between its input and output terminals during this pulse period. In this way, phase detection is performed between the color width carrier signal and the carrier color signal (actually, a burst signal), and the smoothed output thereof is sent to the output terminal 28 of the voltage controlled oscillator 18 in FIG. It is input to the phase control section.

[Problems with background technology]

The conventional circuit described above has a problem in that jitter occurs between the burst signal and the color subcarrier when noise is mixed into the burst signal due to radio interference such as a weak electric field or ghost. Then, the control voltage for obtaining accurate transmission output may be disturbed.
As a result, especially when the color signal data sent by teletext is converted back to an analog color signal by the synthesis circuit 13 for fixed display, the color tone becomes inaccurate. Furthermore, in the above circuit, the phase-locked loop is always active, so
There is a problem in that it is impossible to adjust the oscillation center frequency of the reference oscillator.

[Purpose of the invention]

The present invention was made to address the above-mentioned circumstances, and it is possible to turn the phase-locked loop on and off depending on the display mode, and in particular, in the fixed display mode, it is possible to obtain a stable reference frequency, and further, It is an object of the present invention to provide a reference signal generation circuit for color signal processing that can adjust the center oscillation frequency of a voltage controlled oscillator in fixed display mode and improve color reproduction.

[Summary of the invention]

In this invention, the mode switching signal input terminal 33 for switching the display mode, and the first switching means 31, 3
2. Second switching means Q10, 34, 35, 36,
37 is provided to control the phase locked loop. That is, an input to which the mode switching signal (F/) is applied at the first level in the super display and transmission video signal display modes, and at the second level in the fixed display mode in which the entire screen image is obtained using data in the image data memory. a terminal 33, and when the input terminal 33 is at the first level,
A keying pulse (P) synchronized with the burst signal period is applied to the phase detection circuit section Q1 to Q8, _I0 to put this circuit section into a synchronous detection state in which phase detection processing is performed during the burst signal period, and the input terminal 33 is at the second level, the keying pulse (P) is stopped, the synchronous detection state of the phase detection circuit section is stopped, and the load resistance means
first switching means 31, 32 for making the output of _R0 constant; and when the input terminal 33 is at the first level, the keying pulse (P) is sent to the control section of the transfer gate circuit 25; In addition, this transfer gate circuit 25 introduces the phase detection output from the load resistance means R ₀ into the low-pass filter 27 only during the burst period, and the first input terminal 33 When the transfer gate circuit 25 is at the level, a certain signal is applied to the control section of the transfer gate circuit 25.
5 includes second switching means Q10, 34, 35, 36, 37 for always introducing the DC output of the load resistance means _R0 into the low-pass filter 27.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings. In Figure 3, block A surrounded by a broken line is
Since it is the same circuit as in FIG. 2, the same reference numerals as in FIG. 2 will be used for explanation. For this circuit, the keying pulse () synchronized with the burst signal period is
It is applied from an input terminal 31 via an OR circuit 32 to the common base of transistors Q6 and Q7. Further, a mode switching pulse (F/) is input to the OR circuit 32 via the input terminal 32. The mode switching pulse (F/) is at a high level in the fixed display mode and is at a low level in the superimpose mode. Furthermore, the mode switching pulse (F/) is also applied to the base of transistor Q10 via resistor 34. The emitter of this transistor Q10 is connected to the reference ground potential, and the collector is connected to the output terminal of the OR circuit 32 via resistors 35 and 36 in series. Therefore, in the fixed display mode, this transistor Q10 is turned on and the keying pulse (
Transistors Q6 and Q7 regardless of the input of
This lowers the base potential of this transistor Q
6, Q7 can be turned off. In addition, this transistor Q10 is turned off during superimposition, and the keying pulse (P) is turned off.
is allowed to influence the base potential of the transistors Q6 and Q7, and the resistors 35 and 36
The keying pulse (P) is allowed to appear at the connection. The connection between the resistors 34 and 35 is connected to the negative input terminal of the operational amplifier 37. The positive input terminal of the operational amplifier 37 is supplied with a DC voltage (VM) at a level near the middle of the level of the keying pulse (P) via the input terminal 38, and the low level keying pulse during the burst signal period. When (P) is input, a high level pulse can be output during the burst period. The output pulse of the operational amplifier 37 is input to the control terminal of the transfer gate circuit 25. When the transistor Q10 is on, the negative input terminal of the operational amplifier 37 is always at a low level, so the output is always at a high level and the transfer gate circuit 25 is always conductive. That is, in the fixed display mode, the transfer gate circuit 25 is always conductive, and the DC voltage determined by the resistor R ₀ is input to the low-pass filter 27.

Here, transistors Q1 to Q8, constant current source I ₀
This will be explained in more detail, including the phase detection function.

(1) When in super display mode.

In the super display mode, a video signal based on data from the image data memory is superimposed on a part of the video signal that is normally sent as a television signal. The images sent by character multiplexing are displayed so as to overlap with a part of the continuous images.

Since the mode switching signal (F/) at this time is at low level, the keying pulse (P)
is the transistor Q as in the circuit of Figure 2.
6 and Q7, transistors Q6 and Q7 are turned off during the burst signal period, and transistors Q5 and Q8 are turned on. In other periods, transistors Q6 and Q7 are on and transistors Q5 and Q8 are off. Further, the operational amplifier 37 outputs a pulse that makes the transfer gate circuit 25 conductive only during the burst signal period.

FIG. 4 shows signal waveforms for each part of the burst signal period for one cycle. Waveform 4 in Figure 4
A shows the voltage waveform derived from the load resistor R ₀ , waveform 4B shows the voltage waveform of the burst signal included in the carrier color signal ( _ch ), and waveform 4C shows the voltage waveform of the color subcarrier signal. During the burst signal period, the collector current of transistor Q4 flows because the base voltage of transistor Q8 is
and the base voltage of transistor Q4
This is when the base voltage of Q3 is higher than the base voltage of transistor Q3. Therefore, during the negative half period of the burst signal and the negative half period of the color subcarrier signal, the collector current flows through the transistor Q4. Further, the collector current of the transistor Q2 flows when the base voltage of the transistor Q5 is higher than the base voltage of the transistor Q8 and the base voltage of the transistor Q2 is higher than the base voltage of the transistor Q1. Therefore, the collector current flows through the transistor Q2 in the positive half period of the burst signal and in the positive half period of the color subcarrier signal. Therefore, the voltage waveform generated at the load resistor R ₀ becomes as shown by waveform 4A in FIG.

When the frequency of the color subcarrier signal ( _sc ) becomes higher than the frequency of the burst signal included in the carrier color signal ( _ch ), the collector currents of transistors Q5 and Q4 increase, the voltage at the output terminal 28 drops, and as a result, The oscillation frequency of the voltage controlled oscillator 18 is lowered. Also, when the frequency of the color subcarrier signal ( _sc ) becomes lower than the frequency of the burst signal included in the carrier color signal ( _ch ), transistors Q2 and Q4
, the collector current of the voltage controlled oscillator 18 decreases, and the voltage at the output terminal 28 increases, thereby causing the oscillation frequency of the voltage controlled oscillator 18 to increase. During periods other than the burst signal period, the keying pulse () is at a high level, and transistors Q6, Q7 are turned on, and transistors Q5, Q8 are turned off. At this time, the collector current of the transistor Q4 is in opposite phase to the collector current of the transistor Q2, and these collector currents cancel each other out and do not appear in the load resistance R ₀ . Also,
At this time, the keying pulse () is at high level, and the transistor Q is in the super display mode.
10 is off, the low-level signal inverted by the operational amplifier 37 is applied to the transfer gate circuit 25, so the input/output terminal is closed, and the output from the load resistor _R0 is in the low frequency range. It is not input to the filter 27.

It is assumed that the voltage controlled oscillator 18 has an oscillation frequency that increases when the applied control voltage increases, and an oscillation frequency that decreases when the applied control voltage decreases.

(2) When in fixed display mode.

The fixed display mode is a mode in which data sent by teletext is stored in the image data memory for one screen, and the video of the entire screen is displayed based only on the data.

Since the mode switching signal (F/) at this time is at a high level, the transistor Q10 is turned on. Furthermore, the output of the OR circuit 32 is at a high level regardless of the keying pulse ( ), transistors Q6 and Q7 are turned on, and transistors Q5 and Q7 are turned on.
Q8 is turned off.

Next, since the transistor Q10 is on, a low level signal is applied to the negative input terminal of the operational amplifier 37, and the output becomes high level. Therefore, the input and output terminals of the transfer gate circuit 25 are electrically connected. In this state, transistors Q2 and Q4 turn on and off in an antiphase relationship, so
Both collector currents cancel each other out, and a constant DC voltage is generated across the load resistance R ₀ . This DC voltage is
The signal is input to a low-pass filter 27 via a transfer gate circuit 25, and a constant DC voltage is generated at an output terminal 28. This causes the voltage controlled oscillator 18 to freely oscillate at a constant frequency. In this case, if it is desired to change the color tone of the screen in the fixed display mode, by making the resistor R ₀ variable, the oscillation frequency of the voltage controlled oscillator 18 can be adjusted and the oscillation center frequency can be set. Also, in fixed display mode, the phase lock loop is turned off, so
It is possible to obtain a stable color image without being affected by the transmitted burst signal, and the noise in the burst signal, the influence of ghost, and the color tone are not disturbed.

As described above, in the circuit of the present invention, the reference signal ( _sc ) obtained from the voltage controlled oscillator 18 can be switched between a phase synchronized state and an adjustable state depending on the display mode. That is,
In super display or normal transmission video display mode, the color components displayed on the screen are determined by the phase difference with the burst signal that is also transmitted, so the internal reference signal (3.58MHz) is It is necessary to synchronize the phase with the signal. However, when forming the entire image using data in the image data memory, such as in fixed display mode, if the internal reference signal (3.58MHz) is phase-synchronized with the transmitted burst signal, the burst signal In such cases, the phase-locked loop is turned off so that a stable reference signal can be obtained.
In such a case, if the load resistance R ₀ is made variable, the reference signal phase can be freely changed according to the user's preference, and the image can be viewed with the desired color scheme.

Furthermore, in this circuit, the output of the voltage controlled oscillator 18 is input to a clock generation circuit 39 to generate various pulses such as image data read pulses and address gate pulses. By doing so, data processing synchronized with the reference signal (3.58 MHz) can be obtained in each of the fixed display mode and super display mode, and the synchronization of the entire system is improved.

This invention is not limited to the above embodiments, but can be implemented in various forms. For example, the keying pulse () causes the phase detection circuit to
We get synchronous detection, but the keying pulse () is
The constant current source I ₀ may be turned on and off. Further, in the above embodiment, the first switching means 41 applies the keying pulse () to the phase detection circuit section depending on the display mode or stops the application, and the transfer means 41 applies the keying pulse () to the phase detection circuit section depending on the display mode. Although the second switching means 42 that turns the gate circuit 25 on and off or always on is shown in the simplest form, the first and second switching means 41 and 42 are each configured independently. It's okay. Further, although only one resistor is shown as the load resistor R ₀ , a constant current source circuit, a current mirror circuit, etc. may be added.

〔Effect of the invention〕

As described above, the present invention can turn on and off the reference signal synchronization loop for color signal processing according to the display mode, and can obtain a stable reference signal frequency adapted to each mode. In this case, it is possible to provide a reference signal generation circuit for color signal processing that can contribute to improving image quality by adjusting the center frequency of the reference signal.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a color signal data processing system, FIG. 2 is a circuit diagram showing a conventional phase synchronization circuit, FIG. 3 is a circuit diagram showing an embodiment of the present invention, and FIG. FIG. 3 is a diagram of voltage waveforms at various parts of the circuit shown in the figure. Q1 to Q8...Transistor, _I0 ...Constant current source, _R0
...Load resistance, 18...Voltage controlled oscillator, 25...Transfer gate circuit, 27...Low pass filter, 3
3...Mode switching signal input terminal, 41...First switching means, 42...Second switching means.

Claims (1)

[Claims] 1. A carrier color signal is input to the first input terminal,
A phase detection circuit section into which a color width carrier signal is inputted to the input terminal of the phase detection circuit section, a load resistance means for deriving the detection output connected between the detection output terminal of this phase detection circuit section and a power supply, and this load resistance means. a transfer gate circuit for guiding the output of the low-pass filter to a low-pass filter; an output terminal of the low-pass filter is connected to a frequency control terminal, the oscillation frequency and phase are controlled by the output of the low-pass filter, and the oscillation a voltage controlled oscillator for applying the output as the width carrier wave signal to the second input terminal of the phase detection circuit section; an input terminal to which a second level mode switching signal is applied when in a fixed display mode for obtaining an entire image; and when the input terminal is at the first level, a keying pulse synchronized with the burst signal period is applied to the phase detection circuit section; In addition, the circuit section is brought into a synchronous detection state in which phase detection processing is performed during the burst signal period, and when the input terminal is at the second level,
a first switching means for stopping the keying pulse and stopping the synchronous detection state of the phase detection circuit unit so that the output of the load resistance means becomes constant; and the input terminal is at the first level. When the keying pulse is applied to the control section of the transfer gate circuit, the transfer gate circuit introduces the phase detection output from the load resistance means to the low-pass filter only during the burst period, and When the input terminal of No. 1 is at the second level, a constant signal is applied to the control section of the transfer gate circuit, so that the transfer gate circuit always introduces the DC output of the load resistor means to the low-pass filter. 1. A reference signal generation circuit for color signal processing, characterized in that the circuit comprises a second switching means for controlling the color signal.