JPH0430464A - Semiconductor device and manufacture thereof - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] This invention relates to the structure of a capacitor of a storage cell of a DRAM (dynamic random access memory) and its manufacturing method.

The object of the present invention is to provide a capacitor structure that does not deform the storage electrode, does not significantly increase the number of manufacturing steps (and has a shape that is easy to clean), and a method for manufacturing the same.

1) Consisting of a selection transistor formed on a semiconductor substrate (11), a storage electrode (16) formed on the source/drain region of the transistor, a dielectric film (17), and a counter electrode (18) DRA consisting of a capacitor
The storage electrode (16) has a hollow cylindrical shape with both ends open, and the dielectric film (17) and the counter electrode are in contact with the inner and outer surfaces of the cylinder of the storage electrode (16). (18) is formed. 2) Semiconductor substrate (11
), and a process of forming a selection transistor of a DRAM cell on a first insulating film (21) and a second insulating film (22) in order on the first insulating film (21) and a second insulating film (22); a step of forming an opening (SC) penetrating the insulating film (22) and reaching the source/drain region of the selection transistor; and a step of forming a first conductive film (164) covering the opening (SC); A step of selectively forming a third insulating film (23) on the first conductive film (16A) in a rectangular pattern covering the opening (SC), and a second conductive film covering the third insulating film (23). A step of forming a film (16B), a step of forming an etching mask (24) with a rectangular pattern protruding from both sides of the strip pattern in the width direction, and the etching mask (24).
The second conductive film (16B) and the third insulating film (2
3) and the step of etching away the first conductive film (16A), and removing the second insulating film (22) and the first insulating film (21) without substantially etching the first insulating film (21) after all the steps are completed. 3 and a step of removing the insulating film (23).

[Industrial application field]

The present invention relates to the structure and manufacturing method of a capacitor for a DRAM memory cell.

As the storage capacity of DRAM memory cells increases, storage electrode structures are required that have a small cell area per focal point and a large capacity that can store sufficient charge for memory retention and subsequent storage.

The present invention can be used as a capacitor structure for a memory cell that meets this requirement.

[Conventional technology]

In order to reduce the cell area and increase the capacitance of the capacitor, it is important to increase the surface area of the storage electrode. For this purpose, capacitors are
A dimensional structure is effective, and the fin structure shown in Fig. 3 is known as a typical stacked structure. 1) IEDM Tech, Dig, (1988), p.
592.degree. FIG. 3 is a sectional view illustrating the structure of a conventional fin structure capacitor.

In the figure, 11 is a semiconductor substrate, 12 is an isolation oxide film 13
, 14 is a source/drain region, 15 is a word line (G), 16 is a storage electrode, 17 is a dielectric film, 18 is a common (counter) electrode, and 19 is a bit line.

As shown in the figure, the storage electrode 16 has a fin structure to increase the capacitor area.

[Problem to be solved by the invention] However, in the fin structure shown in FIG.

Since the storage electrode made of polysilicon is supported by a pillar in the center, there is a problem in that the polysilicon deforms and the back surface and the spaces between the polysilicon cannot be used sufficiently as a capacitor, as shown in Figure 4. .

Therefore, a storage electrode with a box structure as shown in Figure 5 was proposed2).
has been done. In this case, there is an advantage that deformation is less likely to occur because the upper layer polysilicon is supported by the periphery.

2) Extended Abstracts of
the conference 5solid 5t
ateDevices and Materials
+Tokyo, 1989. pp141-144. ) However, this structure has the problem of significantly increasing the number of manufacturing steps and increasing the defect rate because it is difficult to wash out foreign substances that have entered the inside of the box.

An object of the present invention is to provide a capacitor structure that is easy to clean without deforming the storage electrode, without significantly increasing the number of manufacturing steps, and a method for manufacturing the same.

[Means to solve the problem] What is the solution to the above problem?

(2) A selection transistor formed on a semiconductor substrate (11), a storage electrode (16) formed on the source/drain region of the transistor, and a dielectric film (17).

The storage electrode (16) has a hollow cylindrical shape with both ends open, and the inside and outside surfaces of the storage electrode (16) are The dielectric film (17) and the counter electrode (1) are in contact with each other in order.
8) is formed, or 2) a selection transistor of a DRAM cell is formed on a semiconductor substrate (11), and a first insulating film (21) and a second insulating film (2) are formed thereon in order.
2) and the first insulating film (21).
and a step of forming an opening (SC) penetrating the second insulating film (22) and reaching the source/drain region of the selection transistor, and a step of forming a first conductive film (16A) covering the opening (SC). and the opening (
a step of selectively forming a third insulating film (23) in a strip pattern covering the third insulating film (23); a step of forming a second conductive film (16B) covering the third insulating film (23); and a step of forming a second conductive film (16B) on the strip pattern. forming an etching mask (24) with a rectangular pattern protruding from both sides in the width direction; and using the etching mask (24), the second conductive film (16B) and the third
A step of etching away the insulating film (23) and the first conductive film (16A), and a step of removing the first insulating film (23) after completing all the above steps.
1) without substantially etching the second insulating film (2).
2) and a step of removing the third insulating film (23).

[Effect]

FIGS. 1A to 1C are structural explanatory diagrams of the present invention.

FIG. 1fa) is a plan view, and FIG. 1(b) is a sectional view taken along line A-A.

FIG. 1 (C1 is a BB sectional view.

The storage electrode 16 is composed of a lower polysilicon film 16A as a first conductive film and an upper polysilicon film 16B as a second conductive film, and both polysilicon films are connected at two opposing sides of a substantially rectangular shape. Since the other two opposing sides of the rectangle have an open hollow structure, the structure is resistant to deformation and easy to clean.

The double-dashed line in the figure indicates the strip pattern during the manufacturing process.

Furthermore, as will be explained in the examples, the number of steps is increased by only one step compared to the conventional fin structure.

[Example] Next, the structure of the present invention shown in FIG. 1 will be explained along with the manufacturing process in the order of steps using FIG. 2.

FIG. 2 (al to (ml) are cross-sectional views explaining the example in the order of steps.

FIGS. 2(a) to 2(d) are cross sections taken along line AA in FIG. 1 (al).

In FIG. 2 ta), an isolation insulating film 12 is provided in an element isolation region of a p-type silicon (p-Si) substrate 11 as a semiconductor substrate.
A word line 15 and source/drain regions 13 and 14 of the two selection transistors are formed.

A silicon dioxide (SiO□) film 20 is grown thereon.

A contact hole BC for the bit line 19 is opened in this film.

Next, bit lines 19 are formed.

In FIG. 2(b), a first insulating film is formed on the entire surface of the substrate.
Jsu500 A no5iJ-membrane 21 and h 2nd v! ! ,
l1III and SiO□ film 22 with a thickness of 500 people Total 22
do.

In FIG. 2(C), S is formed on the source/drain region 14.
i, N, film 21 and SiO□ film 22 are all 22, and a storage contact hole SC for connecting the storage electrode is opened.

In FIG. 2 (dl), a polysilicon film 16A with a thickness of 500 nm is grown as a first conductive film over the entire surface of the substrate.

On top of that, a SiO□ film 2 with a thickness of 500 nm is formed as a third insulating film.
3 all 23.

Next, FIG. 2<Q) shows a BB cross section.

In FIG. 2 fe), the SiO□ film 23 is patterned into a strip shape covering all 23 laser contact holes SC. In the strip-shaped patterning, the elongated direction coincides with the A-A direction.

Next, FIGS. 2(f) to (i) show the A-^ cross section.

In addition, Fig. 2 (0) to (2) are respectively Fig. 2 (f) to
It is a BB cross section corresponding to +1).

In FIGS. 2(fl) and 2(J), a polysilicon film 16B having a thickness of 500 nm is grown as a second conductive film over the entire surface of the substrate.

In FIG. 2 (gl, (k)), a resist film 24 in a rectangular pattern protruding from the strip-shaped pattern of the SiO2 film 23 in the B-B direction is formed, and the polysilicon film 16B is etched using this resist film as a mask.

At this time, since the polysilicon film 168 is exposed in the area where the +5iOz film 23 has been removed, the etching is stopped to prevent this from being removed.

(11) In FIG. 2(h), the entire SiO□ film 23 is selectively etched away from the entire 23 silicon films 16A.

In FIGS. 2(1) and 2(b), the polysilicon film 16^ is subsequently removed by etching, and then the resist film 24 is removed.

In the subsequent steps, as in the method for forming the fin structure capacitor, first, all of the SiO□ film 23 is simultaneously removed using hydrofluoric acid, and the capacitor dielectric film 17. Common electrode 18
The capacitor of the example is completed by growing (see FIG. 3 and FIG. 1).

In the above process, the steps added compared to the process for conventional fin-type capacitors are the step of forming a resist film in a strip pattern and the step of removing the same resist film. Since it decreases, the difference is an increase of one process.

In this embodiment, the direction of the strip pattern is parallel to the bit line, but the present invention can be applied even if the direction of the strip pattern is parallel to the word line.

Further, as the first insulating film, SiOgNy having a composition whose etching rate with hydrofluoric acid is sufficiently lower than 5 iOz may be used.

On the other hand, as the second and third insulating film, we used 5, which has a composition whose etching rate with hydrofluoric acid is sufficiently higher than that of Si3N4.
iOJy may also be used.

Furthermore, as the first insulating film, 5iJa (upper layer)/SiO□
A laminated film may also be used.

The conductive film serving as the storage electrode is not limited to polysilicon, and silicide or high-melting point metal may be used.

In the above embodiment, the case where a capacitor is formed after forming a word line and a bit line is explained, but the present invention can also be applied when forming a capacitor after forming a word line and forming a bit line thereon. can be applied.

〔Effect of the invention〕

As described above, according to the present invention, a capacitor structure and a method for manufacturing the same can be obtained that does not deform the storage electrode, does not significantly increase the number of manufacturing steps, and has a shape that is easy to clean.

As a result, device reliability and manufacturing yields have improved.

[Brief explanation of drawings]

FIG. 1 (al to fc) is a structural explanatory diagram of the present invention. Figures 2(a) to (ml are cross-sectional views explaining the embodiment in the order of steps. Figure 3 is a cross-sectional view explaining the structure of a conventional fin structure capacitor. Figures 4 and 5 are cross-sectional views explaining the conventional example. 11 is a semiconductor substrate. 12 is an isolation oxide film. 13 and 14 are source/drain regions. 15 is a word line (gate). 16 is a storage electrode. 16A is a lower polysilicon film. 16B is the upper polysilicon film. 17 is the dielectric film. 18 is the common (counter) electrode. 19 is the bit line, and the cross-sectional view of the book, Ryoichi Tsuki's explanatory diagram (Fig. 1). (Part 1)

Claims (1)

[Claims] 1) A selection transistor formed on a semiconductor substrate (11), a storage electrode (16) formed on the source/drain region of the transistor, a dielectric film (17), and a counter electrode ( 18) and a capacitor composed of
It has an AM cell, the storage electrode (16) is hollow and has a cylindrical shape with both ends open, and the dielectric film (17) is formed to cover the inside and outside surfaces of the storage electrode (16), A semiconductor device characterized in that the counter electrode (18) is formed so as to cover the surface of the dielectric film (17). 2) A selection transistor of a DRAM cell is formed on a semiconductor substrate (11), and a first insulating film (21) and a second insulating film are formed on it in order.
A process of laminating and forming an insulating film (22), and forming an opening (SC) that penetrates the first insulating film (21) and the second insulating film (22) and reaches the source/drain region of the selection transistor. a step of forming a first conductive film (16A) covering the opening (SC); and a step of forming a third insulating film (16A) on the first conductive film (16A) in a rectangular pattern covering the opening (SC). 23), a step of forming a second conductive film (16B) covering the third insulating film (23), and an etching mask with a rectangular pattern protruding from both sides of the strip pattern in the width direction. (24), and using the etching mask (24), forming the second conductive film (24).
16B), the third insulating film (23), and the first conductive film (16B).
A): removing the second insulating film (22) and the third insulating film (23) without substantially etching the first insulating film (21) after all the steps are completed; A method for manufacturing a semiconductor device, comprising the steps of: