JPH04304683A - Optical variable delay circuit - Google Patents

Abstract

PURPOSE:To make it possible to inhibit loss to a minimum and change the amount of lag time in continuous mode by inputting light to a pnpn semiconductor in an on/of state biassed by voltage and changing on/of time by means of a change in the intensity of incident light. CONSTITUTION:A signal light input from optical fiber 3 is introduced to a semiconductor amplifier 11 where the output signal light is introduced to a pnpn semiconductor device 1. Oscillation signal voltage is supplied to the pnpn semiconductor device 1 from a pnpn semiconductor device drive circuit 21. The output light of the semiconductor device 1 is introduced to a semiconductor device 2. When light is input to the semiconductor devices 1 and 2 in a state biassed by voltage, the semiconductor devices are turned to an an-state. As the turn on time required in this case depends on the intensity of the incident light, it is possible to change the turn on time by changing the intensity of the incident light. This construction makes it possible to inhibit the loss to a minimum and change the amount of time lag in continuous mode.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical variable delay circuit for use in digital optical communication devices and digital optical information processing devices.

0002

2. Description of the Related Art Optical variable delay circuits are essential in constructing optical element circuits for optical communications and optical information processing devices. Conventionally, three methods have been used to construct this optical variable delay circuit.

[0003] The first conventional method has been to first convert an optical signal into an electrical signal, adjust the amount of delay using a variable delay device for electrical signals, and then convert it back into an optical signal.

[0004] As a second method, O.E.C.
There is a method described on page 42 of EC) '90 Lecture Proceedings. In this second method, an optical fiber is used, and the length of the fiber is adjusted so that the delay time within the fiber is equal to the amount of delay required by an optical communication device or an optical information processing device.

[0005] The third method is topical meeting on photonic switching (Topica
l meeting on photonic
switching) Collection of lecture papers, page 141, 1987
As described in 2003, a method has been used in which multiple nodes are arranged in series, each of which is a combination of an optical switch and an optical fiber delay line with a fixed amount of delay. FIG. 8 is a block diagram showing the configuration of the third conventional method, and in the figure, 81 to 8
m is an optical fiber delay line, and the delay amount is shown b
・2m-1, b・2m-2, ..., b・20. At nodes 91, 92, ..., 9m, 2×
If the two optical switches 71, 72, . . . , 7m are in a crossed state, the signal light has b・2m−1, b・
A delay of 2m-2, . Nodes 91, 92
,..., the delay amount d obtained by all 9m is:
d=am-1 b・2m-1 +...+a0 b・2
It is 0. However, am-1,...,a0 is 1
or 0, and “1” is the 2×2 optical switch 71, 72
, . . , 7m cross state and "0" correspond to the through state of the 2×2 optical switches 71, 72, . . . , 7m. A desired delay amount d was obtained by selecting a combination of 2×2 optical switches 71, 72, . . . , 7 m of through and cross.

[0006]

However, the first method has the disadvantage that the size and power consumption of the device for optical-to-electrical conversion and electric-to-optical conversion are large.

[0007] In the second method, since the length of the fiber needs to be adjusted by matching the actual fiber, a large number of man-hours are required to adjust the length of the fiber, and the amount of delay is made variable. The drawback was that it was extremely difficult.

The third method has the following disadvantages: the size of the optical fiber delay line increases, the loss in the optical delay circuit increases due to the insertion of an optical switch, and the amount of delay cannot be changed continuously. there were.

SUMMARY OF THE INVENTION An object of the present invention is to provide an optical variable delay circuit which is small in size, has low power consumption, and has low loss, and is capable of continuously changing the amount of delay.

0010

[Means for Solving the Problems] In order to solve the above problems, as shown in FIG. and a first pnpn signal light intensity adjustment device.
a synchronization signal generation circuit that supplies a synchronization signal voltage to the semiconductor;
a second pnpn semiconductor element that receives the output light of the first pnpn semiconductor element;
An optical variable delay circuit including an npn semiconductor element and a second synchronization signal generation circuit that supplies a synchronization signal voltage to a second pnpn semiconductor element in synchronization with the rise of a current flowing through the first pnpn semiconductor element. Configure.

In order to solve the above problem, as shown in FIG. 7, a synchronizing signal voltage having an arbitrary phase difference with respect to the signal light incident on the pnpn semiconductor element and the pnpn semiconductor element is supplied to the pnpn semiconductor element. An optical variable delay circuit includes a variable phase synchronization signal generation circuit.

0012

[Operation] PNP in off state biased by voltage
When light is incident on an n-semiconductor element, the element is turned on. Since the turn-on time in this case depends on the intensity of the incident light, the turn-on time can be changed by changing the intensity of the incident light.

When a bias voltage pulse and a signal light pulse are applied to a pnpn semiconductor device in an off state to turn it on, the device will be in an on state after the turn-on time has elapsed since both the voltage pulse and the light pulse have been applied. If the timing of pulse application is delayed from the timing of input of the signal light pulse, the time from the input of the signal light pulse until the element turns on can be changed by changing the timing of input of the voltage pulse. be able to.

[0014]

Embodiments Examples of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of the invention according to claims 1 and 2.

As the pnpn semiconductor elements 1 and 2, 199
1st Year IEICE Spring National Conference Proceedings C-14
I use something like the one described in 0. This element has a pnpn structure, with an anode region and a cathode region made of p-AlGaAs and n-AlGaAs, respectively, sandwiching an n-gate region made of n-AlGaAs and a p-gate region made of p-AlGaAs. It becomes. The pnpn semiconductor element turns on and moves from a high impedance state to a low impedance state, and carriers are injected into the n-gate region and confined in this region, resulting in laser oscillation. In order to shift from a high impedance state to a low impedance state, it can be done by applying a voltage higher than the switching voltage (hereinafter referred to as Vs), or by injecting light even at a voltage lower than Vs. . Below, the switching voltage when no light is incident is Vs (L-OFF), and the switching voltage when light is incident is Vs (L-ON).
It is written as Vs (L-OFF) as bias voltage to the element
When turning on the device by applying a voltage between
When turning on the device by applying a voltage pulse between F) and Vs(L-ON), the turn-on time τON is proportional to the intensity of the incident light. In order to shift from a low impedance state to a high impedance state, the applied voltage is lowered to a voltage below a voltage called a holding voltage (hereinafter referred to as VH). Also, the applied voltage is VH
The time from when the value is lowered to below until the element shifts to a high impedance state is called turn-off time τOFF. In this element, output laser light is obtained from the same surface as the surface on which the signal light is incident. Therefore, there is a need for a mounting form suitable for a reflective optical element that can obtain output light as reflected light of input signal light.

Signal light input from the optical fiber 3 is guided to the semiconductor optical amplifier 11 via a lens 15. The output signal light of the semiconductor optical amplifier 11 whose intensity is adjusted by adjusting the gain in the variable current semiconductor optical amplifier drive circuit 12 is transmitted through a lens 51, a beam splitter 50, and a lens 52.
It is guided to the pnpn semiconductor device 1 through the. A synchronizing signal voltage synchronized with the clock supplied from the clock supply circuit 22 is applied to the pnpn semiconductor element 1.
A synchronizing signal voltage is supplied from a pnpn semiconductor element drive circuit 21 that supplies the pnpn semiconductor element drive circuit 21 to the pnpn semiconductor element drive circuit 21. The output light of the pnpn semiconductor element 1 is transmitted through a lens 52, a beam splitter 50, and a lens 53.
, optical fiber 6, lens 61, beam splitter 60,
The light is guided to the pnpn semiconductor element 2 through a lens 62. p
The npn semiconductor element 2 includes a current edge detection circuit 32 that detects the rise of the current flowing through the pnpn semiconductor element 1.
A synchronizing signal voltage is supplied from a pnpn semiconductor element drive circuit 31 that supplies a synchronizing signal voltage synchronized with the pnpn semiconductor element 2 to the pnpn semiconductor element 2 . The output light of the pnpn semiconductor element 2 is
The light is guided to the optical fiber 4 through a lens 62, a beam splitter 60, and a lens 63.

Next, using the timing diagram shown in FIG.
The waveforms and timings of optical signals and voltage signals input and output to the pnpn semiconductor elements 1 and 2 will be explained. pnpn
Immediately after the start of each bit of the input signal light from the pnpn semiconductor element drive circuit 21 to the pnpn semiconductor element 1 shown in (a), Vs (L-) is applied to the pnpn semiconductor element 1 as shown in (b). Apply a voltage between Vs (L-ON) and Vs (L-ON), reduce the applied voltage to a value between Vs (L-ON) and VH before the same bit ends, and apply a voltage between Vs (L-ON) and VH on the next bit. ) and Vs(L-ON) before applying a synchronizing signal pulse that repeats each cycle of reducing the applied voltage to a value below VH.

By applying the optical signals and voltage signals shown in (a) and (b) to the pnpn semiconductor element 1, as shown in (c), if the optical input to the pnpn semiconductor element 1 is in the ON state, , that is, if signal light is input during a certain bit, Vs (L-OFF) and Vs (L-ON)
Light emission starts after τON after applying a voltage between
A pulse that stops emitting light after τOFF is obtained as the output light of the pnpn semiconductor element 1 from the reduction of the applied voltage to a value equal to or lower than VH before applying the voltage between . Here, since the turn-on time τON is proportional to the intensity of the incident light, the intensity of the input light to the pnpn semiconductor element 1 can be adjusted by adjusting the gain of the semiconductor optical amplifier 11 with the variable current semiconductor optical amplifier drive circuit 12. , pnp
The rising start time of the output optical pulse of the n semiconductor element 1 is adjusted. That is, if the input light intensity to the pnpn semiconductor element 1 is reduced by reducing the gain of the semiconductor amplifier 11, the optical pulse whose rise start time is delayed by τ will be transmitted to the pnpn semiconductor element 1, as shown in (c'). obtained as output. On the other hand, the falling start time is pn
Since it is constant regardless of the input light intensity to the pn semiconductor element 1, the light emission time of the pnpn semiconductor element 1 during one bit depends on the desired amount of delay.

Further, if the optical input to the pnpn semiconductor element 1 is in an OFF state, that is, if no signal light is input during a certain bit, an output optical pulse of the pnpn semiconductor element 1 cannot be obtained.

The synchronizing signal voltage output from the pnpn semiconductor element drive circuit 31 is also applied to the pnpn semiconductor element drive circuit 2.
It is similar to the synchronization signal voltage output from 1, and immediately after the start of each bit, Vs (L-OFF) and Vs (L-ON)
set the applied voltage to a value between Vs (L-ON) and VH before the end of the same bit, and set the applied voltage to a value between Vs (L-OFF) and Vs (L-ON) in the next bit. Each cycle consists of reducing the applied voltage to a value below VH before applying a voltage between 1 and 2. The timing of the start of this synchronizing signal voltage is synchronized with the output optical pulse of the pnpn semiconductor element 1. That is, the current edge detection circuit detects the rise of the current as the pnpn semiconductor element 1 starts emitting light, and as the pnpn semiconductor element 1 starts emitting light, Vs (L-OFF) and Vs (L-ON) are detected.
Setting to a voltage between is performed. Therefore, pn
In the bit where the pn semiconductor element 1 does not emit light, the synchronizing signal voltage is maintained at a value below VH.

The pnpn semiconductor element 2 has a pnpn semiconductor element 1 shown in (c) or (c') as an input signal light.
Output light is input, and a synchronization signal voltage output from the pnpn semiconductor element drive circuit 31 is applied as an input signal voltage.

As shown in (e), if the optical input to the pnpn semiconductor element 2 is in the ON state, that is, if the pnpn semiconductor element 1 emits light for a part of the time of a certain bit, Vs(L -OFF) and Vs (L-ON) is applied, light emission starts after τON, and in the next bit a voltage between Vs (L-OFF) and Vs (L-ON) is applied. The pulse that stops emitting light after τOFF from the previous reduction of the applied voltage to a value below VH is pnpn
It is obtained as output light of the semiconductor element 2. Here, a voltage between Vs (L-OFF) and Vs (L-ON) is applied in a certain bit, and then Vs (L-OFF) is applied to the next bit.
The width of the output signal light pulse of the pnpn semiconductor element 2 is as follows: It is always constant regardless of the width of the input signal optical pulse.

Furthermore, if the optical input to the pnpn semiconductor element 2 is in an OFF state, that is, during a certain bit, the pnpn
If the pn semiconductor element 1 is not emitting light, the output light pulse of the pnpn semiconductor element 2 cannot be obtained.

As described above, by using the pnpn semiconductor element 1 to arbitrarily vary the rise start time as an output, and by using the pnpn semiconductor element 2 to make the light emitting time in a certain bit constant, optical variable delay can be achieved. Operation as a circuit is performed.

FIG. 2 shows the second aspect of the invention according to claims 1 and 2.
It is a block diagram showing an example of. In the second example,
A variable optical attenuator 13 is used as a means for adjusting the intensity of the signal light incident on the pnpn semiconductor element 1. It is adjusted by mechanically adjusting the optical system.

FIG. 3 is a block diagram showing an embodiment of the invention according to claim 3. As the pnpn semiconductor element 7,
PNP used in the first embodiment of the invention of claim 1
The same semiconductor elements as n semiconductor elements 1 and 2 are used.

The signal light input from the optical fiber 3 passes through the lens 51, the beam splitter 50, and the lens 52, and then
It is guided to the npn semiconductor element 7. pnpn semiconductor element 7
A synchronizing signal voltage is applied from the phase-variable synchronizing signal generating circuit 40 to . The phase variable synchronization signal generation circuit 40 includes a clock supply circuit 22, a phase adjustment circuit 41, pnpn
The pnpn semiconductor element drive circuit 21 outputs a synchronizing signal voltage in synchronization with a clock generated from a clock supply circuit 22 and whose phase is adjusted by a phase adjustment circuit 41. . p
Output light from the npn semiconductor element 7 is guided to the optical fiber 4 via a lens 52, a beam splitter 50, and a lens 53.

Next, using the timing diagram shown in FIG.
The waveforms and timing of the optical signal and voltage signal output to the pnpn semiconductor element 7 will be explained. From the phase variable synchronization signal generation circuit 40 to the pnpn semiconductor element 1, (b)
As shown in FIG.
(L-OFF) and Vs(L-ON), and reduce the voltage to between Vs(L-ON) and VH.The next bit sets Vs(L-OFF) and Vs( L
- ON) before applying the voltage between VH
Apply a synchronization signal pulse, reducing it to a value less than or equal to the value, repeating each cycle.

By applying the optical signals and voltage signals shown in (a) and (b) to the pnpn semiconductor element 7, as shown in (c), if the optical input to the pnpn semiconductor element 7 is in the ON state, , that is, if signal light is input during a certain bit, Vs (L-OFF) and Vs (L-ON)
Light emission starts after τOH after applying a voltage between
A pulse that stops emitting light after τOFF is obtained as the output light of the pnpn semiconductor element 7 from the reduction of the applied voltage to a value equal to or lower than VH before applying the voltage between .

Here, the phase of the pnpn semiconductor element 7 is adjusted by adjusting the phase between the input signal light to the pnpn semiconductor element 7 and the synchronization signal voltage by the phase adjustment circuit 22 in the phase variable synchronization signal generation circuit 40. Adjust the rise start time of the output optical pulse. That is, in (b'), as the voltage applied to the pnpn semiconductor element 7, a synchronizing signal voltage whose phase is delayed by τ from that in (b) is used, so that the phase is delayed from that shown in (c') by τ. A light pulse delayed by τ is obtained as the output of the pnpn semiconductor element 7.

Here, Vs(L-OFF
) and Vs(L-ON), and before applying the voltage between Vs(L-OFF) and Vs(L-ON) in the next bit, the applied voltage is below VH. Since the time required for the reduction to the value of is always constant, the width of the output signal light pulse of the pnpn semiconductor element 7 is always constant regardless of the rise start time.

Further, while the voltage applied to the pnpn semiconductor element 7 is maintained between Vs (L-OFF) and Vs (L-ON), the optical input to the pnpn semiconductor element 7 is OFF.
state, that is, if no signal light is input,
The output optical pulse of the pnpn semiconductor element 7 cannot be obtained.

As described above, by arbitrarily varying the phase of the synchronizing signal voltage applied to the pnpn semiconductor element 7, the optical variable delay circuit operates.

As described in the above three embodiments, the optical variable delay circuit of the present invention can be used for optical/electrical converters, electrical/electrical converters, etc.
Since neither an optical conversion device nor an optical fiber delay line is required, it is possible to downsize the device and reduce power consumption. In addition, since no optical switch is used, not only is there little loss, but the power of the output light from the pnpn semiconductor element is
Since it is easy to increase the power of the input light higher than the power required to turn on the semiconductor element, the effect of amplifying the power of the signal light can be obtained at the same time. Furthermore, since it is possible to use current control, mechanical system position control, voltage signal delay amount control, etc. as means for adjusting the delay amount, it is easy to continuously adjust the delay amount.

In this embodiment, a reflective type element is used as the pnpn semiconductor element, in which the output signal light is obtained from the signal light incident surface. A transmissive pnpn semiconductor element that can obtain light may be used, and a transmissive pnpn
When using semiconductor elements, beam splitters 50, 6
0 is not required.

In this embodiment, a fiber is used for the input/output of the optical variable delay circuit, but the input/output means may be a waveguide, spatial propagation, or the like.

[0037]

[Effects of the Invention] As described above, the present invention is compact, has low power consumption, has low loss, and can continuously change the amount of delay. This makes it possible to configure an optical variable delay circuit suitable for use, which is extremely useful.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a first embodiment of the invention according to claims 1 and 2;

FIG. 2 is a block diagram showing the configuration of a second embodiment of the invention according to claims 1 and 2;

FIG. 3 is a block diagram showing the configuration of an embodiment of the invention according to claim 3.

FIG. 4 is a timing diagram showing the timing of the operation of the embodiment of the invention according to claims 1 and 2;

FIG. 5 is a timing diagram showing the timing of the operation of the embodiment of the invention as set forth in claim 3;

FIG. 6 is a block diagram showing the configuration of the invention according to claims 1 and 2.

FIG. 7 is a block diagram showing the configuration of the invention according to claim 3.

FIG. 8 is a block diagram showing the configuration of a conventional variable optical delay circuit.

[Explanation of symbols]

1, 2 pnpn semiconductor elements 3, 4, 5, 6 optical fiber 10 signal light intensity adjustment device 11 semiconductor optical amplifier 12 variable current semiconductor optical amplifier drive circuit 13
Variable wavelength optical attenuator 14 Attenuation control device 15, 51, 52, 53, 61, 62, 63 Lenses 20, 30 Synchronization signal generation circuit 21, 31 PNPN semiconductor element drive circuit 22
Clock supply circuit 32 Current edge detection circuit 40 Phase variable synchronization signal generation circuit 41 Phase adjustment circuit 50, 60 Beam splitter 71~7m 2x2 optical switch 81~8m Optical fiber delay line 91~9m Node

Claims (3)

[Claims] 1. A pnpn semiconductor element, and the pnpn
1. An optical variable delay circuit comprising: a signal light intensity adjustment device that adjusts the intensity of signal light incident on a semiconductor element; and a synchronization signal generation circuit that supplies a synchronization signal voltage to the PNPN semiconductor element. 2. The optical variable delay circuit according to claim 1, further comprising: a second pnpn semiconductor element that receives the output light of the first pnpn semiconductor element according to claim 1;
a second device that supplies a synchronizing signal voltage to the second pnpn semiconductor device in synchronization with the rise of the current flowing through the n-semiconductor device;
An optical variable delay circuit comprising: a synchronization signal generation circuit; 3. A pnpn semiconductor element, and the pnpn
1. A variable optical delay circuit comprising: a variable phase synchronization signal generating circuit that supplies a synchronization signal voltage having an arbitrary phase difference with respect to signal light incident on a semiconductor to the pnpn semiconductor element.