JPH0430666A - Smoothing system for area data - Google Patents

Abstract

PURPOSE:To obtain an area data with high picture quality in which no jaggy is remarkable by processing an area data in an area data in an area memory into block at a prescribed size, extracting the pattern of the surrounding area data and supplementing the area with high resolution with the extracted pattern. CONSTITUTION:A block processing means comparing a line buffer 3 and a 3X3 block processing circuit 4 is provided to process the area data of an area memory 2 in a prescribed size and pattern matching is implemented by using the area data processed into blocks by a pattern matching circuit 5 comprising an LUT and the data is outputted while being supplemented by an area data with high resolution. The pattern matching circuit 5 converting the area data with high resolution uses horizontal/vertical area data to apply the pattern matching.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image data smoothing method for outputting data in a region memory edited at low resolution at high resolution.

[Conventional technology]

Digital image processing apparatuses are superior to analog image processing apparatuses in that they can convert halftone image data into multivalued data, store it in memory, and process it easily and freely.

For example, in a digital color copying machine, it is possible to add color (coloring) or to add color to the image data of a document read for each area. In order to perform such editing processing, area memory is prepared. When attempting to perform desired editing processing on image data read from a document, first set an editing command as area data in this area memory, and then extract the area of the image data when processing the image data. The area data is read out and sent to the editing circuit in synchronization with the image data.

The present applicant has already developed a method in which an area memory (brain memory) is prepared in a digital color image processing device such as a digital color copying machine, and editing commands are set as area data to edit and output image data. A proposal has been made (for example, Japanese Patent Application No. 1-44174). When setting area data in the area memory, for example, specify an editing command in advance or specify the editing area with a marker, bliscan the original, and then recognize the marker color from the image data read from the original. The extracted area is extracted and a 4-bit editing command is written as area data into an area memory consisting of four brains.

[Problem to be solved by the invention]

As described above, the area memory sets area data for each area of the document, so basically a memory capacity equal to the size of the document is required. However, in image processing devices such as digital color copying machines, practical machines have a resolution of 16 dots/mm (one pixel is 62.5
If you use area memory at this resolution, the memory capacity will be enormous, so the resolution is 4 dots/m.
It uses area memory with a resolution lowered to m. Therefore, when area editing is performed, area data processed at a resolution of 4 dots/mm is output as is as an image at a resolution of 16 dots/mm, resulting in image quality deterioration. In particular, a problem arises in that jagged edges appear in diagonal directions, making so-called jaggies noticeable.

The present invention is intended to solve the above-mentioned problems, and its purpose is to obtain high-quality region data in which jaggies are not noticeable even when editing processing is performed using a low-resolution region memory. Another object of the present invention is to obtain high resolution region data by complementing low resolution region data.

[Means to solve the problem]

To this end, the present invention provides a smoothing method for area data that reads out area data from an area memory that has been edited and stored at low resolution and outputs it at high resolution.As shown in FIG. A blocking means consisting of 4 is set up to block the area data in the area memory 2 to a predetermined size, and pattern matching is performed on the blocked area data by a pattern matching circuit 5 composed of an LUT to create a high-resolution area. It is characterized by being configured to complement and output data. Furthermore, the pattern matching circuit 5 for converting high-resolution area data is characterized in that it is configured to perform pattern matching using upper, lower, left, and right area data.

[Effect]

In the area data smoothing method of the present invention, the area data in the area memory 2 is divided into blocks of a predetermined size, so it is possible to extract a pattern of surrounding area data and complement high-resolution area data with that pattern. . In this case, using the upper, lower, left, and right area data, complement the high-resolution area data so that the diagonal half of the attention area data is the same area data for the same pattern, such as one of the top and bottom and one of the left and right data. This allows you to improve the image quality of noticeable jaggies in the diagonal direction.

〔Example〕

Examples will be described below with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of a region data smoothing method according to the present invention, and FIG. 2 is a diagram showing an example of a complementary method using pattern matching.

In FIG. 1, a region extracting circuit 1 extracts a region of input data in order to make the region memory 2 correspond to the input data. That is, the resolution of the area memory is 4
dots/mm, and if the resolution of the input data is 16 dots/mm, each line of input data corresponds to 4 pixels, and the number of lines corresponds to an area of 4 lines or 1 area data of area memory. Therefore, the region extraction circuit 1 performs this resolution conversion to extract the region, and controls reading of region data from the region memory 2.

The line buffer 3 delays the area data read from the area memory 2 by one line each to prepare three lines of area data, and the 3×3 blocking circuit 4 reads out the area data from the area memory 2. Three lines of area data consisting of the area data from the previous line, the area data from one line before delayed by the line buffer 3, and the area data from two lines before are sequentially taken in to form 3×3 blocks.

The pattern matching circuit (LUT) 5 sets the center of the data of the 3×3 blocking circuit 4 as attention area data as shown in FIG.
~A is the target data for pattern matching, and corresponding to each pattern, a 4×4 high-resolution image as shown in Figure 2(b) and (C1) is created using the LUT (look-up table) method. Area data a0°~a63
, . . . read out a3° to a33.

For example, 80 in a 3x3 block, A1 or "0", A2,
The example of the pattern A3 or "1" is shown in (b) of the same figure, and the complementation of the attention area data in this case is A,
, the half of the side (closer to the lower right corner) is set to "1".

In addition, as shown in the same figure (C), upper, lower, left and right area data A
If the three values 0 to A3 are the same, the attention area data is complemented so that all pixels have the same value. It should be noted that the high-resolution area data shown in Figure (b) is configured to complement the lower side of the diagonal line upward to the right, or may also be configured to complement the pixels on the diagonal line. Of course. Furthermore, although the high-resolution area data shown in FIG. 1 (C1) is configured so that all pixels have the same value, it may also be configured to leave some portions by weighting the upper, lower, left, and right area data.

The 4X4 data matching circuit 6 receives the high-resolution area data a0° to a02 read out from the pattern matching circuit 5.
, . . . latches a3° to a3S. The ping-pong line buffer 7 has two sets of memories for 4 lines of high-resolution area data corresponding to one line of the area memory 2, while the 4×4 data synchronization circuit 6
The latched area data is written in one area, and during that time, it is read out from the other side and sent to the editing circuit 8. Then, this writing and reading are alternately switched.

FIG. 3 is a diagram for explaining the writing process of high-resolution area data, and FIG. 4 is a diagram showing an example of the configuration of a ping-pong line buffer.

FIG. 2 fbl read out by the pattern matching circuit 5
FIG. 3 shows an example of writing area data into the line buffer. Writing to the line buffer is performed by latch data 1 of the 4×4 data latch circuit 6 shown in FIG.
If there is one, the area data aOS, a13, a! is first stored in the line buffer 12 for four lines. One column consisting of ff5a33 is written, followed by a. 2, each column of a (N, and finally the column of a. The line buffer 12 becomes full when four lines of area data supplemented by pattern matching are written.The area data of line buffer [2] that has become full in this way is synchronized with the input data. The data is read out one line at a time and sent to the editing circuit 8 through the selector 13.

When the transmission of four lines of area data is completed, the input data either continues to the next line or, in the configuration shown in FIG. 3, the area data corresponding to the input data cannot be prepared immediately. Therefore, as shown in FIG. 4, two sets of line buffers 2
A ping-pong line buffer configuration with 2A and 22B is required.

In the configuration of the ping pong line buffer shown in FIG. It is possible to set the buffer 22B to write mode, read out the area data of the next line from the area memory 2, perform complementation processing by the pattern matching circuit 5, and write it into the line buffer 22B.

Therefore, by the time reading from the line buffer 22A is completed, writing to the line pants 722B is completed,
Immediately from line buffer 22A to line buffer 22B
By switching the read mode, the area data corresponding to the next line of input data can be read out from the line buffer 22B and sent out. Line buffer 2 at the same time
Needless to say, 2A becomes the write mode, and further moves to write processing of area data of the next line. Selectors 21 and 24 are used to switch the mode, and a line sync 4 frequency divider circuit 25 is used to generate the switching signal.

FIG. 5 is a diagram showing an example of the configuration of an LUT used in a pattern matching circuit.

In the above-described pattern matching, as shown in FIG. 5, area data A0 to A of 4 bits on the top, bottom, left and right sides are used as addresses to form area data a consisting of 4X4=16 bits. .

~a03, . . . aso-a23 is read.

Note that the present invention is not limited to the above-mentioned embodiments, and various modifications are possible. For example, in the above embodiment, pattern matching was performed using the upper, lower, left, and right region data of a 3×3 block, or pattern matching could be performed using diagonal region data as well. may be made larger. Moreover, although the example shown here complements binary area data, it may also be designed to complement multi-value area data.

[Effects of the Invention] As is clear from the above description, according to the present invention, even if editing commands for each area are set in a low-resolution area memory, the editing commands for each area can be edited pixel by pixel according to the resolution to be output from the surrounding pattern. , it is possible to generate high-quality area data with inconspicuous jaggies even on diagonal lines and curves. Furthermore, since the complementary processing is performed by pattern matching, the circuit can be simplified and the processing speed can be improved.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of a smoothing method for area data according to the present invention, FIG. 2 is a diagram showing an example of a complementary method using pattern matching, and FIG. 3 is a diagram showing an example of a complementary method using pattern matching. FIG. 4 is a diagram showing an example of the configuration of a ping-pong line buffer, and FIG. 5 is a diagram showing an example of the configuration of an LUT used in a pattern matching circuit. ■...Area extraction circuit, 2...Area memory, 3...
Line buffer, 4...3x3 blocking circuit, 5.
...Pattern matching circuit, 6.4x4 data latch circuit, A. Ping-pong line buffer, 8.Editing circuit. Applicant Fuji Xerox Co., Ltd.

Claims (2)

[Claims] (1) A smoothing method for area data that reads out area data in an area memory that has been edited and stored at low resolution and outputs it at high resolution, and includes means for dividing area data in the area memory into blocks of a predetermined size, and blocking. The area data is characterized in that the area data is provided with means for performing pattern matching on the imaged area data and converting it into high-resolution area data, and is configured to complement and output the high-resolution area data with a pattern of area data of a block. smoothing method. (2) The area data smoothing method according to claim 1, wherein the means for converting the high-resolution area data is configured to perform pattern matching using upper, lower, left, and right area data.