JPH0430747U - - Google Patents
Info
- Publication number
- JPH0430747U JPH0430747U JP7221290U JP7221290U JPH0430747U JP H0430747 U JPH0430747 U JP H0430747U JP 7221290 U JP7221290 U JP 7221290U JP 7221290 U JP7221290 U JP 7221290U JP H0430747 U JPH0430747 U JP H0430747U
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- gate oxide
- semiconductor device
- drain region
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
第１図は本考案の半導体装置の一実施例を示す
断面説明図、第２図ａ，ｂ，ｃ，ｄ，ｅは第１図
に示す実施例の半導体装置を製造する工程を示す
断面説明図、第３図は従来の半導体装置を示す断
面説明図である。
１……ソース領域、２……ゲート領域、３……
ドレイン領域、４……ゲート酸化膜、５……シリ
コン基板（Ｐ−シリコン）、６……ゲート電極材
料、７……レジストパターン、８……Ｎ型不純物
イオン、９……層間絶縁膜、１０……メタル配線
、１１……シリコン酸化膜、１２……レジストパ
ターン、ｅ……電子（ホツトエレクトロン）。
FIG. 1 is a cross-sectional explanatory diagram showing one embodiment of the semiconductor device of the present invention, and FIGS. 2 a, b, c, d, and e are cross-sectional explanatory diagrams showing the steps of manufacturing the semiconductor device of the embodiment shown in FIG. 3 are cross-sectional explanatory views showing a conventional semiconductor device. 1... Source region, 2... Gate region, 3...
Drain region, 4... Gate oxide film, 5... Silicon substrate (P - silicon), 6... Gate electrode material, 7... Resist pattern, 8... N-type impurity ion, 9... Interlayer insulating film, 10 ...Metal wiring, 11...Silicon oxide film, 12...Resist pattern, e...Electron (hot electron).
Claims (1)
にわたつて形成されているゲート酸化膜を備えた
半導体装置において、チヤネル中央部におけるゲ
ート酸化膜の膜厚よりドレイン領域側におけるゲ
ート酸化膜の膜厚の方が厚いことを特徴とする半
導体装置。 (2) ソース領域とゲート領域とドレイン領域と
にわたつて形成されているゲート酸化膜を備えた
半導体装置において、上記ゲート酸化膜はチヤネ
ル中央部においてはシリコン結晶面の＜１００＞
面の酸化膜から形成され、ドレイン領域側におい
てはシリコン結晶面の＜１１１＞面の酸化膜から
形成され、チヤネル中央部におけるゲート酸化膜
の膜厚よりドレイン領域側におけるゲート酸化膜
の膜厚の方が厚いことを特徴とする半導体装置。[Claims for Utility Model Registration] (1) In a semiconductor device equipped with a gate oxide film formed across a source region, a gate region, and a drain region, the drain region A semiconductor device characterized in that a gate oxide film is thicker on the side. (2) In a semiconductor device equipped with a gate oxide film formed across a source region, a gate region, and a drain region, the gate oxide film is formed in the <100> direction of the silicon crystal plane in the center of the channel.
On the drain region side, it is formed from an oxide film on the <111> plane of the silicon crystal plane, and the gate oxide film on the drain region side is thicker than the gate oxide film on the channel center. A semiconductor device characterized by being thicker.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7221290U JPH0430747U (en) | 1990-07-06 | 1990-07-06 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7221290U JPH0430747U (en) | 1990-07-06 | 1990-07-06 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0430747U true JPH0430747U (en) | 1992-03-12 |
Family
ID=31609953
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7221290U Pending JPH0430747U (en) | 1990-07-06 | 1990-07-06 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0430747U (en) |
-
1990
- 1990-07-06 JP JP7221290U patent/JPH0430747U/ja active Pending
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