JPH0430764B2 - - Google Patents

Description

[Detailed description of the invention] [Technical field to which the invention pertains] The present invention relates to an integrated circuit including a digital circuit configured using CMOS transistors, and particularly to a circuit that can quickly perform a circuit test of this digital circuit. Concerning embedded integrated circuits.

[Prior art]

Generally, CMOS transistors are said to have significantly inferior frequency characteristics compared to bibolar transistors, which are compared with CMOS transistors. usually,
The frequency characteristics of CMOS transistors are often several MHz or less.

However, although this speed is sufficient for many practical applications, at the stage of manufacturing and testing it, the time required for the test is long and the test cost is high because the test is repeated for various cases in which it will be used in practice. However, there were problems in that the test processing capacity deteriorated, making it difficult to supply in large quantities unless extensive testing equipment was installed. This will be explained using one circuit as an example.

FIG. 1 is a circuit diagram of an example of a conventional key matrix circuit.

In Figure 1, inverters 1 to 4 are CMOS
Constructed using transistors. Inverter 1
4 constitutes an IC output circuit 50, and serves as a key scan inverter that scans the key switches 5 to 20. For example, when key switches 5 to 8 are pressed multiple times (multiple switches are turned on at the same time), the outputs of inverters 1 to 4 are short-circuited. Inverter 21~
24 is also composed of a CMOS transistor and serves as a key input inverter. 25 to 28 are resistors, 29 is a timing generator, and 30 is a key decoder.

As mentioned above, inverters 1 to 4 are P channel
MOS transistor (hereinafter referred to as PMOS transistor) and N-channel MOS transistor (hereinafter referred to as PMOS transistor)
It consists of a CMOS inverter (referred to as NMOS transistor). Now, let Gm of PMOS transistor and NMOS transistor be g _nP and g _nN respectively.
In this case, g _nP /g _nN is set to about several hundred, and the outputs of inverters 1 to 4 are set to the "H" level even when multiple presses are pressed.
g _n of NMOS and PMOS transistors
This difference is due to the way the transistors are made, and means that the fall time t _f of the outputs of the inverters 1 to 4 is much longer than the rise time t _r .

In the normal operation of integrated circuits, it is necessary to set the above G _/N ratio, but when checking the operation of integrated circuits, that is, during testing, there are many test items that assume all possible cases, so the test time cannot be ignored. give rise to defects. In particular, when producing in large quantities, the throughput per hour of the tester decreases significantly depending on the length of test time per unit, and in order to produce in large quantities, it is necessary to equip many testers. This method has the disadvantage that it requires a large amount of installation cost and space, and also requires a long testing time, leading to an increase in costs.

[Purpose of the invention]

An object of the present invention is to eliminate the above-mentioned drawbacks and to provide an integrated circuit that can reduce test time and cost by adding a circuit that increases the g _n of the output transistor only during testing. be.

[Structure of the invention]

The integrated circuit of the present invention has P and N channels.
In an integrated circuit having an internal circuit including complementary MOS transistors consisting of MOS transistors and a CMOS output circuit, the CMOS
The source and drain of another P or N channel MOS transistor having the same polarity as that of the MOS transistor are commonly connected to one or both of the P and N channel MOS transistors constituting the output circuit, and An output end of a phase inversion circuit is connected to the gate of the transistor, an AND NOT circuit is connected to the input end of the phase inversion circuit, and one input end of the AND NOT circuit is connected to an input end of the CMOS output circuit. However, it is constructed by connecting a test mode signal line to the other input terminal of the AND NOT circuit.

[Explanation of Examples]

Next, embodiments of the present invention will be described using the drawings.

Figure 2 is a circuit diagram of the first embodiment of the present invention;
The figure is a detailed circuit diagram of the inverter shown in FIG. 2.

An example of a key matrix driving circuit will be described in the same manner as the conventional example shown in FIG.

This embodiment uses a CMOS output circuit in an integrated circuit having an internal circuit including complementary MOS transistors consisting of P and N channel MOS transistors Q _P and Q _N , and CMOS output circuits 50-1 to 50-4. P and N channel MOS transistors Q _P configuring circuits 50-1 to 50-4,
Q _N or both
Another P or N channel MOS transistor 41 with the same polarity as the MOS transistor
44 sources and drains are connected in common,
The output terminals of inverters 37 to 40 as phase inversion circuits are connected to the gates of other MOS transistors 41 to 44, and the AND NOT circuits 31 to 34 are connected to the input terminals of the inverters. CMOS output circuit 50-1 to 5
0-4, and the test mode signal line SG _TM is connected to the other input terminal.

To explain in more detail, the present invention focuses on the fact that only the transistors of inverters 1 to 4 of the CMOS output circuit 50 have their fall times t _f lengthened due to load fluctuations, etc., and the g _n of the output transistors is increased only during testing. The idea was to increase the number of That is, under normal conditions, the fall time t _f of the output transistor becomes significantly long. In the test state, the g _n of the output transistor is increased to shorten the fall time, and the test can be performed even when a fast test signal is applied, thereby shortening the test time.

Next, the operation of this embodiment will be explained. Since the four output circuits 50-1 to 50-4 have the same shape, only the output circuit 50-1 will be described.

The drain of the NMOS transistor 41 is commonly connected to the output terminal of the inverter 1, and the source and substrate are connected to a reference potential Vss, which is a ground potential. As a result, the NMOS transistor Q _N , which is one of the output transistors of the inverter 1, and the NMOS transistor 41 are connected in parallel. The inverter 32 and the AND NOT circuit 31 are connected as described above.

In test state, test mode signal SG _TM is set to “H”
level, and when a “H” level or “L” level signal is applied to the input of inverter 1, the NMOS
This means that an input of the same level as that of inverter 1 is applied to the gate of transistor 41. In this state, the output transistor _QN of inverter 1
Assuming g _nN1 and g _n41 of NMOS transistor 41,
The total g _nN is expressed as g _nN ≡g _nN1 + g _nN41 . That is, the total g _nN increases. This allows the fall time t _f to be short-circuited.

In the normal operating state, the AND NOT circuit 31
If the test mode signal SG _TM applied to is set to the "L" level, the NMOS transistor 33 is turned off, and the above-mentioned relationship of g _nP /g _nN several hundred is maintained. That is, there is no effect on the normal operation of the original integrated circuit.

FIG. 4 is a circuit diagram of a main part of a second embodiment of the present invention.

This embodiment has an AND NOT circuit 35 in the output circuit.
In this case, a 3-input AND NOT circuit 36 is used and wired as shown. In this way, a circuit that operates similarly to the first embodiment can be obtained.

〔Effect of the invention〕

As explained in detail above, according to the present invention,
Connect transistors of the same polarity in parallel to the P or N channel MOS transistors of the output circuit including CMOS type transistors, and operate them in parallel only during testing to increase the g _n of the output circuit and shorten the fall time. An integrated circuit with reduced test time is obtained. Therefore, there is no need to add an expensive tester, and the cost can be reduced.

[Brief explanation of drawings]

Figure 1 is a circuit diagram of an example of a conventional key matrix circuit, Figure 2 is a circuit diagram of a first embodiment of the present invention, and Figure 3 is a detailed circuit diagram of the inverter shown in Figures 1 and 2. , FIG. 4 is a circuit diagram of a second embodiment of the present invention. 1-4...Inverter, 5-20...Key switch, 21-24...Inverter, 25-28...
...Resistor, 29...Timing generator, 30
...Key decoder, 31-35...AND NOT circuit, 36...AND AND NOT circuit, 37-40...Inverter, 41-44...N channel transistor, 50, 50-1 to 50-4... output circuit,
SG _TM ...Test mode signal, Vss...Reference potential.

Claims (1)

[Claims] 1 The driving capacity of the P-channel and N-channel output MOS transistors constituting the CMOS output circuit is determined based on the external load condition connected to the output terminal of the CMOS output circuit and driven by the CMOS output circuit. An integrated circuit configured such that at least one of the rise time and fall time of the drive signal is longer, the integrated circuit being parallel to at least the output MOS transistor that lengthens the rise time or fall time of the drive signal. further, receives a control signal specifying normal operation or test operation, and when the control signal specifies the normal operation, causes the additional MOS transistor to be held in a non-conducting state; When specifying an operation, a control means is provided to make the additional MOS transistor conductive or non-conductive according to an input signal to the CMOS output circuit, and the rise time and fall time of the signal from the CMOS output circuit are controlled during the test operation. An integrated circuit characterized by its short time.