JPH04307937A - Manufacture of semiconductor element - Google Patents
Manufacture of semiconductor elementInfo
- Publication number
- JPH04307937A JPH04307937A JP7323091A JP7323091A JPH04307937A JP H04307937 A JPH04307937 A JP H04307937A JP 7323091 A JP7323091 A JP 7323091A JP 7323091 A JP7323091 A JP 7323091A JP H04307937 A JPH04307937 A JP H04307937A
- Authority
- JP
- Japan
- Prior art keywords
- polyimide resin
- wafer
- heat treatment
- etching
- curing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 title claims description 4
- 229920001721 polyimide Polymers 0.000 claims abstract description 25
- 239000009719 polyimide resin Substances 0.000 claims abstract description 21
- 239000000126 substance Substances 0.000 claims abstract description 12
- 238000005530 etching Methods 0.000 claims abstract description 10
- 238000010438 heat treatment Methods 0.000 claims abstract description 6
- 239000004642 Polyimide Substances 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 17
- 238000000137 annealing Methods 0.000 abstract description 6
- 238000004380 ashing Methods 0.000 abstract description 6
- OAKJQQAXSVQMHS-UHFFFAOYSA-N hydrazine group Chemical group NN OAKJQQAXSVQMHS-UHFFFAOYSA-N 0.000 abstract description 5
- 230000001681 protective effect Effects 0.000 abstract description 5
- 238000001039 wet etching Methods 0.000 abstract description 4
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 abstract description 3
- 229910001882 dioxygen Inorganic materials 0.000 abstract description 3
- 125000000962 organic group Chemical group 0.000 abstract 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 11
- 235000012431 wafers Nutrition 0.000 description 9
- 239000012535 impurity Substances 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 239000011368 organic material Substances 0.000 description 4
- 239000011347 resin Substances 0.000 description 4
- 229920005989 resin Polymers 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- ZSLUVFAKFWKJRC-IGMARMGPSA-N 232Th Chemical compound [232Th] ZSLUVFAKFWKJRC-IGMARMGPSA-N 0.000 description 2
- 229910052776 Thorium Inorganic materials 0.000 description 2
- 229910052770 Uranium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000011261 inert gas Substances 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000004033 plastic Substances 0.000 description 2
- 238000004382 potting Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- JFALSRSLKYAFGM-UHFFFAOYSA-N uranium(0) Chemical compound [U] JFALSRSLKYAFGM-UHFFFAOYSA-N 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 230000002285 radioactive effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
Landscapes
- Formation Of Insulating Films (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【0001】0001
【産業上の利用分野】この発明は半導体素子の保護膜、
特に熱や湿度あるいはα線の入射による集積回路の誤動
作を防ぐ表面保護膜に関するものである。[Industrial Field of Application] This invention relates to a protective film for semiconductor elements,
In particular, it relates to a surface protective film that prevents malfunctions of integrated circuits due to heat, humidity, or incidence of alpha rays.
【0002】0002
【従来の技術】一般に半導体素子は、セラミックパッケ
ージ若しくはプラスチックパッケージに封止される。こ
れらの材料には数ppm 程度のウラニウムやトリウム
などの放射性の不純物が含まれている。2. Description of the Related Art Semiconductor devices are generally sealed in ceramic packages or plastic packages. These materials contain several ppm of radioactive impurities such as uranium and thorium.
【0003】これらの不純物から放射されるα線は、メ
モリ素子例えばDRAM(ダイナミック・ランダム・ア
クセス・メモリー)などの蓄積電荷データを反転させ誤
動作(一般にソフトエラーと呼称される)を生ずること
が知られている。このため素子の信頼性が著しく低下さ
れることがある。It is known that alpha rays emitted from these impurities can invert stored charge data in memory devices such as DRAMs (dynamic random access memories), causing malfunctions (generally referred to as soft errors). It is being For this reason, the reliability of the device may be significantly reduced.
【0004】このソフトエラーを低減するためにはセラ
ミックパッケージやプラスチックパッケージの純度の高
い材料(低ウラニウム、低トリウム)を使用すれば良い
がコストの大幅な上昇を招くため実用にはそぐわない。[0004] In order to reduce this soft error, it is possible to use highly pure materials (low uranium, low thorium) for ceramic packages or plastic packages, but this is not suitable for practical use because it causes a significant increase in cost.
【0005】このため不純物等から飛来するα線を減衰
、吸収させる手段として半導体素子上をポリイミド樹脂
もしくはポリイミド・イソインドロ・キナゾリジオン樹
脂(以下PII)によって覆って保護することが広く用
いられている。これらの樹脂は半導体素子上の外部電極
接続のための電極パット部に金ワイヤーなどの配線(ワ
イヤーボンディング)が終了した後に滴下するポッティ
ング法と、半導体素子が個々に切り出されていない(ス
クライビング前の)ウエハー段階で回転塗布するウエハ
ーコート法とがある。前者は切り出された半導体素子個
々に行なうため、工数・コストのアップにつながる。ま
た大面積の半導体チップや2辺の比が大きい長方形の半
導体チップでは樹脂が均一に半導体チップをコートでき
にくいなどの問題があるため、後者のウエハーコート法
が広く用いられつつある。その実施例を図3、図4を用
い説明する。なお同一部分には同一符号を付してある。For this reason, as a means to attenuate and absorb alpha rays coming from impurities and the like, it is widely used to cover and protect semiconductor elements with polyimide resin or polyimide isoindolo quinazolidione resin (hereinafter referred to as PII). These resins can be applied using the potting method, in which the semiconductor elements are dripped onto the electrode pads for connecting external electrodes after the wiring (wire bonding), such as gold wire, is completed, and the potting method, in which the semiconductor elements are not individually cut out (before scribing). ) There is a wafer coating method in which spin coating is performed at the wafer stage. The former process is performed on each cut out semiconductor element, which increases the number of man-hours and costs. Furthermore, in the case of large-area semiconductor chips or rectangular semiconductor chips with a large side-to-side ratio, there are problems such as difficulty in uniformly coating the semiconductor chip with resin, so the latter wafer coating method is becoming widely used. An example thereof will be explained using FIGS. 3 and 4. Note that the same parts are given the same reference numerals.
【0006】まず図3において半導体基板内あるいは上
に抵抗、トランジスタなどの各種素子を形成した後、外
部接続端子用の配線パッド2が図示しないホトリソ・エ
ッチング工程により、絶縁膜1上に形成される。この配
線パットは通常アルミニウム単体もしくはSi、Cu等
の不純物を含むアルミニウム合金が用いられる。この材
料は配線のみだけではなくトランジスタ等の素子を形成
する場合にも用いられる。次にリンなどの不純物を含む
酸化膜3、窒化シリコン膜4を順次形成する。これを図
示しないホトリソ・エッチング工程により配線パッド2
上の酸化膜3窒化シリコン膜4の一部を選択的に除去し
開口部5を形成し図1(a)の如き構造を得る。First, in FIG. 3, various elements such as resistors and transistors are formed in or on a semiconductor substrate, and then wiring pads 2 for external connection terminals are formed on the insulating film 1 by a photolithography/etching process (not shown). . This wiring pad is usually made of aluminum alone or an aluminum alloy containing impurities such as Si and Cu. This material is used not only for wiring but also for forming elements such as transistors. Next, an oxide film 3 containing impurities such as phosphorus and a silicon nitride film 4 are sequentially formed. The wiring pad 2 is removed by a photolithography/etching process (not shown).
A portion of the upper oxide film 3 and silicon nitride film 4 is selectively removed to form an opening 5 to obtain a structure as shown in FIG. 1(a).
【0007】次にポリイミド系樹脂6を全面に塗布し、
プリベークを例えば100℃で1分間行なう。Next, polyimide resin 6 is applied to the entire surface,
Prebaking is performed, for example, at 100° C. for 1 minute.
【0008】次に図示しないレジストを塗布しパターニ
ングを行ない、これをマスクにヒドラジン系エッチャン
トによるウェットエッチングや、ドライエッチングによ
り選択的にポリイミド系樹脂6をエッチングしレジスト
を除去することにより開口部7を形成し第1図(b)の
如き構造を得る。Next, a resist (not shown) is applied and patterned, and using this as a mask, the polyimide resin 6 is selectively etched by wet etching with a hydrazine etchant or dry etching, and the resist is removed to form the openings 7. The structure shown in FIG. 1(b) is obtained.
【0009】この後、窒素若しくは不活性ガス雰囲気中
でアニールを200℃と300℃で各々1時間行ないポ
リイミド系樹脂膜6の膜硬化を行なう。Thereafter, annealing is performed at 200° C. and 300° C. for 1 hour each in a nitrogen or inert gas atmosphere to cure the polyimide resin film 6.
【0010】図4は他の手法である。前記手法と同様に
絶縁膜1上に形成された配線パッド2上に、リン等を含
む酸化膜3窒化シリコン膜4を形成し、続いてポリイミ
ド系樹脂6を形成する。必要に応じてプリベークを行な
い、次に図示しないレジストを塗布しパターンニングを
行ない、これをマスクに連続的又は順次ポリイミド系樹
脂6、窒化シリコン膜4、酸化膜3をエッチング除去し
開口部5を形成し、レジストを除去することにより図4
(a)の如き構造を得る。FIG. 4 shows another method. Similar to the method described above, an oxide film 3 containing phosphorus or the like and a silicon nitride film 4 are formed on the wiring pad 2 formed on the insulating film 1, and then a polyimide resin 6 is formed. Prebaking is performed as necessary, and then a resist (not shown) is applied and patterned. Using this as a mask, polyimide resin 6, silicon nitride film 4, and oxide film 3 are etched away continuously or sequentially to form openings 5. Figure 4 by forming and removing the resist.
A structure as shown in (a) is obtained.
【0011】この後、窒素若しくは不活性ガス雰囲気中
でアニールを200℃と300℃で各々1時間行ないポ
リイミド系樹脂膜6の膜硬化を行なう。Thereafter, annealing is performed at 200° C. and 300° C. for 1 hour each in a nitrogen or inert gas atmosphere to cure the polyimide resin film 6.
【0012】0012
【発明が解決しようとする課題】しかしながら以上述べ
た方法では、いずれの場合であってもパターニングして
開口部を形成したポリイミド系樹脂をアニールし硬化さ
せるための熱処理中に、ポリイミド系樹脂に含まれる溶
媒や、低分子のポリイミド前駆体などの有機物が樹脂膜
中から脱離し、これらの物質(炭素が殆んど)が、配線
パッド上やウエハー上に再付着するという現象が起るこ
とが発見された。これを表したのが図3(c)及び図4
(b)に示す黒丸(8番)で有機系の物質を意味してい
る。[Problems to be Solved by the Invention] However, in any of the above methods, during the heat treatment for annealing and curing the polyimide resin that has been patterned to form openings, A phenomenon may occur in which organic substances such as solvents and low-molecular polyimide precursors are desorbed from the resin film, and these substances (mostly carbon) re-deposit on the wiring pads and wafers. It's been found. This is shown in Figures 3(c) and 4.
The black circle (number 8) shown in (b) means an organic substance.
【0013】図5は、配線パッド上に有機系物質が再付
着した状態で金線10によるボンディングを行った例で
、アルミの配線パッドと金線10の間に有機系物質が介
在したままになっている。この状態で金線10の剪断強
度を測定すると100g以下であった。一方、ポリイミ
ド系樹脂を用いない(例えば図3(a))配線パッド2
へ、有機系物質が再付着した状態でボンディングしたの
と同じボンディング条件でボンディングした金線の剪断
強度は130gを越えている。FIG. 5 shows an example in which bonding is performed using the gold wire 10 with the organic material re-attached to the wiring pad, and the organic material remains interposed between the aluminum wiring pad and the gold wire 10. It has become. When the shear strength of the gold wire 10 was measured in this state, it was 100 g or less. On the other hand, wiring pad 2 that does not use polyimide resin (for example, FIG. 3(a))
The shear strength of the gold wire bonded under the same bonding conditions as the bonding with the organic substance redeposited exceeds 130 g.
【0014】剪断強度の低下は、半導体素子をパッケー
ジに封入する際、溶融モールド材との接触圧力や温度に
よるストレスによりボンディング配線の配線パッド部で
の剥れを起すため半導体素子の信頼性が劣化するという
問題があった。またボンディング強度を増すためにはボ
ンディング時の温度、時間、圧力を上げれば良いが熱や
圧力によるストレスで配線パッド部もしくはその近傍に
割れ(クラック)が生じるという問題点があった。The decrease in shear strength is caused by the deterioration of the reliability of the semiconductor device because when the semiconductor device is sealed in a package, the contact pressure with the molten mold material and the stress caused by the temperature cause peeling of the bonding wiring at the wiring pad part. There was a problem. Furthermore, in order to increase the bonding strength, it is possible to increase the temperature, time, and pressure during bonding, but there is a problem in that the stress caused by heat and pressure causes cracks to occur at or near the wiring pad.
【0015】[0015]
【課題を解決するための手段】この発明は半導体素子の
保護膜であるポリイミド系樹脂の熱アニールによる硬化
工程後に、表面層をエッチングし配線パッド上の有機系
物質を除去するようにしたものである。[Means for Solving the Problems] The present invention etches the surface layer and removes organic substances on wiring pads after the polyimide resin, which is a protective film for semiconductor elements, is cured by thermal annealing. be.
【0016】[0016]
【作用】この発明の半導体素子の製造方法によれば、配
線パッド上の有機系物質をエッチングにより除去するよ
うにしたので、ワイヤボンディングによる金線と配線パ
ッドの密着性が上がるため前記問題点を除去できるので
ある。[Operation] According to the method of manufacturing a semiconductor device of the present invention, the organic substance on the wiring pad is removed by etching, which improves the adhesion between the gold wire and the wiring pad during wire bonding, thereby solving the above-mentioned problem. It can be removed.
【0017】[0017]
【実施例】図1(a)ないし(d)、図2(a)ないし
(c)は、この発明の実施例を示す工程断面図である。
なお同一部分には同一符号を付してある。Embodiment FIGS. 1(a) to 1(d) and FIGS. 2(a) to 2(c) are process sectional views showing an embodiment of the present invention. Note that the same parts are given the same reference numerals.
【0018】図1(a)ないし(c)、図2(a)ない
し(b)は従来例の製造方法と同じであるので説明を省
略する。1(a) to (c) and FIG. 2(a) to (b) are the same as the manufacturing method of the conventional example, so the explanation will be omitted.
【0019】まずポリイミド系樹脂をアニールし、膜硬
化工程を行った後、ウエハーを酸素ガスを含む反応系に
おいて、前記アニール工程により配線パッド部を含むウ
エハー全面に再付着した有機系物質を、例えばプラズマ
アッシングや光アッシングによりアッシング(灰化)処
理しウエハー表面層の一部をエッチング除去する。(図
1(d)の9および図2(c)の9)この工程を付加し
たことにより配線パッド上の有機系物質は除去される。
又、この工程はヒドラジン系のエッチャントによるウェ
ットエッチングであってもかまわない。First, the polyimide resin is annealed and a film curing process is performed, and then the wafer is placed in a reaction system containing oxygen gas, and the organic substances that have been redeposited over the entire surface of the wafer, including the wiring pad portion, are treated, for example, in a reaction system containing oxygen gas. Ashing (ashing) processing is performed using plasma ashing or optical ashing to remove a portion of the wafer surface layer by etching. (9 in FIG. 1(d) and 9 in FIG. 2(c)) By adding this step, the organic material on the wiring pad is removed. Further, this step may be wet etching using a hydrazine-based etchant.
【0020】ウエハー上のポリイミド系樹脂は、既に熱
硬化されているため前記エッチング工程を付加してもそ
の膜厚減少は少ない。例えば1000Å程度エッチング
するとしたら、その分最初に厚膜にしても良い。[0020] Since the polyimide resin on the wafer has already been thermally hardened, even if the etching process is added, the film thickness will not decrease much. For example, if the etching is about 1000 Å, the film may be made thicker at first.
【0021】この工程を付加した後、同一条件でボンデ
ィングした後の金線の剪断強度を測定したところ、従来
例では100g以下であったものが、ポリイミドを使わ
ない場合と同様に130g迄回復していた。After adding this step and bonding under the same conditions, the shear strength of the gold wire was measured, and it was found that the shear strength of the gold wire, which was less than 100 g in the conventional example, recovered to 130 g, the same as when no polyimide was used. was.
【0022】[0022]
【発明の効果】以上詳細に説明した通り、この発明によ
ればポリイミド系樹脂やPIIのパターニングおよびア
ニール熱硬化処理後、ウエハー表面全体をアッシング(
灰化)処理又はウェットエッチングする工程を付加した
ことにより引き出し電極部となる配線パッド上の有機系
物質を除去することができる。As explained in detail above, according to the present invention, after patterning and annealing thermosetting of polyimide resin or PII, the entire wafer surface is ashed (
By adding a step of ashing or wet etching, it is possible to remove the organic material on the wiring pad that will become the lead electrode portion.
【0023】従って、ボンディング条件(温度、圧力、
時間)を増大させることなく十分なボンディング強度を
得ることができ、パッシベーション保護膜のクラックや
ワイヤボンディング金線の剥れなどのデバイスの劣化を
防ぎ、高信頼性のデバイスを得ることができる。[0023] Therefore, bonding conditions (temperature, pressure,
Sufficient bonding strength can be obtained without increasing the time (time), device deterioration such as cracks in the passivation protective film and peeling of the wire bonding gold wire can be prevented, and a highly reliable device can be obtained.
【図1】この発明の第1の実施例を示す工程断面図[Fig. 1] Process cross-sectional diagram showing a first embodiment of this invention
【図
2】この発明の第2の実施例を示す工程断面図[Fig. 2] Process sectional view showing a second embodiment of this invention
【図3】
従来技術の第1の実施例を示す工程断面図[Figure 3]
Process cross-sectional diagram showing the first example of the conventional technology
【図4】従来
技術の第2の実施例を示す工程断面図[Fig. 4] Process sectional view showing a second embodiment of the conventional technology
【図5】従来技術
で配線パッド上に金線をボンディングした断面図[Figure 5] Cross-sectional view of gold wire bonded onto wiring pads using conventional technology
1 半導体基板
2 配線パッド
3 リンなどの不純物を含む酸化膜4 窒
化シリコン膜
5,7 開口部
6 ポリイミド系樹脂
8 有機系物質
9 エッチング
10 金線1 Semiconductor substrate 2 Wiring pad 3 Oxide film containing impurities such as phosphorus 4 Silicon nitride film 5, 7 Opening 6 Polyimide resin 8 Organic substance 9 Etching 10 Gold wire
Claims (1)
ポリイミド系樹脂又はポリイミド・イソインドロ・キナ
ゾリジオン(PII)を塗布しパターニングする工程と
、前記ポリイミド系樹脂又はPIIの硬化のための熱処
理を施す工程と、前記熱処理によりウエハー上に再付着
した有機系物質をエッチング除去する工程とを順次行う
ことを特徴とする半導体素子の製造方法。1. A step of applying and patterning a polyimide resin or polyimide isoindolo quinazolidione (PII) on a semiconductor wafer on which elements have been formed, and a step of applying heat treatment to harden the polyimide resin or PII. . A method of manufacturing a semiconductor device, comprising sequentially performing the steps of: etching away organic substances re-attached to the wafer due to the heat treatment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7323091A JPH04307937A (en) | 1991-04-05 | 1991-04-05 | Manufacture of semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7323091A JPH04307937A (en) | 1991-04-05 | 1991-04-05 | Manufacture of semiconductor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04307937A true JPH04307937A (en) | 1992-10-30 |
Family
ID=13512174
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7323091A Pending JPH04307937A (en) | 1991-04-05 | 1991-04-05 | Manufacture of semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04307937A (en) |
-
1991
- 1991-04-05 JP JP7323091A patent/JPH04307937A/en active Pending
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