JPH0431466U - - Google Patents
Info
- Publication number
- JPH0431466U JPH0431466U JP6851190U JP6851190U JPH0431466U JP H0431466 U JPH0431466 U JP H0431466U JP 6851190 U JP6851190 U JP 6851190U JP 6851190 U JP6851190 U JP 6851190U JP H0431466 U JPH0431466 U JP H0431466U
- Authority
- JP
- Japan
- Prior art keywords
- read signal
- delay circuit
- circuit
- signal
- data separator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001934 delay Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
- 230000010355 oscillation Effects 0.000 description 1
Landscapes
- Signal Processing For Digital Recording And Reproducing (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Description
第１図は、この考案によるデータセパレータ回
路の一実施例を示すブロツク図、第２図はこの考
案及び従来例を説明するためのタイミング図、第
３図は従来のデータセパレータ回路を示すブロツ
ク図である。
図において、１Ａは遅延回路、２は位相比較器
、３はフイルタ、４は電圧制御発振回路、５は分
周回路、６は制御指令装置である。なお、図中、
同一符号は同一又は相当部分を示す。
FIG. 1 is a block diagram showing an embodiment of a data separator circuit according to this invention, FIG. 2 is a timing diagram for explaining this invention and a conventional example, and FIG. 3 is a block diagram showing a conventional data separator circuit. It is. In the figure, 1A is a delay circuit, 2 is a phase comparator, 3 is a filter, 4 is a voltage controlled oscillation circuit, 5 is a frequency dividing circuit, and 6 is a control command device. In addition, in the figure,
The same reference numerals indicate the same or equivalent parts.
Claims (1)
読み出し信号を生成する遅延回路と、 上記第２の読み出し信号と基準周波数のクロツ
ク信号との位相を比較し、両者の位相が一致する
ように上記クロツク信号を制御する位相ロツク手
段と、 上記遅延回路を制御して上記第２の読み出し信
号のパルスの幅を可変する制御指令装置と を備えたことを特徴とするデータセパレータ回路
。[Claims for Utility Model Registration] A delay circuit that delays a read signal from a recording medium to generate a second read signal, and a phase comparison between the second read signal and a clock signal of a reference frequency, and and a control command device that controls the delay circuit to vary the pulse width of the second read signal. Data separator circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6851190U JPH0431466U (en) | 1990-06-29 | 1990-06-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6851190U JPH0431466U (en) | 1990-06-29 | 1990-06-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0431466U true JPH0431466U (en) | 1992-03-13 |
Family
ID=31603011
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6851190U Pending JPH0431466U (en) | 1990-06-29 | 1990-06-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0431466U (en) |
-
1990
- 1990-06-29 JP JP6851190U patent/JPH0431466U/ja active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH0431466U (en) | ||
| JPS59180774U (en) | ultrasonic oscillator | |
| JPS6067556U (en) | clock regeneration circuit | |
| JPH03115955U (en) | ||
| JPS6114578U (en) | color synchronization circuit | |
| JPS5883992U (en) | Phase synchronization control circuit | |
| JPS60102690U (en) | Radiation measuring instrument noise prevention circuit | |
| JPS63181037U (en) | ||
| JPS5843043U (en) | frequency synthesizer | |
| JPS6064617U (en) | Multiplier circuit | |
| JPH048538U (en) | ||
| JPH01171186U (en) | ||
| JPS6123785U (en) | Time axis correction device | |
| JPH01140667U (en) | ||
| JPH0361786U (en) | ||
| JPS6336195U (en) | ||
| JPS6384634U (en) | ||
| JPS6292177A (en) | Data separator circuit | |
| JPS5849285U (en) | timer clock circuit | |
| JPS59174733U (en) | pulse generator | |
| JPS6251569U (en) | ||
| JPS6044490U (en) | Inverter control device | |
| JPS5986731U (en) | Tuning control circuit | |
| JPS5988953U (en) | clock synchronizer | |
| JPS6090925U (en) | comb filter |