JPH043156B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a chroma key device, and particularly to a chroma key device that generates an optimal key signal depending on a foreground image using a simple configuration.

An embodiment of the present invention applied to a digital chromakey device will be described below.

Formation of a key signal in an embodiment of the present invention will be explained with reference to FIG. A foreground image in which a subject, such as a person, is positioned in front of a screen with a background color, e.g., blue, is captured by a color camera, and the foreground color video signal output from this camera is digitized, and each sample data is stored in the (U-V) coordinate system. A key signal is formed by comparison with a reference value in (chromaticity coordinate system).

This reference value is an area defined by a group of straight lines. As shown in FIG. 1, the central axis of the key signal is assumed to be the angle from the U axis. Let P ₁ be the straight line perpendicular to this central axis, and P ₂ , P ₃ be the straight lines that intersect at the opening angles +θ, -θ, and these straight lines P ₁ , P ₂ ,
The polygonal line formed by P ₃ is defined as the boundary between the subject and the screen.

If one sample data of the foreground color video signal is (U _A , V _A ), each of the above straight lines can be drawn from this point.
The minimum distance among the distances _{d 1} , d ₂ , and d ₃ to P 1 , P ₂ , and P ₃ is taken as the level of the key signal. If the distances of straight lines P ₁ , P ₂ (P ₃ ) from the origin O are ER ₁ , ER ₂ , then d ₁ ,
d ₂ and d ₃ can be calculated using the following formula.

d ₁ = VA・sinα+U _A・cosα−ER ₁ …(1) d ₂ =−V _A・cos(α+θ)+U _A・sin
(α+θ)−ER ₂ …(2) d ₃ =V _A・cos(α−θ)−U _A・sin(
α+θ)−ER ₂ (3) Ideally, the data corresponding to the blue screen of the foreground color video signal is on the central axis. A trajectory is drawn on the vectorscope by changes in color difference data as the object changes from the blue screen. Since the center axis and the above-mentioned locus may deviate from each other due to the blue paint of the screen actually used, lighting, etc., parameters such as α and θ are adjusted so that the two coincide. In order to easily and accurately perform this adjustment, P ₁ , P ₂ ,
It is necessary to display the background color area determined by the straight line group of _P3 .

A method of generating a boundary signal for displaying a boundary using a vector scope will be described with reference to FIG. 2 and subsequent figures.

As shown in Figure 2, four points A (ua,
va), B (ub, vb), C (uc, vc), D (ud, vd), and U (t), V (t ) and then generate a chroma signal. For example, when moving from point A to point B over a time period of τ, U(t)=ua−ub/τ×t+ua V(t)=va−vb/τ×t+va.

Point B and point C can be found by calculating at the intersection of straight lines P ₁ , P ₂ , and P ₃ . Points A and D can be found by appropriately providing a straight line P ₁ ′ parallel to the straight line P ₁ (giving an appropriate ER ₁ ′), and finding the intersection between this and the straight lines P ₂ and P ₃ . . In this example, (A→B→C→
Boundary display is performed by changing (D→C→B→A→B...).

To further explain the calculation for finding the intersections A, B, C, and D, the straight lines P ₁ , P ₁ ', P ₂ , and P ₃ are expressed as follows.

P ₁ :V=m ₁・U+a ₁ ……(4) P ₁ ′ :V=m ₁・U+a ₁ ′ ……(4)′ P ₂ :V=m ₂・U+a ₂ ……(5) P ₃ :V= _m3・U+ _a3 ...(6) Then, as shown in Figure 3, if the angle between the straight lines _P1 and _P1 ' with the U axis is _m1 =sin/cos=sin(α- 3/2π)/cos(α−3
/2π) = −cosα/sinα……(7) m ₂ = sin(α+θ)/cos(α+θ)……(8) m ₃ = sin(α−θ)/cos(α−θ)……(9 ): V=sinα／cosα・U ...(10) If the intersection of the straight line P ₁ and the central axis is (u ₁ , v ₁ ), then ER ² ₁ = u ² ₁ + v ² ₁ ... (11) (4 ), (7), and (10), sinα/cosα・u ₁ = −cosα/sinαu ₁ + a ₁ From this, u ₁ = a ₁・sinα・cosα ...(12) (12) can be converted to (10) ) and then v ₁ = a ₁・sin ² α ... (13) Substitute equations (12) and (13) into equation (11) and get ER ² ₁ = a ² ₁ sin ² α (sin ² α＋cos ² α)=a ² ₁ sin ² α Therefore, a ₁ =±ER ₁ /sinα ...(14) a ₁ ′=±ER ₁₁ /sinα ...(15) a ₂ =±ER ₂ /cos (α + θ) ... (16) a ₃ = ±ER ₂ / cos (α - θ) ... (17) Now, the intersection of two arbitrary straight lines V=k ₁・U+b ₁ V=k ₂・U+b ₂ is ( u, v), then u=(b ₂ − b ₁ )/(k ₁ − _{k 2} ) ……(18) v=k ₁・b ₂ −k ₂・b ₁ /k ₁ −k ₂ ……( 19) When finding the intersection A (ua, va) in Figure 2, use equations (15) and (16) for b ₁ , b ₂ , k ₁ , and k ₂ in equations (18) and (19), respectively. a ₁ ′, a ₂ in equations (7) and (8)
Just substitute m ₁ and m ₂ . Similarly, B
The intersection points of (ub, vb), C (uc, vc), and D (ud, vd) are found.

Also, if sinα, cos(α+θ), and cos(α−θ) become zero, that is, any of the straight lines P ₁ , P ₂ , and P ₃ becomes V
If it is parallel to the axis, find the intersection using the following method.

First, as shown in FIG. 4A, when the straight line _P1 is parallel to the V axis, the intersection points are as shown below.

ub＝uc＝ER ₁ ua＝ud＝ER ₁ ′ va＝sinθ／cosθ・ER ₁ ′＋ER ₂ /cosθ vd＝−va vb＝sinθ／cosθ・ER ₁ +ER ₂ /cosθ vc＝−vb Also, the fourth As shown in Figure B, when the straight line _P2 is parallel to the V axis, each intersection point is as shown below.

va=vb= _ER2 va=-cosα/sinα· _ER2 + _ER1 '/sinα vb=-cosα/sinα·ER2+ _ER1 /sinα Points C and D are determined by the general method _described above. Furthermore, when the straight line P ₃ is parallel to the V axis,
Each intersection point is found in the same way as when the straight line P ₂ is parallel to the V axis.

Hereinafter, one embodiment of the present invention will be described. FIG. 5 shows the overall configuration. In the figure, 1 is an input terminal for a foreground color video signal;
is the input terminal for the background color video signal.

Both color video signals are digitized by A/D converters 3 and 4 at a sampling frequency of, for example, 4sc (sc is the frequency of the color subcarrier). The foreground color video data from the A/D converter 3 is passed through the delay circuit 5 to the multiplier 6.
The background color video data from the A/D converter 4 is supplied to the multiplier 7. A coefficient K (which can take a value in the range of 0 to 1) corresponding to the level of the key signal is supplied to the multiplier 6;
The multiplier 7 includes an inverter (1-
K) coefficients are provided. The outputs of the multipliers 6 and 7 are supplied to an adder 9. Therefore, the adder 9 obtains composite color video data in which both the foreground and background color video data are composited,
It is supplied to one input terminal of the switch circuit 10.

The other input terminal of the switch circuit 10 has
A boundary signal from RAM 11 is supplied. RAM
11, the data of the intersections A, B, C, and D formed by the CPU 12 as described above is written. The CPU 12 receives α,
Given the values of θ, ER ₁ (ER ₁ ′ is fixed), and ER ₂ , the values of each intersection (ua~ud, va~
vd) is required. Next, the CPU 12 calculates and obtains chroma data that moves linearly at each intersection. This chroma data is written to RAM11.

An address counter 13 is provided in association with the RAM 11. A reference horizontal synchronizing signal and a reference color subcarrier are supplied to this address counter 13 from terminals 14 and 15, respectively.
(horizontal scanning period) as a unit, and an address that changes at a cycle of 1/4sc is formed. The boundary data read from the RAM 11 is converted into an analog signal by the D/A converter 16 via the switch circuit 10 and output to the output terminal 17.

In the boundary signal thus formed, as shown in FIG. 6, the carrier color signals corresponding to the intersections of A, B, C, and D are located sequentially within 1H period. In the next 1H period, the order is (D→C→B→A). Therefore, if the carrier color signal shown in Fig. 6 is demodulated, converted into analog, and supplied to a vector scope synchronized with the standard horizontal synchronization signal and color subcarrier, each intersection point will be bright as shown in Fig. 7. Therefore, it is possible to display a boundary in which the straight line between the intersection points is shown faintly.

The switch circuit 10 is switched by the output of the AND gate 18. The AND gate 18 receives the output of the switch circuit 19 and the 1 from the terminal 20.
A pulse signal that is inverted for each field is supplied. When the low level output is generated by the switch circuit 19, the output of the AND gate 18 will also be low level, and the switch circuit 10 will be in a state to select the composite color video data from the adder 9. Further, when a high level output is generated by the switch circuit 19, the switch circuit 10 is switched for each field. As will be described later, in this case, only the foreground color video data emerges from the adder 9, so that the switch circuit 10 generates foreground color video data and boundary data alternately for each field.

A monitor receiver is connected to the output terminal 17 together with a vector scope or a waveform tube, and during normal chromakey operation, a composite image that is a chromakey output can be viewed through the monitor receiver. In addition, when foreground color video data and boundary data exist alternately in each field, there is flicker, but the foreground image can be seen on a monitor receiver, and the foreground image can be seen on a vector scope. A display in which a locus of color data of foreground color video data is superimposed on the boundary display shown in FIG. 7 is made. Based on this display, parameters such as α and θ are changed so that the boundary for generating the key signal is optimal.

Furthermore, to explain the generation of the key signal in one embodiment of the present invention, the output of the delay circuit 5 is supplied to the Y/C separation circuit 21, the color signal data is supplied to the digital color demodulation circuit 22, and the color data U , V are retrieved.

These input color data are used as address inputs to the RAM 23. The RAM 23 contains data tables 24, 25, 26, which are calculated by the CPU 12.
27, 28, and 29 are written in advance. Predetermined output data converted by each of the data tables 24 to 29 are sent to the adders 30, 31,
It is added by 32. The output of adder 30 is supplied to subtracter 33, and data _ER1 stored in latch circuit 34 is subtracted. This subtractor 33
The data d ₁ expressed by the above-mentioned equation (1) is generated at the output of .

Furthermore, in order to use the smallest one among d ₁ , d ₂ , and d ₃ as the key signal, first, d ₂ and d ₃ (not including ER ₂ ) are compared. Therefore, the outputs of the adders 31 and 32 are supplied to the comparison circuit 35 and the selector 36, and the smaller one of the two is taken out from the selector 36, which is supplied to the subtracter 37, and the data ER stored in the latch 38 is ₂ is subtracted. Therefore, the output of the subtractor 37 contains d ₂ and
Among d ₃ , the one with a lower level appears, and this and d ₁ from the subtracter 33 are supplied to the comparison circuit 39 and the selector 40 . Then, the data of the lowest level among d ₁ , d ₂ , and d ₃ is extracted as the output of the selector 40 .

This data is used as address input to the RAM 41. A data table regarding gain and clip level created by the CPU 12 is stored in the RAM 41. In other words, slice operations and gain control processing on analog signals are
This is done by RAM41. As the clip level, only the peak clip level or both the bottom clip level and the peak clip level are used. The output of this RAM 41 is band-limited by a digital filter 42, and a digital key signal is generated at the output of this digital filter 42.

This key signal is supplied to the switch circuit 43. The other input terminal of this switch circuit 43 is supplied with data corresponding to (K=1) from a terminal 44. The switch circuit 19 and the switch circuit 43 mentioned above are interlocked, and when a normal chroma key operation is performed, the key signal from the filter 42 is selected, and the synthesized signal is mixed at a ratio according to the level of this key signal. Color video data is generated from adder 9. Further, when performing boundary display, since (K=1) is set, only the foreground color video data appears at the output of the adder 9.

As understood from the description of one embodiment above,
According to this invention, the range of the key signal can be set to a predetermined value using the straight line group, and therefore it is possible to form the optimal key signal according to the color of the screen actually used and the color of the subject. can. Furthermore, since the range of the key signal can be set using a group of straight lines, the range of the key signal can be determined relatively easily using the CPU or the like.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram used to explain the key signal forming method in this invention, FIG. 2, FIG. 3, and FIG.
The figure is a schematic diagram used to explain the method of forming a boundary signal in this invention, FIG. 5 is a block diagram showing the configuration of an embodiment of this invention, and FIGS. They are a waveform diagram and a schematic diagram used for explanation. 1...Foreground color video signal input terminal, 2...
...Input terminal for background color video signal, 6, 7...
Multiplier, 11, 24, 41...RAM, 12...
CPU, 17...output terminal, 35, 39...comparison circuit, 36, 40...selector.

Claims (1)

[Scope of Claims] 1. A first multiplication circuit that receives a foreground color video signal in which a subject is located in front of a predetermined background color and multiplies it by a coefficient K; and an addition circuit that adds and outputs an output signal of the first multiplier circuit and an output signal of the second multiplier circuit, the foreground color video A Y/C separation circuit separates a color signal from a signal, and the background color area is defined by a plurality of straight lines in a (U-V) coordinate system, and a selection circuit that outputs a signal indicating the minimum distance between the coordinates in the U-V coordinate system and the plurality of straight lines;
and a key signal generation circuit that forms the coefficient 1-K and supplies it to the first multiplication circuit and the second multiplication circuit.