JPH0431U - - Google Patents
Info
- Publication number
- JPH0431U JPH0431U JP4070390U JP4070390U JPH0431U JP H0431 U JPH0431 U JP H0431U JP 4070390 U JP4070390 U JP 4070390U JP 4070390 U JP4070390 U JP 4070390U JP H0431 U JPH0431 U JP H0431U
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- cmos
- nand element
- output
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Safety Devices In Control Systems (AREA)
- Electronic Switches (AREA)
Description
第１図はこの考案の実施例を示すもので、ＣＰ
Ｕのリセツト回路を示す回路図、第２図は第１図
に示す回路のタイム・チヤートである。第３図は
従来のＣＰＵのリセツト回路の一例を示す回路図
、第４図は第３図に示す回路のタイム・チヤート
である。
１０……ＣＰＵ、１１，１２，１３，１４……
Ｃ ＭＯＳ ＮＡＮＤ素子、２０……トランジス
タ、２１，２２，２４，２５，２６，２９……抵
抗、２３，２８……コンデンサ、２７……ダイオ
ード、３１……第１の充放電回路、３２……第２
の充放電回路。
Figure 1 shows an embodiment of this invention.
FIG. 2 is a circuit diagram showing the reset circuit of U. FIG. 2 is a time chart of the circuit shown in FIG. FIG. 3 is a circuit diagram showing an example of a conventional CPU reset circuit, and FIG. 4 is a time chart of the circuit shown in FIG. 10... CPU, 11, 12, 13, 14...
C MOS NAND element, 20...Transistor, 21, 22, 24, 25, 26, 29...Resistor, 23, 28...Capacitor, 27...Diode, 31...First charge/discharge circuit, 32... Second
charging/discharging circuit.
Claims (1)
ブル割込み端子をもつ制御装置のリセツトを行な
う回路において、 スイツチング制御信号によりスイツチング制御
され、電源電圧をノンマスカブル割込み端子に与
えるスイツチング手段、 上記スイツチング手段が制御されることに応じ
て電源電圧が与えられる第１のＣ ＭＯＳ ＮＡ
ＮＤ素子、 出力端子が上記ストツプ端子と接続されている
第２のＣ ＭＯＳ ＮＡＮＤ素子、 入力側が上記第１のＣ ＭＯＳ ＮＡＮＤ素子
の出力端子と出力側が上記第２のＣ ＭＯＳ Ｎ
ＡＮＤ素子の入力端子とそれぞれ接続され、上記
第１のＣ ＭＯＳ ＮＡＮＤ素子の出力信号に応
じて充放電を行なう第１の充放電回路、 上記スイツチング手段が制御されることに応じ
て電源電圧が与えられる第３のＣ ＭＯＳ ＮＡ
ＮＤ素子、 出力端子がリセツト端子と接続されている第４
のＣ ＭＯＳ ＮＡＮＤ素子、ならびに 入力側が上記第３のＣ ＭＯＳ ＮＡＮＤ素子
の出力端子と出力側が上記第４のＣ ＭＯＳ Ｎ
ＡＮＤ素子の入力端子とそれぞれ接続され上記第
３のＣ ＭＯＳ ＮＡＮＤ素子の出力信号に応じ
て充放電を行なう第２の充放電回路、 を備えた制御装置のリセツト回路。[Claims for Utility Model Registration] In a circuit for resetting a control device having a reset terminal, a stop terminal, and a non-maskable interrupt terminal, a switching means that is controlled by a switching control signal and applies a power supply voltage to a non-maskable interrupt terminal; A first CMOS NA to which a power supply voltage is applied in accordance with the control of
ND element, a second CMOS NAND element whose output terminal is connected to the stop terminal; the input side is the output terminal of the first CMOS NAND element, and the output side is the second CMOS NAND element.
a first charge/discharge circuit that is connected to the input terminals of the AND element and performs charging and discharging according to the output signal of the first CMOS NAND element; 3rd CMOS NA
ND element, the fourth whose output terminal is connected to the reset terminal
C MOS NAND element, and the input side is the output terminal of the third C MOS NAND element, and the output side is the output terminal of the fourth C MOS NAND element.
A reset circuit for a control device, comprising: a second charging/discharging circuit that is connected to the input terminals of the AND element and performs charging and discharging according to the output signal of the third CMOS NAND element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4070390U JP2504003Y2 (en) | 1990-04-18 | 1990-04-18 | Reset circuit of controller |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4070390U JP2504003Y2 (en) | 1990-04-18 | 1990-04-18 | Reset circuit of controller |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0431U true JPH0431U (en) | 1992-01-06 |
| JP2504003Y2 JP2504003Y2 (en) | 1996-07-03 |
Family
ID=31550720
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4070390U Expired - Lifetime JP2504003Y2 (en) | 1990-04-18 | 1990-04-18 | Reset circuit of controller |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2504003Y2 (en) |
-
1990
- 1990-04-18 JP JP4070390U patent/JP2504003Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JP2504003Y2 (en) | 1996-07-03 |
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