JPH04320572A - Data processor - Google Patents

Abstract

PURPOSE:To execute data selecting processing at high speed even when selecting conditions are complexed and to improve the using efficiency of a hardware arithmetic circuit. CONSTITUTION:This data processor is provided with plural controllers 13-1 to 13-m for selecting data and the processing of file data to be computed is divided by these controllers 13-1 to 13-m. Output data prepared by the controllers 13-1 to 13-m are successively outputted to the hardware arithmetic circuit 14 under the control of an arbitor 15. Since the preparation of the output data to the circuit 14 is executed in parallel by the controllers 13-1 to 13-m, data selecting processing can be executed at high speed even when their selecting conditions are complexed and the using efficiency of the circuit 14 can be improved.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing apparatus, and more particularly to a data processing apparatus equipped with a dedicated hardware arithmetic circuit for performing sorting or relational operations on a relational database.

0002

2. Description of the Related Art In recent years, in computer systems that handle databases, dedicated hardware arithmetic circuits have been used to perform high-speed arithmetic processing on databases consisting of large amounts of data.

[0003] This hardware arithmetic circuit executes sorting operations, relational operations in relational databases, etc. on data selected from within a database, such as rearranging a group of selected records according to key values. The database is reconfigured by processing.

However, since this hardware arithmetic circuit only facilitates a specific arithmetic function for database reconfiguration, when complex selection conditions are specified in, for example, sorting processing, the hardware arithmetic circuit Before inputting data, it is necessary to select the data in advance.

[0005] In this data selection, for example, a process is performed in which a key value assigned to each record is compared with a reference value, and only records that satisfy selection conditions are selected as output data to a hardware arithmetic circuit.

[0006] In conventional computer systems, there is usually only one data selection mechanism that performs such data selection, and that one data selection mechanism performs selection processing on all the data to be operated on. Ta.

[0007] For this reason, when the record selection conditions become more complex, the data selection process in the data selection mechanism takes time. In this case, a lot of time is required for the processing at the front stage of the hardware arithmetic circuit, which results in a decrease in the usage efficiency of the hardware arithmetic circuit. This decrease in the usage efficiency of the hardware arithmetic circuit is a major cause of decreasing the efficiency of database reconfiguration processing.

[0008] In this way, in the conventional computer system,
Even if high-speed hardware arithmetic circuits are provided, if the selection conditions become complex, the usage efficiency of the hardware arithmetic circuits will decrease. There was a problem that the overall performance was lowered.

[0009]

Conventionally, when the selection conditions become complicated, the usage efficiency of the hardware arithmetic circuit is reduced, and the arithmetic processing of the database requires a lot of time.

The present invention has been made in view of the above points, and has an object to enable data selection processing to be executed at high speed even when selection conditions become complicated, and to improve the usage efficiency of hardware arithmetic circuits. The purpose is to provide a data processing device that can.

[0011]

[Means and Operations for Solving the Problems] A data processing device according to the present invention includes a memory that stores file data consisting of a plurality of records, and performs predetermined arithmetic processing on input data using key values of the records. An arithmetic circuit to be executed and a plurality of data selection means each receiving a distributed input of file data to be operated on and stored in the memory, and each creating data to be output to the arithmetic circuit from the input file data according to predetermined selection conditions. and output control means for sequentially outputting a plurality of output data created by the plurality of data selection means to the arithmetic circuit, the output data being created to the arithmetic circuit by the plurality of data selection means in parallel. It is characterized by being executed in a specific manner.

[0012] In this data processing device, a plurality of data selection means are provided, and processing for file data to be operated on is shared among these plurality of data selection means. These data selection means perform processes such as data selection and processing on the respective file data in accordance with the selection conditions, and create data to be output to the arithmetic circuit. The output data created by these data selection means are sequentially output to the arithmetic circuit by the output control means. Therefore, the creation of output data to the arithmetic circuit is executed in parallel by multiple data selection means, so even if the selection conditions become complex, data selection processing can be executed at high speed, making the use of the arithmetic circuit more efficient. It is possible to improve the

[0013]

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows the system configuration of a computer system according to an embodiment of the present invention. This computer system is a database system that constructs and generates desired data using a database stored in a magnetic disk device (not shown), and includes a system bus 10, a central processing unit (CPU) 11, a main memory 12, a It includes n-th controllers 13-1 to 13-m, a hardware arithmetic circuit 14, and an arbiter 15.

[0015] A central processing unit (CPU) 11 is in charge of overall control of this computer system, and is responsible for the first to mth
A command is issued to the controllers 13-1 to 13-m to cause them to perform calculations on the file data.

In this case, the commands supplied from the central processing unit (CPU) 11 to each of the controllers 13-1 to 13-m are sent to a buffer indicating the storage location (memory address) of the file data to be operated on in the main memory 12. information and
Logical information of the file data to be computed (block length, record length, key position, key length), the type of computation to be executed (sort computation, or relational computation in a relational database), and accompanying conditions associated with that computation (selection conditions) and buffer information indicating the storage location (memory address) of the calculation result on the main memory 12.

The main memory 12 stores calculation target file data read from a magnetic disk device (not shown), calculation results obtained by the controllers 13-1 to 13-m and the hardware calculation circuit 14, and the like. Here, the first address of the storage position of the file data to be calculated is "A1", and the first address of the storage position of the calculation result is "B1", so the buffer information indicating the storage position of the file data to be calculated is address"
A1" is designated, and address "B1" is designated as buffer information indicating the storage location of the calculation result.

[0018] First to m-th controllers 13-1 to 1
3-m uses a hardware arithmetic circuit 14 to execute an arithmetic operation specified by a central processing unit (CPU) 11 on file data to be arithmetic, and each of these controllers includes, for example, a microprocessor. Each of them is composed of RAM and the like.

Here, processing for file data to be calculated is performed by these m controllers 13-1 to 13-.
Shared by m. This calculation target file data allocation is performed based on a command from the central processing unit (CPU) 11, for example.

That is, the central processing unit (CPU) 11 determines the number of records of the file data to be calculated, and equally allocates the records to be calculated to the m controllers 13-1 to 13-m.

Each of the controllers 13-1 to 13-m selects a record for the file data in charge, processes the selected record, and thereby creates data to be output to the hardware arithmetic circuit 14. do. Records are selected and processed by the central processing unit (CPU) 1.
It is executed according to the selection conditions specified from 1.

That is, in the selection process, a record that satisfies the selection condition is selected by comparing the key value of the record with a reference value. In addition, in the processing, the selected record is processed into a data format compatible with the calculation processing of the hardware calculation circuit 14. In this processing, for each selected record, a process of extracting only the key field specified by the selection condition and a process of assigning an identifier to the extracted key field are executed.

[0023] This identifier is used to identify which record the extracted key field belongs to.
The start address of the storage position of the record above 2 can be used. Regarding the selection and processing of such data by the controllers 13-1 to 13-m, see FIG.
will be described later with reference to.

The hardware arithmetic circuit 14 is a dedicated arithmetic circuit that performs sorting or relational arithmetic operations on a relational database in order to reconstruct file data.
-m or directly via a control line (not shown) to the central processing unit (CPU 1).
You will be notified from 1. The calculation result of the hardware calculation circuit 14 is stored in a predetermined storage location on the main memory 12 (a storage area whose top address is address B1).

[0025] The arbiter 15 controls the controllers 13-1 to 13-1.
This is an output arbitration circuit for sequentially outputting a plurality of output data created in 13-m to the hardware arithmetic circuit 14 so as not to conflict with each other. This arbiter 1
5 receives data output request signals (REQ) output from the controllers 13-1 to 13-m, and sends a response signal (ACK) to approve the requests according to predetermined priority information.
be returned in order.

The controller that receives the response signal (ACK) is permitted to output data, and the other controllers wait for data output until they receive the response signal (ACK). As a result, data is outputted from the controllers 13-1 to 13-m without interruption.

FIG. 2 shows an example of a specific structure of file data stored on the main memory 12. As shown, the file data consists of n records R1
-Rn, and each record R1-Rn is composed of five fields f1-f5.

Record R1 is stored at the location specified by the start address A1 on the main memory 12, and similarly, record R2 is stored at the start address A2, record R3 is stored at the start address A3, and record R4 is stored at the start address A3.
4.Furthermore, record Rn is stored at a position whose start address is specified by An. Next, the controllers 13-1 to 1 for the file data configured in this way
The operation of data selection and processing by 3-m will be explained.

Here, five fields f1 to f5 of each record R1 to Rn constituting the file data in FIG.
Among them, the second field f2 is the controller 13-1.
~13-m is designated as a key field (first priority key field) for performing selection processing, and the fourth field f4 is designated as a key field (second priority key field) for performing calculation processing by hardware calculation circuit 14. Assume that it is specified as a key field).

In this case, the key values of records R1 to Rn in the first priority key field are K1 to Kn, and the key values of records R1 to Rn in the second priority key field are K1' to Kn. ´ is.

[0031] Such double specification of key fields is as follows:
For example, this is performed when sorting is performed using both the data item defined in the second field f2 and the data item defined in the fourth field f4.

When the controllers 13-1 to 13-m receive an arithmetic command from the central processing unit (CPU) 11, they each take in the record group assigned by the central processing unit (CPU) 11 from the main memory 12. Each of the controllers 13-1 to 13-m is
The key value of the first priority key field in the record in charge is compared with a reference value specified by the central processing unit (CPU) 11, and only records that satisfy the selection conditions are selected.

Next, from among the five fields f1 to f5 included in this selected record, the second priority key field (fourth field f4) used in the arithmetic processing of the hardware arithmetic circuit 14 is selected. Only key values are extracted. This extracted key value is given address information (starting address on the main memory 12) indicating the storage position of the record to which the key belongs as an identifier. As a result, a data string consisting of the extracted key value and address information is constructed, and this becomes output data to the hardware arithmetic circuit 14. FIG. 3 shows an example of output data to the hardware arithmetic circuit 14 created as a result of such data selection and processing.

As shown in the figure, the record R1 to be operated on is processed into a data string R1' consisting of the key value K1' of the fourth field f4 and the address A1, and similarly, the record R2 to be operated on is processed to the data string R1' consisting of the key value K1' of the fourth field f4 and the address A1. is processed into a data string R2' consisting of the key value K2' and address A2, and the record R4 to be operated on has the key value K4 of the fourth field f4.
' and address A4, and furthermore, the record Rn to be operated on is stored in the fourth field f.
A data string R consisting of a key value Kn' of 4 and an address An.
Processed into n'.

Furthermore, in this example, the record R to be operated on is
Although the output data corresponding to No. 3 is not shown, this means that the key value K2 of the second field f2 of record R3 did not satisfy the specified condition.

Each of the controllers 13-1 to 13-m sequentially executes such data selection and processing processing on the records it is responsible for, and each time it finishes processing on one record, that is, one Every time an output data string is created, a data output request signal (REQ) is issued. and,
When receiving a response signal (ACK) from the arbiter 15, the output data is supplied to the hardware arithmetic circuit 14.

The hardware arithmetic circuit 14 sorts the input data selected and processed by the controllers 13-1 to 13-m using key values K1', K2', K4', etc., or sorts the input data in a relational database. Relational calculations, etc. are performed, and as a result, the data strings R1', R
2', R4', . . . are selected and rearranged.

The calculation results of the hardware calculation circuit 14 are as follows:
The data is written to a storage area starting from address B1 on the main memory 12. In this case, the operation results include the selected and rearranged data strings R1', R2', and R4'.
Among them, only address information (A1, A2, A4...) can be used.

That is, the hardware arithmetic circuit 14 is
Address information (
A1, A2, A4...) is generated and stored in the main memory 12 in order.

The calculation results stored in the main memory 12 are referenced by the central processing unit (CPU) 11 and used to obtain desired file data. That is, the central processing unit (CPU) 11 selects records R1 to R1 of file data to be operated on, which are stored in the main memory 12.
Rn is rearranged in the order of the address information indicated by the calculation results, a new file is created according to the designated calculation results, and the reconstructed file information is stored in a magnetic disk device (not shown).

As described above, in this embodiment, a plurality of controllers 13-1 to 13-1 are used for data selection.
m is provided, and these controllers 13-1 to 1
Processing for the file data to be calculated is shared by 3-m. These controllers 13-1 to 13-m
The output data created in is sequentially output to the hardware arithmetic circuit 14 under the control of the arbiter 15.

Therefore, the creation of output data to the hardware arithmetic circuit 14 is performed by a plurality of controllers 13-1 to 1.
3-m in parallel, data selection processing can be executed at high speed even if the selection conditions are complicated, and the efficiency of use of the hardware arithmetic circuit 14 can be improved.

[0043] Here, the controllers 13-1 to 1
In the data processing process using 3-m, only the specified key is extracted and address information is added to the extracted key as an identifier. Therefore, depending on the function of the hardware arithmetic circuit 14, it is also possible to create all fields of the selected record as output data to the hardware arithmetic circuit 14 without extracting the specified key. It is.

In this case, since the specified key is extracted within the hardware arithmetic circuit 14, in order to simplify the extraction process, the controllers 13-1 to 1
In step 3-m, it is preferable to move the field of the specified key to the first field of the record in advance. FIG. 4 shows the configuration of a computer system according to a second embodiment of the present invention.

Similar to the computer system of the first embodiment shown in FIG. 1, this second embodiment has a configuration in which a plurality of controllers share and process the file data to be processed. Controllers 23-1 to 23-m and output buffers 24-1 to 24-m are provided in place of 13-1 to 13-m, and a priority control circuit 25 is provided in place of arbiter 15. ing.

The controllers 23-1 to 23-m, like the controllers 13-1 to 13-m, sequentially execute selection and processing on the records in charge, and output the created data in record units to the corresponding output buffer 24-1. ~24-m
Store in. Further, when data storage in the output buffer is completed, a data output request is issued to the priority control circuit 25. When the priority control circuit 25 receives a data output request, the priority control circuit 25 outputs the output buffers 24-1 to 24-1 according to predetermined priority information.
24-m.

[0047] With this configuration, processing for the next record can be executed with the creation data written in the output buffer, so selection and processing for the record to be operated on can be executed at higher speed.

[0048]

[Effects of the Invention] As described above, according to the present invention, data selection processing can be executed at high speed even when selection conditions become complicated, thereby improving the usage efficiency of hardware arithmetic circuits. It is possible to achieve faster calculation processing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a system configuration according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an example of the configuration of calculation target file data in the same embodiment.

FIG. 3 is a diagram showing an example of the configuration of output data created by a plurality of controllers provided in the embodiment.

FIG. 4 is a block diagram showing a system configuration according to a second embodiment of the invention.

[Explanation of symbols]

11...CPU, 12...Main memory, 13-1 to 13-
m...Controller, 14...Hardware arithmetic circuit, 15
…arbiter.

Claims (3)

[Claims] 1. A memory that stores file data consisting of a plurality of records, an arithmetic circuit that performs predetermined arithmetic processing on input data using key values of the records, and an arithmetic operation target stored in the memory. a plurality of data selection means each receiving a distributed input of file data and creating data to be output to the arithmetic circuit from the input file data according to predetermined selection conditions; and a plurality of data selection means created by the plurality of data selection means. A data processing device comprising: output control means for sequentially outputting output data to the arithmetic circuit, and generating output data to the arithmetic circuit in parallel by the plurality of data selection means. 2. The data processing device according to claim 1, wherein the arithmetic circuit performs arithmetic processing on the file data, including sorting or relational operations in a relational database. 3. The data selection means selects a record requested by the selection condition from among the operation target file data using a key value of the record;
2. The data processing apparatus according to claim 1, further comprising means for processing the selected record into a data format compatible with arithmetic processing by said arithmetic circuit.