JPH04322448A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH04322448A JPH04322448A JP11811591A JP11811591A JPH04322448A JP H04322448 A JPH04322448 A JP H04322448A JP 11811591 A JP11811591 A JP 11811591A JP 11811591 A JP11811591 A JP 11811591A JP H04322448 A JPH04322448 A JP H04322448A
- Authority
- JP
- Japan
- Prior art keywords
- silicon oxide
- oxide film
- phosphorus
- film
- containing silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 16
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 62
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 62
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims abstract description 26
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 26
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 26
- 239000011574 phosphorus Substances 0.000 claims abstract description 26
- 238000000034 method Methods 0.000 claims abstract description 23
- 238000004528 spin coating Methods 0.000 claims abstract description 14
- 239000011229 interlayer Substances 0.000 claims abstract description 10
- 239000012298 atmosphere Substances 0.000 claims abstract description 9
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 8
- 239000001301 oxygen Substances 0.000 claims abstract description 8
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 8
- 239000011248 coating agent Substances 0.000 claims abstract description 5
- 238000000576 coating method Methods 0.000 claims abstract description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 22
- 229910052796 boron Inorganic materials 0.000 claims description 22
- 238000010438 heat treatment Methods 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 7
- 125000000217 alkyl group Chemical group 0.000 claims description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 2
- 239000000654 additive Substances 0.000 claims description 2
- 230000000996 additive effect Effects 0.000 claims description 2
- 125000001183 hydrocarbyl group Chemical group 0.000 claims description 2
- 239000001257 hydrogen Substances 0.000 claims description 2
- 229910052739 hydrogen Inorganic materials 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 9
- 229920005591 polysilicon Polymers 0.000 abstract description 9
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 6
- 239000010410 layer Substances 0.000 abstract description 4
- 101000635799 Homo sapiens Run domain Beclin-1-interacting and cysteine-rich domain-containing protein Proteins 0.000 abstract 1
- 102100030852 Run domain Beclin-1-interacting and cysteine-rich domain-containing protein Human genes 0.000 abstract 1
- 239000002075 main ingredient Substances 0.000 abstract 1
- CPUDPFPXCZDNGI-UHFFFAOYSA-N triethoxy(methyl)silane Chemical compound CCO[Si](C)(OCC)OCC CPUDPFPXCZDNGI-UHFFFAOYSA-N 0.000 abstract 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 9
- 239000007864 aqueous solution Substances 0.000 description 5
- 239000000243 solution Substances 0.000 description 5
- 239000012299 nitrogen atmosphere Substances 0.000 description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
Landscapes
- Local Oxidation Of Silicon (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Weting (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は半導体装置の製造方法に
関し、特に層間絶縁膜の形成方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming an interlayer insulating film.
【０００２】0002
【従来の技術】半導体高集積回路において、平坦化層間
絶縁膜を用いることは、必須である。2. Description of the Related Art In highly integrated semiconductor circuits, it is essential to use a planarizing interlayer insulating film.
【０００３】従来、この種の平坦化層間絶縁膜は、以下
の工程で作成されていた。すなわち、図３に示すように
能動素子を有する半導体基板３０１上に第１の電極・ゲ
ートポリシリコン電極３０３を形成する。３０２はシリ
コン酸化膜である。その後、化学気相成長法により、ホ
ウ素／リン含有シリコン酸化膜３０４を形成し、続いて
９００℃の窒素雰囲気中で３０分間熱処理を行い上記ホ
ウ素／リン含有シリコン酸化膜のリフローを行う。続い
て、第１アルミニウム配線３０５を形成していた（参考
文献１９８２，ＲＣＡ Ｒｅｖｉｅｗ Ｐ．４２３
〜）。Conventionally, this type of planarized interlayer insulating film has been produced by the following steps. That is, as shown in FIG. 3, a first electrode/gate polysilicon electrode 303 is formed on a semiconductor substrate 301 having active elements. 302 is a silicon oxide film. Thereafter, a boron/phosphorus containing silicon oxide film 304 is formed by chemical vapor deposition, followed by heat treatment in a nitrogen atmosphere at 900° C. for 30 minutes to reflow the boron/phosphorus containing silicon oxide film. Subsequently, the first aluminum wiring 305 was formed (Reference 1982, RCA Review P.423
~).
【０００４】0004
【発明が解決しようとする課題】上述した従来の技術に
おいて、化学気相成長法により形成した第１のホウ素／
リン含有シリコン酸化膜は、配線幅が広く孤立している
部分のパターン上での膜厚と配線のないフィールド領域
での膜厚とが等しいため、下地段差は緩和されない。さ
らに、第２・第３のＣＶＤ法シリコン酸化膜においても
、同様の形状を示すため、第３のＣＶＤ法シリコン酸化
膜形成後の形状は悪く、上に形成したアルミニウム配線
が断線、あるいは短絡してしまい、多層配線構造の形成
が困難であるばかりか、歩留り，信頼性が著しく損なわ
れてしまうという問題を有している。[Problems to be Solved by the Invention] In the above-mentioned conventional technology, the first boron/
In the phosphorus-containing silicon oxide film, the film thickness on the pattern in the isolated portion where the wiring width is wide is equal to the film thickness in the field region where there is no wiring, so that the difference in base level is not alleviated. Furthermore, since the second and third CVD silicon oxide films exhibit similar shapes, the shapes after forming the third CVD silicon oxide film are poor, and the aluminum wiring formed above may be disconnected or short-circuited. This poses a problem in that not only is it difficult to form a multilayer wiring structure, but also yield and reliability are significantly impaired.
【０００５】本発明の目的は、パターン依存性をなくし
、多層化を可能にする多層配線構造体の製造方法を提供
することにある。An object of the present invention is to provide a method for manufacturing a multilayer wiring structure that eliminates pattern dependence and enables multilayering.
【０００６】[0006]
【課題を解決するための手段】前記目的を達成するため
、本発明に係る半導体装置の製造方法においては、能動
素子を有する半導体基板上に、第１の配線を形成する工
程と、上記形成された第１の配線上に、層間絶縁膜の一
部として回転塗布法によりシリコン酸化膜を形成する工
程と、上記回転塗布法により形成されたシリコン酸化膜
の一部を薄い弗化水素酸溶液でエッチングする工程と、
８５０℃以下の温度で、かつ酸素雰囲気中で熱処理する
工程とを含むものである。[Means for Solving the Problems] In order to achieve the above object, a method for manufacturing a semiconductor device according to the present invention includes a step of forming a first wiring on a semiconductor substrate having an active element, and a step of forming a first wiring on a semiconductor substrate having an active element. A step of forming a silicon oxide film as part of the interlayer insulating film on the first wiring by a spin coating method, and a step of coating a part of the silicon oxide film formed by the spin coating method with a thin hydrofluoric acid solution. The etching process and
The method includes a step of heat treatment at a temperature of 850° C. or lower and in an oxygen atmosphere.
【０００７】また、前記シリコン酸化膜は、Ｒｎ−Ｓｉ
（ＯＲ′）４−ｎ，Ｓｉ（ＯＲ″）４（ｎ＝１，２，３
）（Ｒ：１価の炭化水素基，Ｒ′：アルキル基，Ｒ″：
水素又はアルキル基）のうちの少なくとも１つを主成分
とする塗布溶液を用いて形成されるものである。[0007] Furthermore, the silicon oxide film is made of Rn-Si
(OR')4-n, Si(OR'')4(n=1,2,3
) (R: monovalent hydrocarbon group, R': alkyl group, R'':
It is formed using a coating solution containing at least one of hydrogen or alkyl groups as a main component.
【０００８】また、前記回転塗布法により形成されるシ
リコン酸化膜は、添加物としてリンあるいはホウ素のう
ち少なくとも１つを含有するものである。Furthermore, the silicon oxide film formed by the spin coating method contains at least one of phosphorus and boron as an additive.
【０００９】[0009]
【作用】能動素子を有する半導体基板上に第１の配線を
形成し、上記形成された第１の配線上に層間絶縁膜の一
部として回転塗布法によりシリコン酸化膜を形成し、上
記回転塗布法により形成されたシリコン酸化膜の一部を
薄い弗化水素酸溶液でエッチングし、続いて８５０℃以
下の温度で、かつ、酸素雰囲気中で熱処理するものであ
る。[Operation] A first wiring is formed on a semiconductor substrate having an active element, a silicon oxide film is formed as a part of an interlayer insulating film by a spin coating method on the first wiring formed above, and a silicon oxide film is formed by a spin coating method. A part of the silicon oxide film formed by the method is etched with a dilute hydrofluoric acid solution, and then heat-treated at a temperature of 850° C. or less in an oxygen atmosphere.
【００１０】0010
【実施例】次に本発明について図面を参照して説明する
。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.
【００１１】（実施例１）図１は、本発明の実施例１を
工程順に示す縦断面図である。(Embodiment 1) FIG. 1 is a longitudinal cross-sectional view showing a first embodiment of the present invention in the order of steps.
【００１２】図１（ａ）に示すように、能動素子を有す
る半導体基板１０１に、シリコン酸化膜１０２を介して
、厚さ０．４μｍのポリシリコン電極１０３を形成し、
レジストを用いた公知の方法でパターニングする。
次に、ポリシリコン電極１０３上に化学気相成長法を用
いてシリコン酸化膜１０４を１０００Å形成する。続い
て、主成分がＳｉ（ＯＣ２Ｈ５）４とＣＨ３−Ｓｉ（Ｏ
Ｃ２Ｈ５）３との混合物からなり、かつＰ２Ｏ５を５ｍ
ｏｌ％、Ｂ２Ｏ３を１０ｍｏｌ％含む塗布溶液を４００
０ｒｐｍで２０秒間回転塗布する。この後、１５０℃の
ホットプレートで２０秒間熱処理を行い、続いて４００
℃の窒素雰囲気中で３０分間熱処理を行い、ホウ素／リ
ン含有シリコン酸化膜１０５を形成する。As shown in FIG. 1A, a polysilicon electrode 103 with a thickness of 0.4 μm is formed on a semiconductor substrate 101 having an active element with a silicon oxide film 102 interposed therebetween.
Patterning is performed by a known method using resist. Next, a silicon oxide film 104 with a thickness of 1000 Å is formed on the polysilicon electrode 103 using chemical vapor deposition. Subsequently, the main components are Si(OC2H5)4 and CH3-Si(O
consisting of a mixture of C2H5)3 and 5m of P2O5.
400% of coating solution containing 10 mol% of B2O3
Spin coat at 0 rpm for 20 seconds. After this, heat treatment was performed on a hot plate at 150°C for 20 seconds, followed by a heat treatment at 400°C.
Heat treatment is performed for 30 minutes in a nitrogen atmosphere at .degree. C. to form a boron/phosphorous containing silicon oxide film 105.
【００１３】次に、図１（ｂ）に示すように、純水と弗
化水素酸との割合が５０：１の薄い弗化水素酸水溶液で
上記ホウ素／リン含有シリコン酸化膜１０５を３０秒間
エッチングする。Next, as shown in FIG. 1B, the boron/phosphorus containing silicon oxide film 105 is coated with a dilute hydrofluoric acid aqueous solution having a ratio of pure water to hydrofluoric acid of 50:1 for 30 seconds. etching.
【００１４】続いて図１（ｃ）に示すように、８５０℃
の酸素雰囲気中で１時間熱処理を行い、上記ホウ素／リ
ン含有シリコン酸化膜１０５をリフローし、ホウ素／リ
ン含有シリコン酸化膜リフロー膜１０６を形成する。こ
のときのホウ素／リン含有シリコン酸化膜膜厚は０．２
μｍである。Next, as shown in FIG. 1(c), the temperature was 850°C.
Heat treatment is performed in an oxygen atmosphere for one hour to reflow the boron/phosphorous containing silicon oxide film 105 to form a boron/phosphorus containing silicon oxide film reflow film 106. At this time, the thickness of the boron/phosphorous containing silicon oxide film was 0.2
It is μm.
【００１５】さらに図１（ｄ）に示すように、上記ホウ
素／リン含有シリコン酸化膜リフロー膜１０６上に化学
気相成長法を用いてシリコン酸化膜１０７を厚さ０．２
μｍに形成する。Furthermore, as shown in FIG. 1(d), a silicon oxide film 107 is formed to a thickness of 0.2 on the boron/phosphorous containing silicon oxide film reflow film 106 by chemical vapor deposition.
Formed to μm.
【００１６】ここで、低温（４００℃）ベーク後のホウ
素／リン含有シリコン酸化膜の純水と弗化水素酸との割
合が５０：１の薄い弗化水素酸水溶液に対するエッチン
グレートは、平坦な部分で３００〜４００（Å／ｍｉｎ
）と小さい。しかしながら段差側壁から底部にかけては
、１０００〜２０００（Å／ｍｉｎ）と平坦部と比較し
、かなり大きい値である。このような純水と弗化水素酸
との割合が５０：１の薄い弗化水素酸水溶液に対するエ
ッチングレートの差を利用して図１（ｂ）に示すような
形状のホウ素／リン含有シリコン酸化膜を形成すること
ができ、さらに８５０℃の酸素雰囲気中で１時間リフロ
ーすることにより、図１（ｃ）に示すようなホウ素／リ
ン含有シリコン酸化膜を形成することができる。Here, the etching rate of the boron/phosphorus-containing silicon oxide film after baking at a low temperature (400° C.) in a dilute hydrofluoric acid aqueous solution with a ratio of pure water to hydrofluoric acid of 50:1 is flat. 300 to 400 (Å/min
) and small. However, from the step sidewall to the bottom part, the value is 1000 to 2000 (Å/min), which is considerably larger than that in the flat part. Utilizing the difference in etching rate for a dilute hydrofluoric acid aqueous solution with a ratio of pure water and hydrofluoric acid of 50:1, boron/phosphorus-containing silicon oxide in the shape shown in Figure 1(b) is etched. A film can be formed, and by further reflowing in an oxygen atmosphere at 850° C. for 1 hour, a boron/phosphorous containing silicon oxide film as shown in FIG. 1(c) can be formed.
【００１７】以上のように形成されたホウ素／リン含有
シリコン酸化膜リフロー膜１０６を有する層間絶縁膜は
、配線のないフィールド領域に厚く形成できることから
、パターン依存がなく、十分な平坦性が得られ、さらに
上層アルミニウム配線の断線，短絡は発生せず、多層化
が可能となり、高歩留りかつ良好なデバイス特性を得る
ことができる。Since the interlayer insulating film having the boron/phosphorus-containing silicon oxide reflow film 106 formed as described above can be formed thickly in the field area where there is no wiring, there is no pattern dependence and sufficient flatness can be obtained. Furthermore, there is no disconnection or short-circuiting of the upper layer aluminum wiring, making it possible to have multiple layers, resulting in high yield and good device characteristics.
【００１８】本実施例においては、ホウ素／リン含有シ
リコン酸化膜とポリシリコン電極との間に化学気相成長
法により、シリコン酸化膜を形成しているが、上記化学
気相成長シリコン酸化膜を形成しない場合においても、
同様の効果を得ることができる。In this example, a silicon oxide film is formed between the boron/phosphorous containing silicon oxide film and the polysilicon electrode by chemical vapor deposition. Even if it does not form,
A similar effect can be obtained.
【００１９】また、本実施例において、回転塗布法で形
成される膜として、ホウ素／リン含有シリコン酸化膜を
用いたが、リン含有シリコン酸化膜、あるいはホウ素含
有シリコン酸化膜においても同様の結果を得ることがで
きる。Furthermore, in this example, a boron/phosphorous containing silicon oxide film was used as the film formed by the spin coating method, but similar results could be obtained with a phosphorus containing silicon oxide film or a boron containing silicon oxide film. Obtainable.
【００２０】（実施例２）図２は、本発明の実施例２を
工程順に示す断面図である。(Embodiment 2) FIG. 2 is a sectional view showing a second embodiment of the present invention in the order of steps.
【００２１】図２（ａ）に示すように、能動素子を有す
る半導体基板２０１上にポリシリコン電極２０３を形成
し、レジストを用いた公知の方法でパターニングする。
上記ポリシリコン電極上に主成分がＳｉ（ＯＣ２Ｈ５）
４とＣＨ３−Ｓｉ（ＯＣ２Ｈ５）３との混合物からなり
、かつＰ２Ｏ５を８ｍｏｌ％含む塗布溶液を４０００ｒ
ｐｍで２０秒間回転塗布する。この後、１５０℃のホッ
トプレートで２０秒間熱処理を行い、続いて４００℃の
窒素雰囲気中で３０分間熱処理を行い、第１のリン含有
シリコン酸化膜２０４を形成する。As shown in FIG. 2A, a polysilicon electrode 203 is formed on a semiconductor substrate 201 having active elements, and patterned by a known method using a resist. The main component is Si (OC2H5) on the above polysilicon electrode.
4000r
Spin coat at pm for 20 seconds. Thereafter, heat treatment is performed on a hot plate at 150° C. for 20 seconds, and then heat treatment is performed in a nitrogen atmosphere at 400° C. for 30 minutes to form the first phosphorus-containing silicon oxide film 204.
【００２２】次に図２（ｂ）に示すように、純水と弗化
水素酸との割合が５０：１の薄い弗化水素酸水溶液で上
記第１のリン含有シリコン酸化膜２０４を３０秒間エッ
チングする。Next, as shown in FIG. 2B, the first phosphorus-containing silicon oxide film 204 is coated with a dilute hydrofluoric acid aqueous solution having a ratio of pure water and hydrofluoric acid of 50:1 for 30 seconds. etching.
【００２３】続いて、８５０℃の酸素雰囲気中で１時間
熱処理を行う。このときの上記第１のリン含有シリコン
酸化膜２０４の膜厚は０．３μｍである。[0023] Subsequently, heat treatment is performed for 1 hour in an oxygen atmosphere at 850°C. The thickness of the first phosphorus-containing silicon oxide film 204 at this time is 0.3 μm.
【００２４】次に図２（ｃ）に示すように、上記８５０
℃の熱処理を行った第１のリン含有シリコン酸化膜２０
４上に、第１のリン含有シリコン酸化膜形成時に用いた
ときのと同じ溶液を４０００ｒｐｍで２０秒間回転塗布
し、厚さ０．３μｍの第２のリン含有シリコン酸化膜２
０５を形成する。Next, as shown in FIG. 2(c), the above 850
First phosphorus-containing silicon oxide film 20 subjected to heat treatment at ℃
A second phosphorus-containing silicon oxide film 2 with a thickness of 0.3 μm is formed by spin-coating the same solution used in forming the first phosphorus-containing silicon oxide film 2 at 4000 rpm for 20 seconds on top of 4.
Form 05.
【００２５】この後、図２（ｄ）に示すように、１５０
℃のホットプレートで２０秒間熱処理を行い、続いて２
４００℃の窒素雰囲気中で３０分間熱処理を行い、最後
に８５０℃の酸化雰囲気中で１時間熱処理を行い、リン
含有シリコン酸化膜２０６が形成される。After that, as shown in FIG. 2(d), 150
Heat treatment was performed on a hot plate at ℃ for 20 seconds, followed by 2
Heat treatment is performed in a nitrogen atmosphere at 400° C. for 30 minutes, and finally heat treatment is performed in an oxidizing atmosphere at 850° C. for 1 hour to form a phosphorus-containing silicon oxide film 206.
【００２６】本実施例では、第１のリン含有シリコン酸
化膜で高温（〜８５０℃）熱処理後、直ちに第２のリン
含有シリコン酸化膜を成膜したが、上層に形成された膜
が塗布法により形成された膜であるために、平坦性は良
好であった。In this example, the second phosphorus-containing silicon oxide film was formed immediately after the first phosphorus-containing silicon oxide film was heat-treated at a high temperature (~850°C), but the film formed on the upper layer was Since the film was formed using the same method, the flatness was good.
【００２７】ここで、本実施例で形成したときの形状と
従来技術で形成したときの形状を比較してみると、従来
技術で形成した場合、配線幅が広く孤立している部分の
パターン上での膜厚と配線のないフィールド領域でのそ
の生じる段差は０．４μｍと、下地段差と同程度であっ
たが、本実施例で形成した場合、第１層目の層間絶縁膜
を配線層の広い部分にのみ形成するため、配線幅が広く
孤立している部分との生じる膜厚差は０．１μｍと小さ
く、十分な平坦性を得ることができ、さらに上部配線の
断線，短絡は全く発生せず、多層配線形成が容易に可能
で、高歩留りかつ良好なデバイス特性を得ることができ
る。Comparing the shape formed in this example and the shape formed by the conventional technique, it is found that when formed by the conventional technique, the pattern on the isolated part with a wide wiring width is The film thickness and the resulting step in the field area without wiring were 0.4 μm, which was about the same as the underlying step. However, when formed in this example, the first interlayer insulating film was Since it is formed only on the wide part of the wiring, the difference in film thickness between the wide and isolated parts is as small as 0.1 μm, and sufficient flatness can be obtained, and there is no disconnection or short circuit in the upper wiring. It is possible to easily form multilayer interconnections, and to obtain high yield and good device characteristics.
【００２８】尚、本実施例において、回転塗布法で形成
される膜として、リン含有シリコン酸化膜を用いたが、
ホウ素／リン含有シリコン酸化膜あるいは、ホウ素含有
シリコン酸化膜あるいは、シリコン酸化膜においても、
同様の結果を得ることができる。In this example, a phosphorus-containing silicon oxide film was used as the film formed by the spin coating method.
In boron/phosphorus-containing silicon oxide film, boron-containing silicon oxide film, or silicon oxide film,
Similar results can be obtained.
【００２９】[0029]
【発明の効果】以上説明したように本発明は、層間絶縁
膜の一部として回転塗布法によりシリコン酸化膜を形成
し、薄い弗化水素酸水溶液で上記回転塗布法シリコン酸
化膜の一部をエッチングし、続いて高温（〜８５０℃）
の酸素雰囲気中で熱処理することにより、配線幅が広く
孤立している部分と、配線のないフィールド領域との生
じる段差が低減できることから、十分な平坦性が得られ
、上層配線の断線，短絡は発生せず、高歩留りかつ良好
なデバイス特性を得ることができ、さらに信頼性も向上
するという効果を有する。また、多層化が容易となると
いう効果を有している。As explained above, the present invention forms a silicon oxide film as part of an interlayer insulating film by a spin coating method, and then coats a portion of the silicon oxide film by spin coating with a thin hydrofluoric acid aqueous solution. Etching followed by high temperature (~850℃)
By heat treatment in an oxygen atmosphere, it is possible to reduce the difference in level between the wide and isolated part of the wiring and the field area with no wiring, thereby achieving sufficient flatness and preventing disconnections and short circuits in the upper layer wiring. This has the effect that high yields and good device characteristics can be obtained without any occurrence of oxidation, and reliability is further improved. It also has the effect of facilitating multi-layering.
【図１】本発明の実施例１を工程順に示す断面図である
。FIG. 1 is a cross-sectional view showing a first embodiment of the present invention in order of steps.
【図２】本発明の実施例２を工程順に示す断面図である
。FIG. 2 is a cross-sectional view showing a second embodiment of the present invention in order of steps.
【図３】従来例を示す断面図である。FIG. 3 is a sectional view showing a conventional example.
１０１ 半導体基板
１０２ シリコン酸化膜
１０３ ポリシリコン電極
１０４ ＣＶＤ法シリコン酸化膜
１０５ ホウ素／リン含有シリコン酸化膜１０６
ホウ素／リン含有シリコン酸化膜リフロー膜１０７
ＣＶＤ法シリコン酸化膜
２０１ 半導体基板
２０２ シリコン酸化膜
２０３ ポリシリコン電極
２０４ 第１のリン含有シリコン酸化膜２０５ 第
２のリン含有シリコン酸化膜２０６ リン含有シリコ
ン酸化膜101 Semiconductor substrate 102 Silicon oxide film 103 Polysilicon electrode 104 CVD silicon oxide film 105 Boron/phosphorous containing silicon oxide film 106
Boron/phosphorous containing silicon oxide film reflow film 107
CVD silicon oxide film 201 Semiconductor substrate 202 Silicon oxide film 203 Polysilicon electrode 204 First phosphorus-containing silicon oxide film 205 Second phosphorus-containing silicon oxide film 206 Phosphorus-containing silicon oxide film
Claims (3)
１の配線を形成する工程と、上記形成された第１の配線
上に、層間絶縁膜の一部として回転塗布法によりシリコ
ン酸化膜を形成する工程と、上記回転塗布法により形成
されたシリコン酸化膜の一部を薄い弗化水素酸溶液でエ
ッチングする工程と、８５０℃以下の温度で、かつ酸素
雰囲気中で熱処理する工程とを含むことを特徴とする半
導体装置の製造方法。1. A step of forming a first wiring on a semiconductor substrate having an active element, and forming a silicon oxide film as part of an interlayer insulating film by a spin coating method on the first wiring formed as described above. a step of etching a part of the silicon oxide film formed by the spin coating method with a dilute hydrofluoric acid solution; and a step of heat treatment at a temperature of 850° C. or less in an oxygen atmosphere. A method for manufacturing a semiconductor device, characterized in that:
ＯＲ′）４−ｎ，Ｓｉ（ＯＲ″）４（ｎ＝１，２，３）
（Ｒ：１価の炭化水素基，Ｒ′：アルキル基，Ｒ″：水
素又はアルキル基）のうちの少なくとも１つを主成分と
する塗布溶液を用いて形成されることを特徴とする請求
項１に記載の半導体装置の製造方法。2. The silicon oxide film is made of Rn-Si (
OR')4-n, Si(OR'')4(n=1,2,3)
A claim characterized in that it is formed using a coating solution containing at least one of (R: monovalent hydrocarbon group, R': alkyl group, R'': hydrogen or alkyl group) as a main component. 1. The method for manufacturing a semiconductor device according to 1.
コン酸化膜は、添加物としてリンあるいはホウ素のうち
少なくとも１つを含有することを特徴とする請求項１に
記載の半導体装置の製造方法。3. The method of manufacturing a semiconductor device according to claim 1, wherein the silicon oxide film formed by the spin coating method contains at least one of phosphorus and boron as an additive.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11811591A JP3158486B2 (en) | 1991-04-22 | 1991-04-22 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11811591A JP3158486B2 (en) | 1991-04-22 | 1991-04-22 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04322448A true JPH04322448A (en) | 1992-11-12 |
| JP3158486B2 JP3158486B2 (en) | 2001-04-23 |
Family
ID=14728403
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11811591A Expired - Fee Related JP3158486B2 (en) | 1991-04-22 | 1991-04-22 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3158486B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8309265B2 (en) | 2003-09-12 | 2012-11-13 | Hitachi, Ltd. | Electrolyte membrane for fuel cells, its production and fuel cell using the same |
| JP6025279B1 (en) * | 2015-10-28 | 2016-11-16 | 孝己 伊藤 | Multi-layered decorative bowl unit |
-
1991
- 1991-04-22 JP JP11811591A patent/JP3158486B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP3158486B2 (en) | 2001-04-23 |
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