JPH04322529A - Scramble synchronization recovery circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scramble synchronization recovery device that newly acquires scramble synchronization when a receiver receiving a scrambled transmission signal loses scramble synchronization.

0002

2. Description of the Related Art Conventionally, when a receiver loses scramble synchronization, it either gives up on reception or descrambles the received signal in all cases of scrambled signals, and checks whether the scramble is descrambled in all cases. , tested and judged by humans.

However, in the conventional method of restoring scramble synchronization through human testing and judgment as described above, it takes a certain amount of time for human judgment, so it is difficult to perform tests and judgments on all cases of scrambled signals. , it would take an unrealistic amount of time. Further, if multiple people perform tests and judgments to solve the scramble in a short time, a large amount of labor costs will be required.

0004

[Problems to be Solved by the Invention] As described above, in the past, scramble synchronization was recovered by artificial testing and judgment, so it would be unrealistic to perform tests and judgments for all cases of scrambled signals. Furthermore, if multiple people are required to perform tests and judgments to solve the scramble in a short period of time, a large amount of labor costs will be required.

The present invention was made in order to solve the above-mentioned problems, and an object of the present invention is to provide a scramble synchronization recovery device that recovers scramble synchronization by unscrambling in a short time and without incurring large labor costs. purpose.

[0006]

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a scramble synchronization recovery method that newly acquires scramble synchronization when a receiver receiving a scrambled transmission signal loses scramble synchronization. In the apparatus, a storage means for storing known information of the transmission signal in advance, a scramble synchronization variable control means for changing the scramble synchronization with respect to the received signal of the receiver, information obtained from the received signal by this means and the storage. Comparison/judgment means for comparing known information stored in the means to detect a match or a maximum likelihood state between the two; and a scramble synchronization selection for stopping the change in the scramble synchronization when the means detects a match or a maximum likelihood state. and means.

[0007]

[Operation] In the scramble synchronization recovery device having the above configuration, known information of the transmission signal is stored in advance, and when the scramble synchronization is lost, the scramble synchronization is changed and the information obtained from the received signal and the stored known information are stored. A match or a maximum likelihood state is detected by comparing the information, and when a match or a maximum likelihood state is detected, the change in scramble synchronization is stopped to recover scramble synchronization.

[0008]

Embodiments Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1 to 4.

FIG. 1 shows a first embodiment, in which the present invention is applied to a receiver that receives and descrambles scrambled digital audio signals.

In FIG. 1, the received signal is a scrambled digital audio signal. This received signal is supplied to a descrambler (DSCR) 1. This descrambler 1 applies a scramble signal generated by a scramble signal generator (PG) 6 to an input received signal to descramble it. Scramble signal generator 6
can generate several types of scramble signals through the control circuit 5.

A digital signal output from the descrambler 1 (a digital audio signal obtained if the scramble synchronization is normal) is converted into an analog signal by a decoder (DEC) 2. It is already known that this analog signal should be a voice band signal.

The analog signal is subjected to frequency analysis by a spectrum analyzer (SPA) 3 and sent to a determination circuit 4. This determination circuit 4 determines whether the scrambled signal is appropriate or not based on the spectrum obtained by frequency analysis. The judgment result of this judgment circuit 4 is sent to the control circuit 5. This control circuit 5 receives the determination result, and if it is determined to be inappropriate, the scramble signal generator 6
This control is repeated until it is determined to be appropriate, and when it is determined to be appropriate, the generator 6 is locked to generate the scramble signal in that state. be. In the above configuration,
The operation will be explained below.

Assume that the descrambler 1 performs scramble synchronization normally. In this case, when the output digital signal is passed through the decoder 2 to be converted into an analog signal and subjected to frequency analysis using the spectrum analyzer 3, the spectrum has a distribution with many audio band components as shown in FIG.

On the other hand, in the descrambler 1,
If the scramble synchronization is lost for some reason, the spectrum of the analog signal often becomes flat (white noise) as shown in FIG.

Therefore, in this embodiment, the known information that the analog signal is a voice band signal is used to cause the determination circuit 4 to identify the above-mentioned difference and determine whether the scrambled signal is appropriate or not.

The determination circuit 4 can be easily realized by, for example, using a personal computer having a GPIB function, transferring and inputting measurement data from the spectrum analyzer 3, and performing mask determination of the spectral shape.

When the determination circuit 4 determines that there are many audio band components in the spectrum distribution and that the scramble signal is appropriate, the control circuit 5 generates a scramble signal so as to continue generating the scramble signal at that time. Lock device 6. Further, when the determination circuit 4 determines that the spectral distribution is flat and the scramble signal is inappropriate, the control circuit 5 controls the scramble signal generator 6 to generate the next scramble signal. Repeat until deemed appropriate.

In this way, the scramble signal generator 6
If the spectrum is locked, that is, if a spectrum with a distribution with many audio band components is detected, there is a high possibility that scramble synchronization has been recovered. In order to further improve accuracy, it is preferable to perform upper-level determination and selection through the control circuit 5, such as by switching back and forth the selection of the scramble signal generated by the scramble signal generator 6. What is the top judgment and selection?
For example, judgment and selection by humans. However, the determination and selection of the higher rank only requires confirmation, and does not take much time.

Therefore, if the scramble synchronization recovery device having the above configuration is used, even if the scramble synchronization is lost, it will automatically select a scramble signal, determine its suitability, and search for a suitable scramble signal, thereby eliminating the need for human intervention. Most of the work will now be done at the level of confirmation. This makes it possible to descramble and restore scramble synchronization in a relatively short time and without incurring large personnel costs.

FIG. 4 shows a second embodiment, in which the present invention is applied to a receiver that receives and descrambles scrambled 8-bit serial data signals (numbers, characters). shows the configuration of In addition, in FIG. 4, the same parts as in FIG. 1 are denoted by the same symbols,
Here, we will mainly explain the different parts.

In FIG. 4, the received signal is a scrambled serial data signal. This received signal is supplied to a descrambler 1, and a scramble signal generator 6
After being descrambled by a scramble signal generated by , it is sent to a serial/parallel converter (S/P) 7 where it is converted into a parallel data signal of every 8 bits. We already know that this parallel data should be numbers or letters.

In this embodiment, this fact is utilized to determine the suitability of the scramble signal. That is, 8-bit parallel data of at least some numbers and characters is stored in the table 8 in advance, and the determination circuit 4 compares and collates the data signal obtained by the descrambler 1 with the data stored in the table 8.

[0023] If there is no scramble synchronization,
Parallel data is often data that is not included in the stored data of table 8. On the other hand, if scramble synchronization is performed, the parallel data always matches any of the stored data in table 8.

The control circuit 5 receives the match/mismatch judgment result from the judgment circuit 4, and if it is judged that they match for a certain period of time, it locks the scramble signal generator 6 as it is, and if the judgment of mismatch continues, it starts the next scramble. generate a signal.

In this way, the scramble signal generator 6
is locked, that is, if parallel data matching any of the contents of table 8 is detected for a certain period of time, there is a high possibility that scramble synchronization has been recovered. In order to further improve accuracy, as in the first embodiment, a scramble signal generator 6 is
It is advisable to make higher-level judgments and selections, such as by looking back and forth in the selection of scramble signals generated in .

Therefore, in this embodiment as well, when the scramble synchronization is lost, a scramble signal is automatically selected, its suitability is determined, and a suitable scramble signal is searched, so that almost no human work is required. Scramble synchronization can be recovered by unscrambling in a relatively short time and without incurring large personnel costs.

In the second embodiment, the case where the data is numbers and characters has been explained, but limited control other than numbers and characters, such as SI (shift in) and SO (shift out), Of course, the present invention can also be applied to code data that includes a code. In this case, this can be easily handled by adding these control codes to Table 8.

[0028]

As described above, according to the present invention, it is possible to provide a scramble synchronization recovery device that recovers scramble synchronization by unscrambling in a short time and without incurring large personnel costs.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram showing a first embodiment of a scramble synchronization recovery device according to the present invention.

FIG. 2 is a spectrum distribution diagram when the scramble signal of the same embodiment is appropriate.

FIG. 3 is a spectrum distribution diagram when the scramble signal of the same embodiment is inappropriate.

FIG. 4 is a block circuit diagram showing a second embodiment of the scramble synchronization recovery device according to the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1... Descrambler, 2... Decoder, 3... Spectrum analyzer, 4... Judgment circuit, 5... Control circuit, 6... Scramble signal generator, 7... Serial/parallel converter, 8
…table.

Claims (3)

[Claims] 1. A scrambling synchronization recovery device that newly acquires scrambling synchronization when a receiver receiving a scrambled transmission signal loses scrambling synchronization, a storage means for storing known information of the transmission signal in advance. a scramble synchronization variable control means for changing the scramble synchronization with respect to the received signal of the receiver; and a scramble synchronization variable control means that compares the information obtained from the received signal with the known information stored in the storage means and determines whether the two match. Alternatively, a scramble synchronization recovery device comprising a comparison determination means for detecting a maximum likelihood state, and a scramble synchronization selection means for stopping the change of the scramble synchronization when a match or a maximum likelihood state is detected by the means. 2. The scramble synchronization recovery device according to claim 1, wherein the known information is a transmission frequency band. 3. The scramble synchronization recovery device according to claim 1, wherein the known information is a transmission code.