JPH04324643A - Field effect type semiconductor device - Google Patents

Abstract

PURPOSE:To obtain gate-withstand voltage sufficient to practical use, and increase reliability as an element. CONSTITUTION:On a semi-insulating GaAs substrate 1, the following are formed in order; a buffer layer 2 which is composed of GaAs semiconductor and serves as a barrier layer, a channel layer 3 composed of an N-type InGaAs doped with N-type impurity of high concentration, and an undoped cap layer 10 composed of GaAs semiconductor. Two regions of the cap layer 10 are ohmic layers 11, 11 in which Si ions of high concentration are implanted. Source and drain electrodes 6, 7 are connected with the ohmic regions 11, 11, and a gate electrode 8 is connected with the undoped region of the cap layer 10.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect semiconductor device.

0002

2. Description of the Related Art As the demand for satellite broadcast receiving systems increases, attention is being focused on improving the performance of ultra-low noise field effect transistors, which are an important part of these systems. In order to improve the performance of these transistors, shortening the gate length, increasing mutual conductance, etc. are essential conditions. Therefore, a field effect transistor in which the channel layer is doped with impurities at a high concentration has been proposed.

FIG. 3 is a sectional view showing the structure of a first conventional field effect transistor. In the figure, 1 is semi-insulating G
The aAs substrate has on the substrate 1 a buffer layer 2 made of a GaAs semiconductor which also serves as a barrier layer, a channel layer 3 made of an n-type InGaAs semiconductor doped with n-type impurities at a high concentration, and an n-type AlGaAs semiconductor layer. 4, n-type GaAs
A cap layer 5 made of semiconductor is provided in this order. A source electrode 6 is connected to one side of the cap layer 5, and a drain electrode 7 is connected to the other side of the cap layer 5. Between the source electrode 6 and the drain electrode 7, n
A gate electrode 8 is provided which makes a Schottky connection to the AlGaAs type semiconductor layer 4 .

FIG. 4 is a sectional view showing the structure of a second conventional field effect transistor. In the figure, parts that are the same as those in the prior art example described above are given the same numbers and their explanations will be omitted. In this field effect transistor, a cap layer 9 made of an n-type GaAs semiconductor is provided on the channel layer 3, and a gate electrode is Schottky connected to the cap layer 9.

[0005]

[Problems to be Solved by the Invention] By the way, the gate breakdown voltage of a conventional field effect transistor in which the gate electrode is formed on an n-AlGaAs layer is about 5V, which is low for practical use. Since it is easily oxidized and electrically unstable, there is a problem that the reliability of the device is low. The present invention has been made to solve these problems, and involves doping impurities in a region of a cap layer made of a GaAs semiconductor to which a pair of electrodes are connected, while a gate electrode is connected to the cap layer. An object of the present invention is to provide a field effect semiconductor device in which a practically sufficient gate breakdown voltage is obtained by making the region of the cap layer undoped, and the device has high reliability.

[0006]

[Means for Solving the Problems] A field-effect semiconductor device of the present invention includes, on a semiconductor substrate, a buffer layer, a channel layer made of a semiconductor of one conductivity type, and a GaAs film doped with impurities in two regions. a pair of electrodes each connected to an impurity-doped region of the cap layer; and a gate electrode disposed between the electrodes and connected to an undoped region of the cap layer. It is characterized by having Further, the field effect semiconductor device of the present invention is characterized in that an undoped channel layer made of a semiconductor having a higher electron affinity than the semiconductor of the buffer layer is provided between the buffer layer and the channel layer. .

[0007]

[Function] In the field effect semiconductor device of the present invention, since the gate electrode is connected to the undoped region of the cap layer made of GaAs, the gate breakdown voltage is improved and good Schottky gate characteristics are obtained.・Since the region connected to the drain electrode is doped with impurities, sufficient source resistance can be obtained. Furthermore, since GaAs, which is difficult to oxidize, appears on the surface of the device, it is electrically stable. Further, in the field effect semiconductor device of the present invention, during device operation, electrons passing directly under the gate electrode pass through a channel layer made of an undoped semiconductor, so noise generation is suppressed.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be explained below based on drawings showing embodiments thereof. FIG. 1 is a schematic cross-sectional view showing the structure of a first embodiment of a field effect transistor according to the present invention. In the figure, 1 is a semi-insulating GaAs substrate, and there is no G
Buffer layer 2, n which also serves as a barrier layer made of aAs semiconductor
A channel layer 3 made of an n-type InGaAs semiconductor doped with type impurities at a high concentration, and an undoped cap layer 10 made of a GaAs semiconductor are provided in this order, and a part of the cap layer 10 is implanted with n+ ions at a high concentration. Ta2
There are two ohmic regions 11, 11.

A source electrode 6 is connected to one of the ohmic regions 11, 11, and a drain electrode 7 is connected to the other. Between the source electrode 6 and the drain electrode 7,
A gate electrode 8 is provided to make a Schottky connection to an undoped cap layer 10 made of a GaAs semiconductor.

FIG. 2 is a schematic cross-sectional view showing the structure of a second embodiment of a field effect transistor according to the present invention. Components that are the same as those in the first embodiment are given the same numbers and their explanations will be omitted. In this embodiment, a channel layer 12 made of an undoped InGaAs semiconductor is provided between the buffer layer 2 and the gate layer 3. The reason for this is that during operation of the field effect transistor, electrons passing directly under the gate electrode 8 pass through the channel layer 3, which is heavily doped with impurities.
This is because the generation of noise is suppressed by passing through the undoped channel layer 12 instead.

[0011] Next, Table 1 shows the details of the element structure of each sample, with the first conventional example as A, the second conventional example as B, the first embodiment as C, and the second embodiment as D. . In addition, in the table,
n is the impurity concentration, d is the film thickness, and
The molar composition is 0.22, and the In molar composition of InGaAs is 0.
．． It is 15. In addition, the undoped Ga of samples C and D
The conditions for implanting n+ ions into the As layer are implantation energy 9
0 KeV, doping amount 3×10 13 cm −2 , and short-time annealing at 850° C. for 5 seconds.

0012

[Table 1]

Field effect transistors A, B, C, and D having a gate length of 0.2 μm and a gate width of 200 μm were fabricated by growing each semiconductor layer of these samples by MBE growth, and the device characteristics of each were determined as follows. Gate current 10μ
Gate breakdown voltage at A, gate Schottky electrode (Ti/Al
ideality factor (n value) of the electrode), maximum mutual conductance (
gmmax ) and 12GHz (Vds=2V, Ids
Table 2 shows the results of comparing the minimum noise figure NFmin at 10 mA).

[0014]

[Table 2]

As is clear from Table 2, the characteristics of samples C and D of this embodiment are as follows compared to samples A and B of the conventional example.
The gate breakdown voltage and n value are improved, the maximum transconductance gmmax is increased, and the minimum noise figure NFmi is
n is reduced.

[0016]

As described above, in the field effect semiconductor device of the present invention, the gate breakdown voltage, n The device has good device characteristics in terms of value, maximum mutual conductance, and minimum noise figure, and the device has a structure in which GaAs, which is resistant to oxidation and is electrically stable, is exposed on the device surface, so it has the excellent effect of high reliability as a device. play.

[Brief explanation of the drawing]

FIG. 1 is a schematic cross-sectional view showing the structure of a first embodiment of a field effect transistor according to the present invention.

FIG. 2 is a schematic cross-sectional view showing the structure of a second embodiment of a field effect transistor according to the present invention.

FIG. 3 is a schematic cross-sectional view showing the structure of a conventional field effect transistor.

FIG. 4 is a schematic cross-sectional view showing the structure of another conventional field effect transistor.

[Explanation of symbols]

1 Semi-insulating GaAs substrate 2 GaAs 3 N-type InGaAs channel layer 6 Source electrode 7 Drain electrode 8 Gate electrode 10 GaAs cap layer 11 Ohmic region 12 InGaAs channel layer

Claims (2)

[Claims] 1. On a semiconductor substrate, a buffer layer, a channel layer made of a semiconductor of one conductivity type, and a cap layer made of GaAs doped with impurities in two regions,
A pair of electrodes each connected to an impurity-doped region of the cap layer, and a gate electrode disposed between the electrodes and connected to an undoped region of the cap layer. A field-effect semiconductor device. 2. The field effect semiconductor device according to claim 1, further comprising an undoped channel layer made of a semiconductor having a higher electron affinity than the semiconductor of the buffer layer, between the buffer layer and the channel layer.