JPH04329657A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH04329657A JPH04329657A JP3100078A JP10007891A JPH04329657A JP H04329657 A JPH04329657 A JP H04329657A JP 3100078 A JP3100078 A JP 3100078A JP 10007891 A JP10007891 A JP 10007891A JP H04329657 A JPH04329657 A JP H04329657A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- semiconductor element
- lead frame
- shielding
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【0001】0001
【産業上の利用分野】この発明は、半導体素子を電磁的
外乱信号から遮蔽するための構造を有する半導体装置お
よびその製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a structure for shielding a semiconductor element from electromagnetic disturbance signals and a method for manufacturing the same.
【0002】0002
【従来の技術】近年、電子技術の進歩は著しく、その応
用分野は民生、産業の分野を問わず拡がるとともに、様
々な機器に用いられている。また、その使用環境も様々
で、なかには電子機器及び、それを構成する半導体装置
の動作に対して極めて悪い影響を与える電磁的外乱信号
を有する環境も多く、逆に電子機器自身がその発生源と
成りうる場合も少なくない。電磁的外乱信号による影響
を防止する一つの対策として、導電性材料を用いて電子
機器自身あるいは、各半導体装置を個々に、電磁的外乱
信号から遮蔽保護する方法があげられる。BACKGROUND OF THE INVENTION In recent years, electronic technology has made remarkable progress, and its application fields are expanding to both consumer and industrial fields, and it is being used in a variety of devices. In addition, the environments in which they are used vary; some environments contain electromagnetic disturbance signals that have an extremely negative effect on the operation of electronic equipment and the semiconductor devices that make up it; on the other hand, electronic equipment itself is the source of the disturbance. There are many cases where this is possible. One measure to prevent the influence of electromagnetic disturbance signals is to shield and protect the electronic equipment itself or each semiconductor device individually from electromagnetic disturbance signals using conductive materials.
【0003】従来、この種の遮蔽器は被遮蔽物とは異な
った構成物を用い、電子機器への実装時に被遮蔽物とと
もに装着されるのが一般的で、以下、その構成について
図9および図10を参照しながら説明する。図9は従来
の半導体装置の構造を示す外観透視斜視図、図10は同
半導体装置の内部構造を示す側面断面図である。[0003] Conventionally, this type of shield uses a structure different from that of the object to be shielded, and is generally attached together with the object to be shielded when mounted on electronic equipment. This will be explained with reference to FIG. FIG. 9 is an external perspective view showing the structure of a conventional semiconductor device, and FIG. 10 is a side sectional view showing the internal structure of the semiconductor device.
【0004】図に示すごとく、従来の半導体装置は、半
導体素子1をリードフレームの半導体素子搭載部2に載
置し、半導体素子1の電極体を金属細線3によってリー
ドフレームの電極部5に電気的接続をしたのち、外囲器
4に封入し、その周囲を覆う導電性材料により形成され
た遮蔽器9が装着されている。この遮蔽器9は所定の電
位を与えられることではじめて、電磁的外乱信号を遮蔽
するという機能を有することになるが、上記構成のまま
では遮蔽器9はいずれからも電気的に絶縁されており、
目的とする遮蔽器としてまったく機能しない。所定の電
位を与えるには、半導体素子1の所定の電極体と選択的
に電気的接続をし、遮蔽器9を所定の電位に保つことが
あげられ、これは最も簡易的であるが、被遮蔽物と遮蔽
器の間の距離が最小ですむため最も効果がある接続方法
である。As shown in the figure, in the conventional semiconductor device, a semiconductor element 1 is mounted on a semiconductor element mounting part 2 of a lead frame, and an electrode body of the semiconductor element 1 is electrically connected to an electrode part 5 of the lead frame by a thin metal wire 3. After the electrical connections are made, a shield 9 made of a conductive material is enclosed in the envelope 4 and covered around it. This shielder 9 has the function of shielding electromagnetic disturbance signals only when a predetermined potential is applied to it, but with the above configuration, the shielder 9 is electrically insulated from both. ,
It does not function as the intended shield at all. In order to provide a predetermined potential, it is possible to selectively electrically connect a predetermined electrode body of the semiconductor element 1 and maintain the shield 9 at a predetermined potential.This is the simplest method, but it This is the most effective connection method because it minimizes the distance between the shield and the shield.
【0005】具体的には、半導体装置を回路基板等に実
装するうえで、リードフレームの所定の電極部5と遮蔽
器電極部10を金属ロウ材等を用い電気的に接続をする
ことで、遮蔽器9には、接続される所定の電極部5と同
じ電位が与えられることになり、電磁的外乱信号を遮蔽
するという本来の機能を果たすことになる。Specifically, when mounting a semiconductor device on a circuit board or the like, a predetermined electrode portion 5 of a lead frame and a shield electrode portion 10 are electrically connected using a metal brazing material or the like. The shield 9 is given the same potential as the predetermined electrode portion 5 to which it is connected, and fulfills its original function of shielding electromagnetic disturbance signals.
【0006】[0006]
【発明が解決しようとする課題】このような従来の半導
体装置において、遮蔽器9を機能させるためには、実装
時での電気的接続を必要とするため組み立て工数並びに
、部品点数が増すこと、また、外囲器4の外部に遮蔽器
9を設けた構造のため、装置の小型化が困難で高密度実
装には向かない等の問題があった。また、半導体素子1
は外囲器4を介して遮蔽器9と隔たることとなり、その
距離d′は半導体素子1表面からの外囲器厚により規制
されてしまう。その効果をより高めるためには、この距
離d′をできるかぎり小さくすることが不可欠となり、
外囲器厚(距離d′)が大きくなるような場合は、電磁
的外乱信号に対し十分な遮蔽効果を発揮できていないと
いう問題もあった。[Problems to be Solved by the Invention] In such a conventional semiconductor device, in order to make the shield 9 function, electrical connection is required at the time of mounting, which increases the number of assembly steps and the number of parts. Furthermore, since the shielding device 9 is provided outside the envelope 4, it is difficult to miniaturize the device, making it unsuitable for high-density packaging. In addition, the semiconductor element 1
is separated from the shield 9 via the envelope 4, and the distance d' is regulated by the thickness of the envelope from the surface of the semiconductor element 1. In order to further enhance the effect, it is essential to make this distance d' as small as possible,
When the envelope thickness (distance d') becomes large, there is also the problem that a sufficient shielding effect against electromagnetic disturbance signals cannot be exhibited.
【0007】この発明の目的は、上記問題を解決するも
ので、実装工程が簡便にすみ、安価で小型の電磁的外乱
信号に対し高い遮蔽効果を有する半導体装置およびその
製造方法を提供することである。An object of the present invention is to solve the above-mentioned problems, and to provide a semiconductor device that has a simple mounting process, is inexpensive and small, and has a high shielding effect against electromagnetic disturbance signals, and a method for manufacturing the same. be.
【0008】[0008]
【課題を解決するための手段】請求項1記載の半導体装
置は、半導体素子と、この半導体素子の表面要域を覆う
遮蔽平板とを一つの外囲器に一体的に封入している。請
求項2記載の半導体装置は、請求項1記載の半導体装置
において、遮蔽平板と半導体素子の所定の電極体とを電
気的に接続したことを特徴とする。A semiconductor device according to a first aspect of the present invention includes a semiconductor element and a shielding plate that covers a major surface area of the semiconductor element, which are integrally enclosed in one envelope. A semiconductor device according to a second aspect of the invention is characterized in that, in the semiconductor device according to the first aspect, the shielding flat plate and a predetermined electrode body of the semiconductor element are electrically connected.
【0009】請求項3記載の半導体装置の製造方法は、
第1のリードフレームに半導体素子を載置し、遮蔽平板
を有する第2のリードフレームと第1のリードフレーム
とを位置合わせし、樹脂封止することを特徴とする。The method for manufacturing a semiconductor device according to claim 3 comprises:
The present invention is characterized in that a semiconductor element is mounted on a first lead frame, and a second lead frame having a shielding flat plate and the first lead frame are aligned and sealed with resin.
【0010】0010
【作用】この発明の構成によれば、半導体素子とその表
面要域を覆う遮蔽平板とを外囲器内部に一体的に形成し
ているため、遮蔽平板を半導体素子に近接して配置する
ことができ、遮蔽平板を所定の電位に保つことにより、
半導体装置の動作に関わる電磁的外乱信号の影響は排除
され、安定で良好な動作を得ることができる。[Operation] According to the structure of the present invention, since the semiconductor element and the shielding flat plate covering the main surface area of the semiconductor element are integrally formed inside the envelope, the shielding flat plate can be placed close to the semiconductor element. By keeping the shielding plate at a predetermined potential,
The influence of electromagnetic disturbance signals related to the operation of the semiconductor device is eliminated, and stable and good operation can be obtained.
【0011】[0011]
【実施例】〔第1の実施例〕この発明の第1の実施例に
ついて図1,図2,図3および図4を参照しながら説明
する。図1はこの発明の第1の実施例の半導体装置の構
造を示す外観透視斜視図、図2は同半導体装置の内部構
造を示す側面断面図である。Embodiments [First Embodiment] A first embodiment of the present invention will be described with reference to FIGS. 1, 2, 3, and 4. FIG. 1 is an external perspective view showing the structure of a semiconductor device according to a first embodiment of the present invention, and FIG. 2 is a side sectional view showing the internal structure of the semiconductor device.
【0012】この半導体装置は、半導体素子1を導電性
接着剤等により第1リードフレームの半導体素子搭載部
2に載置し、半導体素子1の電極体を金属細線3によっ
て第1リードフレームの電極部5と電気的接続をしたの
ち、遮蔽平板(導電性材料)11を有する第2リードフ
レームとともに一体的に樹脂から成る外囲器4に封入し
、それぞれのリードフレームから下桟部7、中桟部6、
上桟部13(図3,図4参照)を切断、取り除き単体に
分離される。ここで、外囲器4の形成にはトランスファ
ーモールド法を用いている。In this semiconductor device, a semiconductor element 1 is mounted on a semiconductor element mounting portion 2 of a first lead frame using a conductive adhesive or the like, and an electrode body of the semiconductor element 1 is attached to an electrode of the first lead frame using a thin metal wire 3. After making an electrical connection with the part 5, the second lead frame having the shielding flat plate (conductive material) 11 is integrally enclosed in an envelope 4 made of resin, and from each lead frame, the lower crosspiece part 7, the middle part Pier 6,
The upper crosspiece 13 (see FIGS. 3 and 4) is cut and removed to separate into individual pieces. Here, the envelope 4 is formed using a transfer molding method.
【0013】図3および図4は同半導体装置の組み立て
工程の構成を示す斜視図である。第2リードフレームは
、第1リードフレームに載置した半導体素子1の表面を
遮蔽平板11が覆うように対向し、かつ、第1リードフ
レームの電極部5の伸長方向とは反する方向に第2リー
ドフレームの遮蔽平板電極部12が位置するよう成形金
型に挿着されるが、その位置決めは成形金型に突き出た
案内ピンと、それぞれのリードフレームの下桟部7、上
桟部13に設けた位置合わせ穴8、14によって行われ
る。また、第2リードフレームにはあらかじめ圧縮曲げ
加工が施され、遮蔽平板11を含む先端部は、半導体素
子1の表面より所定の距離d(図2)で離間するよう屈
曲させ、成形されている。但し、その距離dは金属細線
3と接触することなく、かつ、高い遮蔽効果を得るため
最小でなければならない。FIGS. 3 and 4 are perspective views showing the structure of the assembly process of the semiconductor device. The second lead frame faces the semiconductor element 1 mounted on the first lead frame so that the surface of the semiconductor element 1 is covered with a shielding flat plate 11, and the second lead frame is arranged in a direction opposite to the extending direction of the electrode portion 5 of the first lead frame. The lead frame is inserted into the mold so that the shielding plate electrode portion 12 is positioned, but this positioning is determined by guide pins protruding from the mold and provided on the lower crosspiece 7 and upper crosspiece 13 of each lead frame. This is done through the alignment holes 8, 14. Further, the second lead frame is subjected to a compression bending process in advance, and the tip portion including the shielding flat plate 11 is bent and shaped so as to be separated from the surface of the semiconductor element 1 by a predetermined distance d (FIG. 2). . However, the distance d must be the minimum in order to avoid contact with the thin metal wire 3 and to obtain a high shielding effect.
【0014】このように構成された半導体装置は、回路
基板に実装されて遮蔽平板11に所定の電位が与えられ
、遮蔽器として機能することになる。ここで、遮蔽平板
11は、遮蔽平板電極部12を介し、半導体素子1が載
置された半導体素子搭載部2を有する第1リードフレー
ム電極部5と接続される。このため半導体素子1を表裏
から挟み覆うよう所定の電位に保たれた遮蔽平板が存在
することになり、その効果はより高いものとなる。The semiconductor device constructed in this manner is mounted on a circuit board, a predetermined potential is applied to the shield plate 11, and it functions as a shield. Here, the shielding flat plate 11 is connected via the shielding flat plate electrode part 12 to the first lead frame electrode part 5 having the semiconductor element mounting part 2 on which the semiconductor element 1 is mounted. Therefore, there is a shielding flat plate maintained at a predetermined potential so as to sandwich and cover the semiconductor element 1 from the front and back, and the effect becomes even higher.
【0015】以上のように、この発明の第1の実施例に
よれば、遮蔽平板11が半導体装置の外囲器4内部に一
体的に形成され、半導体素子1の表面全要域を覆うとと
もに、その表面より物理的に可能な限り最小の距離dに
配設され、かつ、所定の電位に保たれた遮蔽平板11に
より半導体装置の動作に関わる電磁的外乱信号の影響は
排除され、安定で良好な動作を得ることができる。As described above, according to the first embodiment of the present invention, the shield plate 11 is integrally formed inside the envelope 4 of the semiconductor device, covers the entire surface area of the semiconductor element 1, and The influence of electromagnetic disturbance signals related to the operation of the semiconductor device is eliminated by the shielding plate 11, which is disposed at the minimum physically possible distance d from the surface of the shielding plate 11 and maintained at a predetermined potential. Good operation can be obtained.
【0016】〔第2の実施例〕この発明の第2の実施例
について図5,図6,図7および図8を参照しながら説
明する。図5はこの発明の第2の実施例の半導体装置の
構造を示す外観透視斜視図、図6は同半導体装置の内部
構造を示す側面断面図である。[Second Embodiment] A second embodiment of the present invention will be described with reference to FIGS. 5, 6, 7, and 8. FIG. 5 is an external perspective view showing the structure of a semiconductor device according to a second embodiment of the present invention, and FIG. 6 is a side sectional view showing the internal structure of the semiconductor device.
【0017】この半導体装置は、第1の実施例と同様、
同じ部品材料によって構成され、また、その組み立て方
法、電磁的外乱信号を遮蔽する構造に関して何ら変わる
ことなく同様の効果を有するが、第1の実施例と異なる
点は、その構造において既に第2リードフレームの遮蔽
平板(導電性材料)31が、その遮蔽平板電極部32を
介して、第1リードフレームの所定の電極部22(半導
体素子1が載置された半導体素子搭載部21を有する電
極部)と選択的に電気的接続されている点である。この
第1の実施例と異なる点について、図7および図8を参
照しながら説明する。Similar to the first embodiment, this semiconductor device has the following features.
It is made of the same parts and materials, and has the same effect in terms of its assembly method and structure for shielding electromagnetic disturbance signals. However, the difference from the first embodiment is that the second lead is already connected to the second lead in its structure. The shielding flat plate (conductive material) 31 of the frame is connected to the predetermined electrode part 22 of the first lead frame (the electrode part having the semiconductor element mounting part 21 on which the semiconductor element 1 is mounted) via the shielding flat plate electrode part 32 of the frame. ) is selectively electrically connected to the Points different from the first embodiment will be explained with reference to FIGS. 7 and 8.
【0018】図7および図8は同半導体装置の組み立て
工程の構成を示す斜視図である。第1、第2それぞれの
リードフレームの配設状態が、第1の実施例とは異なり
、第1リードフレームの電極部22の伸長方向と一致し
た方向に第2リードフレームの電極部32が位置するた
め、外囲器4を形成後、それぞれが重複することになる
。ただし、この状態ではそれぞれが面接触をするに過ぎ
ず、残る組み立て工程におき、第1、第2リードフレー
ムの下桟部24、35、中桟部23、34を切断、取り
除いたのち、外囲器4より露出したそれぞれの電極部2
2、32を金属ロウ材で被覆するよう表面処理を施すと
、それぞれは必然的に電気的接続されることとなる。
また、この表面処理は、電極部材の酸化防止、実装での
ロウ付け性向上等、製品価値を高める目的から従来より
実施されているもので、ここで、あえて用いたものでは
なく、組み立ての工数を増すものではない。最後にそれ
ぞれのリードフレームの上桟部25、36が切断、単体
に分離される。なお、26a,26bは第1リードフレ
ームの位置あわせ穴、33は不完全電極、37a,37
bは第2リードフレームの位置あわせ穴である。FIGS. 7 and 8 are perspective views showing the structure of the assembly process of the semiconductor device. The arrangement state of each of the first and second lead frames is different from that in the first embodiment, and the electrode portion 32 of the second lead frame is positioned in a direction that matches the direction in which the electrode portion 22 of the first lead frame extends. Therefore, after the envelope 4 is formed, each of them overlaps. However, in this state, they only make surface contact, and in the remaining assembly process, after cutting and removing the lower crosspieces 24, 35 and middle crosspieces 23, 34 of the first and second lead frames, the outer Each electrode part 2 exposed from the enclosure 4
When surfaces 2 and 32 are subjected to surface treatment so as to be coated with metal brazing material, they will inevitably be electrically connected to each other. Additionally, this surface treatment has traditionally been carried out for the purpose of increasing product value, such as preventing oxidation of electrode members and improving brazing properties during mounting. It does not increase the Finally, the upper rail portions 25 and 36 of each lead frame are cut and separated into individual pieces. In addition, 26a and 26b are alignment holes of the first lead frame, 33 is an incomplete electrode, and 37a and 37
b is an alignment hole of the second lead frame.
【0019】以上のように、この発明の第2の実施例に
よれば第1の実施例と同様の効果が得られることはいう
までもなく、そのうえ半導体装置の構造において既に第
2リードフレームの遮蔽平板31が第1リードフレーム
の所定の電極部22と選択的に電気的接続されているた
め、回路基板等への実装において、あえてこれらを電気
的接続する作業が必要でなく、工数の削減も可能とする
。As described above, according to the second embodiment of the present invention, it goes without saying that the same effects as the first embodiment can be obtained. Since the shielding flat plate 31 is selectively electrically connected to the predetermined electrode portion 22 of the first lead frame, there is no need to electrically connect these when mounting on a circuit board, etc., reducing the number of man-hours. Also possible.
【0020】なお、各実施例において、半導体素子1の
種別は何ら限定していないが、全ての半導体素子に関し
応用することができる。Note that in each embodiment, the type of semiconductor device 1 is not limited in any way, but the invention can be applied to all semiconductor devices.
【0021】[0021]
【発明の効果】この発明の半導体装置およびその製造方
法によれば、半導体素子の表面要域を覆い所定の電位に
保たれる遮蔽平板を半導体素子に近接して配置し、外囲
器内部に一体的に形成することにより、実装工程が簡便
にすみ、安価で小型の構造を有するとともに、電磁的外
乱信号に対し高い遮蔽効果を有し、安定で良好な動作を
得ることができる。Effects of the Invention According to the semiconductor device and its manufacturing method of the present invention, a shielding plate that covers the surface area of the semiconductor element and is maintained at a predetermined potential is placed close to the semiconductor element, and By integrally forming the device, the mounting process can be simplified, the device can have an inexpensive and compact structure, it can also have a high shielding effect against electromagnetic disturbance signals, and stable and good operation can be obtained.
【図1】この発明の第1の実施例の半導体装置の構造を
示す外観透視斜視図である。FIG. 1 is an external perspective view showing the structure of a semiconductor device according to a first embodiment of the present invention.
【図2】同半導体装置の内部構造を示す側面断面図であ
る。FIG. 2 is a side cross-sectional view showing the internal structure of the semiconductor device.
【図3】同半導体装置の組み立て工程の構成を示す斜視
図である。FIG. 3 is a perspective view showing the configuration of an assembly process of the semiconductor device.
【図4】同半導体装置の組み立て工程の構成を示す斜視
図である。FIG. 4 is a perspective view showing the configuration of an assembly process of the semiconductor device.
【図5】この発明の第2の実施例の半導体装置の構造を
示す外観透視斜視図である。FIG. 5 is an external perspective view showing the structure of a semiconductor device according to a second embodiment of the invention.
【図6】同半導体装置の内部構造を示す側面断面図であ
る。FIG. 6 is a side cross-sectional view showing the internal structure of the semiconductor device.
【図7】同半導体装置の組み立て工程の構成を示す斜視
図である。FIG. 7 is a perspective view showing the configuration of an assembly process of the semiconductor device.
【図8】同半導体装置の組み立て工程の構成を示す斜視
図である。FIG. 8 is a perspective view showing the configuration of an assembly process of the semiconductor device.
【図9】従来の半導体装置の構造を示す外観透視斜視図
である。FIG. 9 is an external perspective view showing the structure of a conventional semiconductor device.
【図10】同半導体装置の内部構造を示す側面断面図で
ある。FIG. 10 is a side cross-sectional view showing the internal structure of the semiconductor device.
1 半導体素子
2 第1リードフレーム半導体素子搭載部3
金属細線
4 外囲器
5 第1リードフレーム電極部1 Semiconductor element 2 First lead frame semiconductor element mounting section 3
Fine metal wire 4 Envelope 5 First lead frame electrode part
Claims (3)
要域を覆う遮蔽平板とを一つの外囲器に一体的に封入し
た半導体装置。1. A semiconductor device in which a semiconductor element and a shielding plate covering a major surface area of the semiconductor element are integrally enclosed in one envelope.
とを電気的に接続したことを特徴とする請求項1記載の
半導体装置。2. The semiconductor device according to claim 1, wherein the shielding flat plate and a predetermined electrode body of the semiconductor element are electrically connected.
の製造方法であって、第1のリードフレームに前記半導
体素子を載置し、遮蔽平板を有する第2のリードフレー
ムと前記第1のリードフレームとを位置合わせし、樹脂
封止することを特徴とする半導体装置の製造方法。3. A method for manufacturing a semiconductor device in which a semiconductor element is encapsulated with resin, the semiconductor element being mounted on a first lead frame, a second lead frame having a shielding flat plate and the first lead. A method of manufacturing a semiconductor device, which comprises aligning a frame with a frame and sealing the semiconductor device with a resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3100078A JP2970952B2 (en) | 1991-05-01 | 1991-05-01 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3100078A JP2970952B2 (en) | 1991-05-01 | 1991-05-01 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04329657A true JPH04329657A (en) | 1992-11-18 |
| JP2970952B2 JP2970952B2 (en) | 1999-11-02 |
Family
ID=14264413
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3100078A Expired - Fee Related JP2970952B2 (en) | 1991-05-01 | 1991-05-01 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2970952B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06254633A (en) * | 1993-03-08 | 1994-09-13 | Uchinuki:Kk | Punching machine |
-
1991
- 1991-05-01 JP JP3100078A patent/JP2970952B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06254633A (en) * | 1993-03-08 | 1994-09-13 | Uchinuki:Kk | Punching machine |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2970952B2 (en) | 1999-11-02 |
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