JPH04330827A - D/a converter circuit - Google Patents

Abstract

PURPOSE:To ensure a monotonous increase at the time of inverting a polarity by constituting a D/A converter which converts an (n+m)bit input signal into an analog signal by combining 2<n> pieces of (n) bit ladder resistance circuits. CONSTITUTION:This circuit is equipped with 2<n> pieces of (n) bit ladder resistances 11 and 12, and a logical circuit 100 which supplies an output to the (n) bit ladder resistance circuits 11 and 12 corresponding to the input signal, and the logical circuit 100 selects the operation of each (n) bit ladder resistance circuit 11 and 12 based on the upper (m) bit of the input signal. Then, when an input bit 2<n>(MSB) is '0', input 7 bits to the ladder resistance circuit 12 are all '0', and the ladder resistance circuit 12 is equivalently connected through a 2R resistance with the '0' level. And also, when the input bit 2<n>(MSB) is '1', the input 7 bits to the ladder resistance circuit 11 are all '1', the ladder resistance circuit 11 is equivalently connected through the 2R resistance with the '1' level.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a D/A converter, and more particularly to a D/A converter using a ladder resistance circuit.

0002

2. Description of the Related Art A circuit shown in FIG. 3 is used as a conventional D/A converter using resistance division. This D
/A converter is called a ladder resistance circuit, and the resistance value R
The analog output OUT is obtained from the digital inputs 20 to 27 by combining two types of resistors, 2R and 2R, and using resistance division.

FIG. 3 shows an 8-bit input D/A converter circuit, and this method connects unit resistors R1 to R256 in series for the required number of levels shown in FIG. 4, corresponding to digital inputs 20 to 27. Compared to the R-string method in which the analog level to be output is selected by a switch matrix, this method has the advantage that fewer resistive elements are required and the D/A converter can be formed with a small area.

On the other hand, although the R-string method requires a large number of unit resistance elements, it has the advantage that monotonous increase, which is essential for a D/A converter, is guaranteed in principle. Monotonicity refers to the property that as the digital input value increases, the analog output always increases, even if there is an error.

[0005] In the R-string method, as the number of input bits increases, the number of required unit resistance elements increases significantly, so a method as shown in FIG. 5 has been proposed to solve this difficulty.

FIG. 5 shows an 8-bit input D/A converter, in which a switch matrix 51 is connected for every 4 input bits.
, 52, and the required number of unit resistors R1 to 2-stage configuration.
R16, R1' to R16' are decreased. However, in this case, highly accurate buffers 53 and 54 are required. In this method, the upper 4 bits 20 to 23 of the input signal control the switch matrix 51, and the two buffers 53, 5
4, each with 16 resistor rows R1 to R16, R1' to R
The voltage passed through the buffer is further divided into 16 and selected by a switch matrix 52 controlled by the lower four bits 24 to 27.

[0007]

[Problem to be solved by the invention] The conventional D described above
In the /A converter, the R string method shown in FIG. 4 requires a large number of unit resistors, and when integrated into an IC, it has the problem that it occupies a larger area on the chip than other methods.

In the improved R string system shown in FIG. 5, buffer circuits 53, 5 with a wide input range and high accuracy
I need 4. For example, if VREF is 2.5V, in an 8-bit D/A, 1LSB is about 10mV, and if the difference in offset voltage between the two buffer circuits 53 and 54 becomes 10mV or more, monotonous increase property cannot be satisfied. have.

Further, although the ladder resistance method shown in FIG. 3 can be constructed on a relatively small area, the guarantee of monotonous increase is greatly affected by variations in the precision of the resistor.
In particular, there is a problem in that when the MSB changes, the monotonous increase is greatly affected.

[0010] The present invention uses MS in the ladder resistance method.
It is an object of the present invention to provide a D/A converter which is capable of improving the monotonous increase property when B changes, and which occupies a small area and can realize a good monotone increase property.

[0011]

[Means for Solving the Problems] The gist of the present invention is (m+n
)-bit input signal and generates an analog output signal corresponding to the input signal, the D/A converter circuit includes 2m n-bit ladder resistance circuits, and the n-bit ladder resistance circuit in response to the input signal. , and the logic circuit selects the operation of each n-bit ladder resistor circuit based on the upper m bits of the input signal.

0012

Embodiments Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a first D/A converter according to the present invention.
An example is shown. In this embodiment, two sets of 7-bit ladder resistance circuits 11 and 12, which are a combination of resistors R and 2R, are output.
and input bits 20 (LSB) to 2b and input bit 27 (MSB) are connected to 7-bit ladder resistor 11.
The logical product output of these input bits is applied to the 7-bit ladder resistor 12, and the logical sum output of these input bits is applied to the 7-bit ladder resistor 12, respectively. The AND circuit and the OR circuit collectively represent a logic circuit 100.

In the first embodiment configured as described above, when the input bit 27 (MSB) is "0", all 7 bits input to the ladder resistance circuit 12 become "0", and the ladder resistance circuit 12 is equivalently connected to the “0” level through a 2R resistor, and the conventional D in FIG.
This is equivalent to input 27 (MSB) being "0" in the /A converter.

In the D/A converter shown in FIG. 1, when the input 27 (MSB) is "1", the ladder resistor circuit 1
All 7 bits input to 1 become "1", and the ladder resistor circuit 2 is equivalently connected to the 1 level via 2R. This is equivalent to 27 (MSB) being 1. Therefore, the operation is the same as that of the conventional ladder resistance circuit shown in FIG. However, in the case of the conventional D/A converter shown in Figure 3, the input is "(MSB) 01111111 (LSB
)" to "(MSB) 10000000 (LSB)", the polarity of the resistor to which the inputs 20 to 26 are applied changes from 1 to 0, and the polarity of the resistor to which the input to input 27 is applied changes from 0 to 1, the accuracy of variations in these resistances, particularly the accuracy of variations in the resistance to which the input to the input 27 is applied, greatly affects the output voltage.

On the other hand, in the case of the D/A converter of this embodiment, even when the input signal changes in the same way, the phenomenon in which the polarities applied to each resistor are all reversed does not occur, and the monotonous increase property is maintained. Never crumbles. Differences in operation from such a conventional example are schematically shown in FIG. 6 (this embodiment) and FIG. 7 (prior art example). 6 and 7, state 1 is the input signal (011
11111) is being supplied, and in the above bit string, "0" indicates the MSB. Also,
State 2 indicates a state in which the input signal (10000000) is supplied, and "1" is the MSB. In the figure ()
The bits marked with are inverted when changing from state 1 to state 2.

FIG. 2 shows a 2-bit ladder resistance circuit 200,
A second embodiment of the present invention is shown in which four bits 201, 202, and 203 are combined to form a 4-bit D/A converter. These ladder resistance circuits 200 to 203 are controlled by a logic circuit 204. Similarly, an 8-bit D/A converter can be constructed by combining four 6-bit ladder resistance circuits. In this case, it is possible to guarantee monotonous increase in the upper two bits when the bits are inverted.

[0017]

Effects of the Invention As explained above, in the present invention, a D/A converter that converts an (n+m) bit input signal into an analog signal is configured by combining 2m n-bit ladder resistor circuits. For m bits, it is possible to guarantee monotonous increase when the polarity is reversed.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a first embodiment.

FIG. 2 is a circuit diagram showing a second embodiment.

FIG. 3 is a circuit diagram of a conventional example.

FIG. 4 is a circuit diagram of another conventional example.

FIG. 5 is a circuit diagram showing still another conventional example.

FIG. 6 is a schematic diagram showing the operation of the first embodiment.

FIG. 7 is a schematic diagram showing the operation of the conventional example shown in FIG. 3;

[Explanation of symbols]

11, 12 Ladder resistance circuit R, 2R Resistance element 100,204 Logic circuit

Claims (1)

[Claims] Claim 1: A D/A converter circuit that is supplied with an (m+n) bit input signal and generates an analog output signal corresponding to the input signal, comprising: 2m n-bit ladder resistor circuits; and a logic circuit that supplies an output to the n-bit ladder resistance circuit, the logic circuit selecting the operation of each n-bit ladder resistance circuit based on the upper m bits of the input signal.
converter circuit.