JPH0433100B2 - - Google Patents

Description

[Detailed Description of the Invention] (Structure of conventional example and its problems) Conventionally, cathode ray tubes have been mainly used as display elements for displaying color television images. It was impossible to create a thin television receiver with such a long depth. In addition, EL display elements, plasma display devices, liquid crystal display elements, etc. have recently been developed as flat display elements.
All of them are insufficient in terms of performance such as brightness, contrast, and color display, and have not yet been put into practical use.

Therefore, in order to achieve a flat display device using electron beams, the present applicant filed a patent application in 1983-
No. 20618 (Japanese Unexamined Patent Publication No. 135590/1983) proposed a new display device.

This method generates an electron beam for each section when the screen is vertically divided into multiple sections, and displays multiple lines by deflecting each electron beam vertically for each section. However, it displays the television image as a whole.

First, a basic configuration example of the image display element used here will be explained with reference to FIG.

This display element is arranged in order from the back to the front.
A back electrode 1, a line cathode 2 as a beam source, vertical focusing electrodes 3, 3', a vertical deflection electrode 4, a beam flow control electrode 5, a horizontal focusing electrode 6, a horizontal deflection electrode 7, a beam accelerating electrode 8, and a screen 9 are arranged. These are housed in the evacuated interior of a flat glass bulb (not shown). A line cathode 2 serving as a beam source is stretched horizontally so as to generate an electron beam distributed linearly in the horizontal direction, and a plurality of line cathodes 2 (here, Only four (2A to 2D are shown) are provided. In this example, it is assumed that 15 are provided. Let's call them 2i~2yo. These line cathodes 2 are, for example, 10~
It consists of an oxide cathode material for thermionic emission coated on the surface of a 20 μφ tungsten wire. These line cathodes 2I to 2Y are heated so as to generate a thermionic beam when a current is passed through them, and as described later, the line cathodes 2
The electron beams are controlled to be emitted sequentially from A to A for a fixed period of time. The back electrode 1 suppresses generation of electron beams from line cathodes 2 other than the line cathode 2 controlled to emit electron beams for a certain period of time,
It also functions to push out the generated electron beam only in the forward direction. The back electrode 1 may be formed by a coating of a conductive material applied to the inner surface of the rear wall of the glass bulb. Further, instead of the back electrode 1 and the linear cathode 2, a planar electron beam emitting cathode may be used.

The vertical focusing electrode 3 is a conductive plate 11 having a horizontally long slit 10 facing each of the line cathodes 2I to 2Y, and extracts the electron beam emitted from the line cathode 2 through the slit 10, and focus in a direction. An electron beam for one horizontal line (360 pixels) is extracted at the same time. In the figure, only one section in the horizontal direction is shown. The slit 10 may be provided with crosspieces at appropriate intervals in the middle, or may be substantially configured as a slit by a row of through holes arranged horizontally at small intervals (nearly touching intervals). may have been done. The vertical focusing electrode 3' is also similar.

A plurality of vertical deflection electrodes 4 are arranged horizontally in the middle of each of the slits 10, and are each composed of conductors 13 and 13' provided on the upper and lower surfaces of an insulating substrate 12. has been done. And the opposing conductors 13, 13'
A vertical deflection voltage is applied between them to deflect the electron beam in the vertical direction. In this example, the electron beam from one line cathode 2 is vertically deflected to 16 line positions by a pair of conductors 13, 13'. The 16 vertical deflection electrodes 4 constitute 15 pairs of conductors corresponding to each of the 15 line cathodes 2, and the electron beams are ultimately drawn so as to draw 240 horizontal lines on the screen 9. deflect.

Next, the control electrodes 5 are composed of conductive plates 15 each having a vertically long slit 14, and a plurality of control electrodes 15 are arranged in parallel in the horizontal direction at predetermined intervals. In this embodiment, 180 conductive plates 15a to 15n for control electrodes are provided (only nine are shown in the figure). Each of the control electrodes 5 separates and extracts the electron beam into two picture elements in the horizontal direction, and controls the amount of electron beam passing therethrough in accordance with a video signal for displaying each picture element. Therefore, the conductive plates 15a to 15n for the control electrode 5 are
With this arrangement, 360 pixels can be displayed per horizontal line. In addition, in order to display images in color, each picture element is displayed with phosphors of three colors, R, G, and B, and each control electrode 5 has two picture elements of R, G, and B. Each video signal is added sequentially. In addition, 180 conductive plates 15a to 15n for control electrodes 5
180 sets of video signals for one line (two picture elements per set) are simultaneously applied to each of the lines, and one line of video is displayed at one time.

The horizontal focusing electrode 6 is composed of a conductive plate 17 having a plurality of vertically long slits 16 (180 slits 16) facing the slits 14 of the control electrode 5, and collects electrons for each picture element divided in the horizontal direction. Each beam is focused horizontally into a narrow electron beam.

The horizontal deflection electrode 7 is made up of a plurality of conductive plates 18, 18' arranged vertically on both sides of the slit 16, and each electrode 18, 18' has six levels of horizontal deflection. A voltage is applied to horizontally deflect the electron beam for each pixel, and on the screen 9 two sets of R,
The G and B phosphors are sequentially irradiated to emit light. In this example, the deflection range is two picture elements wide for each electron beam.

The accelerating electrode 8 is composed of a plurality of conductive plates 19 arranged horizontally in the same arrangement as the vertical deflection electrode 4, and accelerates the electron beam so that it collides with the screen 9 with sufficient energy.

The screen 9 is constructed by applying a phosphor 20, which emits light when irradiated with an electron beam, to the back surface of a glass plate 21, and adding a metal back layer (not shown). The phosphor 20 is arranged for each slit 14 of the control electrode 5, that is, for each horizontally divided electron beam.
Two pairs of phosphors in each of the three colors R, G, and B are provided, and are applied in stripes in the vertical direction. In FIG. 1, the broken lines drawn on the screen 9 indicate divisions in the vertical direction that are displayed corresponding to each of the plurality of line cathodes 2, and the two-dot chain lines correspond to each of the plurality of control electrodes 5. Indicates the horizontal division displayed. As shown in the enlarged view in Fig. 2, one section partitioned by these two has R, G, and B phosphors 20 for two pixels in the horizontal direction, and 16 lines in the vertical direction. It has a wide range.
For example, the size of one section is 1 in the horizontal direction.
mm, and the vertical direction is 10 mm.

Note that in FIG. 1, the length in the horizontal direction is greatly enlarged relative to the length in the vertical direction for clarity.

Further, in this example, one control electrode 5, that is, one
R, G, B phosphors 20 for the electron beam of the book
Although only one unit for two picture elements is provided, of course, one picture element or three or more picture elements may be provided, and in that case, the control electrode 5 is provided with one picture element or for three picture elements or more. R, G, and B video signals are sequentially applied, and horizontal deflection is performed in synchronization with the R, G, and B video signals.

Next, the basic configuration of a drive circuit for displaying television images on this display element will be explained with reference to FIG. First, a driving portion for irradiating the screen 9 with an electron beam to emit raster light will be described.

The power supply circuit 22 is a circuit for applying a predetermined bias voltage (operating voltage) to each electrode of the display element,
-V ₁ to the back electrode 1, and -V 1 to the vertical focusing electrodes 3 and 3'.
DC voltages of V ₃ , V ₃ ', V ₆ to the horizontal focusing electrode 6, V ₈ to the accelerating electrode 8, and V ₉ to the screen 9 are applied.

Next, a composite video signal of a television signal is applied to the input terminal 23, and a synchronization separation circuit 24 separates and extracts a vertical synchronization signal V and a horizontal synchronization signal H.

The vertical deflection drive circuit 40 includes a vertical deflection counter 25, a memory 27 for storing vertical deflection signals, and a digital-to-analog converter 39 (hereinafter referred to as a DA converter). As input pulses to the vertical deflection drive circuit 40, a vertical synchronizing signal V and a horizontal synchronizing signal H shown in FIG. 4 are used. The vertical deflection counter 25 (8 bits) receives the vertical synchronization signal V.
The horizontal synchronizing signal H is counted. This vertical deflection counter 25 counts the effective scanning period (here, a period of 240 hours) excluding the vertical retrace period of the vertical period,
This count output is supplied to an address in memory 27. The memory 27 outputs vertical deflection signal data (here, 8 bits) corresponding to each address, and the D-A converter 39 outputs the data of the vertical deflection signal as shown in FIG.
It is converted into a vertical deflection signal of V′. In this circuit
There is a memory address that stores the vertical deflection signal corresponding to each line of 240H, and by storing regular data in the memory every 16H, it is possible to obtain 16 levels of vertical deflection signals.

On the other hand, the line cathode drive circuit 26 receives the vertical synchronization signal V
Using the output of the vertical deflection counter 25, line cathode drive pulses I to Y are created. FIG. 5a shows the relationship between the vertical synchronizing signal V, the horizontal synchronizing signal H, and the lower five bits of the vertical deflection counter 25. FIG. 5b shows a method of creating line cathode drive pulses 1' to 16' every 16H using these signals. In Figure 5,
LSB indicates the lowest bit, and (LSB+1) means the bit one higher than the LSB.

The first line cathode drive pulse I' consists of the vertical synchronizing signal V and the output of the vertical deflection counter 25 (LSB+
4) can be created using an R-S flip-flop, etc., and the line cathode drive pulses LO' to YO' can be created using a shift register, and the line cathode drive pulses LO' to YO' are output from the vertical deflection counter 25 (LSB+3).
It can be obtained by using the inverted version of the clock as a clock and transmitting it. These drive pulses I'~Yo' are inverted and made low potential only during each pulse period, and converted into line cathode drive pulses I~Yo that are at a high potential of about 20 volts during other periods, and each line cathode 2 I~
Added to 2yo.

Each line cathode 2i to 2yo is heated by a current flowing through it during the high potential period of the drive pulses I to YO, and the heated state is maintained so that electrons can be emitted during the low potential period of the drive pulses I to YO. Ru. As a result, electrons are emitted from the 15 line cathodes 2i to 2yo only during the 16H period when low-potential drive pulses are applied to each of them. During the period when a high potential is applied, the potential at the line cathode 2 is lower than the potential at the position of the line cathode 2 determined by the bias voltage applied to the back electrode 1 and the vertical focusing electrode 3. Since the applied high potential becomes positive, no electrons are emitted from the line cathodes 2I to 2Y. Thus, in the line cathode 2, electrons are sequentially emitted from the upper line cathode 2a toward the lower line cathode 2y every 16H period during the effective vertical scanning period.

The emitted electrons are pushed forward by the back electrode 1, pass through the opposing slits 10 of the vertical focusing electrode 3, and are focused in the vertical direction to form a flat electron beam.

Next, the relationship between the line cathode drive pulses I to Y and the vertical deflection signals V and V' will be explained with reference to FIG. FIG. 6a is a waveform diagram of a line cathode pulse, b is a waveform diagram of a vertical deflection signal, and FIG. 6c is a waveform diagram of a horizontal deflection signal. The vertical deflection signals V and V' in FIG. 6b change in 16 steps by 1H during the 16H period of each line cathode pulse E to Y in FIG. 6A. Vertical deflection signal V
and V' both have a center voltage of _V4 , and are configured to change in opposite directions so that V increases sequentially and V' decreases sequentially. These vertical deflection signals V and V' are applied to the vertical deflection electrode 4, respectively.
As a result, the electron beams generated from the respective line cathodes 2a to 2o are vertically deflected in 16 steps, and as mentioned earlier, one beam is applied to the screen 9. The electron beam is deflected to draw a 16-line raster one line at a time, starting from the top.

As a result of the above, an electron beam is emitted for a period of 16 hours from the top of the 15 line cathodes 2A to 2Y, and each electron beam is sequentially emitted for one line from the top to the bottom within 15 sections in the vertical direction. As a result, the electron beam is vertically deflected one line at a time on the screen 9 from the first line at the top end to the 240th line at the bottom end, thereby drawing a raster of 240 lines in total.

The electron beam thus vertically deflected is horizontally deflected by 180 degrees by the control electrode 5 and the horizontal focusing electrode 6.
It is divided into sections and taken out. Figure 1 shows one of these categories. The amount of electron beam passing through each section is controlled by a control electrode 5, and horizontally focused by a horizontal focusing electrode 6 into a single narrow electron beam, which is then controlled by horizontal deflection means described below. The light is then deflected in six steps in the horizontal direction and is sequentially irradiated onto each of the R, G, and B phosphors 20 corresponding to two picture elements on the screen 9. FIG. 2 shows the vertical and horizontal divisions. The phosphors corresponding to each of 15a to 15n of the control electrode 5 are R, G, and B for two picture elements, but for convenience of explanation, one picture element is
Let R ₁ , G ₁ , B ₁ be R ₂ , G ₂ , B ₂ .

The horizontal deflection drive circuit 41 includes a horizontal deflection counter (11 bits), a memory 29 storing horizontal deflection signals, and a DA converter 38. The input pulse to the horizontal deflection drive circuit 41 is synchronized with the vertical synchronizing signal V and the horizontal synchronizing signal H, as shown in FIG. 7, and uses a pulse 6H having a repetition frequency six times that of the horizontal synchronizing signal H.

The horizontal deflection counter 28 is reset by the vertical synchronizing signal V and counts horizontal six times pulses 6H. This horizontal deflection counter 28 is
6 times during 1H, 240H x 6/H = 1440 during 1V
The count output is supplied to an address in the memory 29. Horizontal deflection signal data (here, 8 bits) corresponding to the address is output from the memory 29, and converted by the D-A converter 38 into horizontal deflection signals such as h and h' shown in FIG. . This circuit has a memory address for storing horizontal deflection signals corresponding to each of 6 x 240 lines, and by storing 6 pieces of regular data for each line in the memory, 6 levels of data are stored in 1H period. horizontal deflection signals can be obtained.

This horizontal deflection signal is a pair of horizontal deflection signals h and h' that change in 6 steps as shown in FIG. 7, both have a center voltage of V ₇ , and h gradually decreases.
h' increases in sequence and changes in opposite directions. These horizontal deflection signals h, h' are applied to electrodes 18 and 18' of the horizontal deflection electrode 7, respectively.
As a result, each of the horizontally divided electron beams is transmitted to the R, G, B of the screen 9 during each horizontal period.
It is horizontally deflected so that R, G, and B (R ₁ , G ₁ , B ₁ , R ₂ , G ₂ , B ₂ ) phosphors are sequentially irradiated with H/6 each. Thus, in each line raster, the electron beam is R ₁ ,
Each phosphor 20 of G ₁ , B ₁ , R ₂ , G ₂ , and B ₂ is irradiated in sequence.

Therefore, an electron beam is applied to each horizontal section of each line.
A color television image can be displayed on the screen 9 by modulating the video signals R ₁ , G ₁ , B ₁ , R ₂ , G ₂ , and B ₂ .

Next, the modulation control portion of the electron beam will be explained.

First, the composite video signal applied to the television signal input terminal 23 is applied to the color demodulation circuit 30, where the R-Y and B-Y color difference signals are demodulated and the G
-Y color difference signals are matrix-synthesized, and further,
These are combined with the luminance signal Y, and R, G, and B primary color signals (hereinafter referred to as R, G, and B video signals) are output. Those R, G, and B video signals are
180 sample and hold circuit sets 31a to 31n
added to. Each sample and hold circuit set 31a
~31n are for R ₁ , G ₁ , B ₁ , R ₂ , respectively.
It has 6 sample and hold circuits for G ₂ and B ₂ . These sample and hold outputs are respectively applied to holding memory sets 32a-32n.

On the other hand, the reference clock oscillator 33 is constituted by a PLL (phase locked loop) circuit or the like, and in this example generates a reference clock 6f _sc that is six times as large as the color subcarrier f _sc and a reference clock 2f _sc that is twice the color subcarrier f sc.
The reference clock is controlled to always have a constant phase with respect to the horizontal synchronizing signal H. The reference clock _fsc is added to the deflection pulse generation circuit 42, which generates a signal 6H which is six times the horizontal synchronizing signal H and signal switching pulses r ₁ , g ₁ , b ₁ , r ₂ , g ₂ , b every H/6. I'm getting ₂ pulses. On the other hand, the reference clock 6f _sc is applied to the sampling pulse generation circuit 34, where it is delayed by one clock period by a shift register, and is thus applied to the effective horizontal scanning period (approximately 50 μsec) of the horizontal period (63.5 μsec). In the meantime, 1080 sampling pulses R _a1 to B _o2 are sequentially generated, and then one transfer pulse t is generated. These sampling pulses R _a1 to B _o2 correspond to each picture element when one line of the video to be displayed is divided into 360 picture elements in the horizontal direction, and their positions are always constant with respect to the horizontal synchronization signal H. controlled so that

Each of these 1080 sampling pulses R _a1 to B _o2 is connected to 180 sets of sampling hold circuit set 3.
1a to 31n, and as a result, each sample hold circuit group 31a to 31n has 2 of each when one line is divided into 180 circuits.
Each picture element's R ₁ , G ₁ , B ₁ , R ₂ , G ₂ , and B ₂ video signals are individually sampled and held. The sample held 180 pairs of R ₁ , G ₁ , B ₁ ,
The video signals of R ₂ , G ₂ , and B ₂ are stored in 180 sets of memories 32a to 32n after completing the sample hold for one line.
are transferred all at once by a transfer pulse t, and held here for the next horizontal period. This held
The signals R ₁ , G ₁ , B ₁ , R ₂ , G ₂ , and B ₂ are applied to switching circuits 35a to 35n. The switching circuits 35a to 35n each have R ₁ , G ₁ , B ₁ ,
It is composed of a tri-state or analog gate having individual input terminals for R ₂ , G ₂ , and B ₂ and a common output terminal that sequentially switches and outputs them.

The output of each switching circuit 35a to 35n is
180 sets of pulse width modulation (PWM) circuits 37a to 3
7n, and here, the reference pulse signal is pulse width modulated according to the magnitude of the sampled and held R ₁ , G ₁ , B ₁ , R ₂ , G ₂ , B ₂ video signals and is output. It is desirable that the repetition period of the reference pulse signal is sufficiently smaller than the pulse width of the signal switching pulses r ₁ , g ₁ , b ₁ , r ₂ , g ₂ , b ₂ , for example, 1:10 to 1:1. A ratio of about 1:100 is used.

The output of the pulse width modulation circuits 37a to 37n is used as a control signal for modulating the electron beam to the 180 conductive plates 15a to 15 of the control electrode 5 of the display element.
n separately. Each of the switching circuits 35a to 35n receives a switching pulse r ₁ applied from the switching pulse generation circuit 36,
Switching is controlled simultaneously by g ₁ , b ₁ , r ₂ , g ₂ , and b ₂ . The switching pulse generation circuit 36 generates a signal switching pulse from the deflection pulse generation circuit 42 mentioned above.
controlled by r ₁ , g ₁ , b ₁ , r ₂ , g ₂ , b ₂ ,
Each horizontal period is divided into six, and the switching circuits 35a to 35n are switched by H/6, and R ₁ , G ₁ , B ₁ ,
Switching signals r _{1 ,} g _{1 ,} b ₁ , r ₂ , b _{2 ,} g ₂ occurs.

What should be noted here is that the switching circuit 3
R ₁ , G ₁ , B ₁ , R ₂ , G ₂ , B ₂ in 5a to 35n
video signal supply switching and horizontal deflection drive circuit 4
The horizontal deflection of the electron beams R ₁ , G ₁ , B ₁ , R ₂ , G ₂ , and B ₂ irradiated onto the phosphor by 1 is synchronously controlled so that they completely match both in timing and order. It is that you are. As a result, when the electron beam is irradiating the R ₁ phosphor, the amount of the electron beam is controlled by the R ₁ video signal, and also for G ₁ , B ₁ , R ₂ , G ₂ , and B ₂ . Similarly controlled, R ₁ , G ₁ , B ₁ , R ₂ , G ₂ ,
B ₂ The emission of each phosphor is caused by the R ₁ , G ₁ , B ₁ ,
Each picture element is controlled by the R ₂ , G ₂ , and B ₂ video signals, and each picture element is displayed by emitting light according to the input video signal. Such control is performed simultaneously for 180 sets of one line (2 picture elements each) to display an image of 360 picture elements for one line, and then sequentially for 240 minutes of lines starting from the upper line. One image will be displayed.

The above operations are repeated for each field of the input television signal, and as a result,
The screen 9 is similar to a normal television receiver.
The television footage of the video is shown above.

By the way, in the image display device of the example described above, the line cathodes provided corresponding to each vertical section are driven in the following manner. Below, the 8th
One of the plurality of line cathodes will be explained with reference to the drawings. In Fig. 8a, the line cathode 2 has one end A
In order to flow a heating current from the transistor to the other end B,
Q ₁ is made conductive, transistor Q ₂ is turned off, power supply 51 (V _K ) is applied to A, and current flows to A-B-power supply 53 (V _G ) through diode Q ₃ (8th
period T ₄ in figure b). While this current is flowing, the wire cathode 2 is heated and accumulates thermoelectrons. next,
When transistor _Q1 is cut off, transistor _Q2 is made conductive, and point A is brought to the potential of the power supply 52 (-V _K '), transistor _Q3 is cut off under the condition (V _G ) > (-V _K '). The potential between A and B is maintained at approximately (-V _K ') (period _T5 in FIG. 8b). Therefore, the back electrode 1 in FIG. 8c is set to −V _K ′
Lower electron extraction electrode (vertical focusing electrode)
3 is higher than (-V _K ′) and lower than (+V _K ), thermionic electrons are emitted from the wire cathode 2 toward the electron extraction electrode 3 only when the wire cathode 2 has a potential of (−V _K ′). be done. In other words, in Fig. 8a, current flows toward the line cathode 2 as shown by the arrow, and the transistor
It is recovered to the power source 52 through _Q2 .
Therefore, currents with different current densities flow between A and B during that time, resulting in a superimposed potential difference at both ends (-V _K '), which causes a difference in the electric field to the electron extraction electrode of the wire cathode, causing problems in the image. For example, since the velocity of electrons incident on the vertical deflection plate 4 located behind the electron extraction electrode, ie, the vertical focusing electrode 3, differs, the deflection width naturally differs, causing vertical deflection distortion on the screen.

(Object of the invention) The present invention solves these problems,
An object of the present invention is to provide an image display device capable of reproducing faithful images by reducing the potential difference at a line cathode.

(Structure of the Invention) In order to achieve the above object, the present invention provides an image display device having a line cathode which is a thermionic emission source as described above. A second switching element for connecting the switching element and a second power source that provides a low potential is connected, and a first diode for flowing a heating current is connected to the other end of the same line cathode. Either connect a third switching element for connecting to a second power source that provides a low potential to the other end, or connect a second diode in parallel with the line cathode so that one end of the line cathode becomes the cathode. By supplying emitted electrons, that is, collecting current at both ends of the line cathode, the difference in initial speed of the electron flow emitted from the line cathode is reduced, thereby reducing vertical deflection distortion. It is possible to reproduce images with less fidelity.

(Description of Examples) Examples of the present invention will be described below with reference to the drawings.
In the embodiment shown in FIG. 9, a diode Q ₄ is connected to the line cathode 2.
are connected in parallel as shown in the figure, and during heating they are reverse biased and do not conduct, but during electron emission, when the value of V _B (potential at point B) - V _A (potential at point A) exceeds the threshold value. It is designed to conduct and collect current from point B as well. In addition, in the embodiment shown in FIG. 10, the transistor Q ₅ is connected as shown, and in synchronization with the period T ₅ of FIG. 8b, the transistors Q ₂ ,
The same effect can be obtained by switching _Q5 .

In this way, the vertical deflection distortion (difference between both ends of the deflection width) on the screen is reduced to 1/4, and since it appears symmetrically, a large uniform effect is produced.

(Effects of the Invention) As described above, according to the present invention, an image display device capable of reproducing faithful images with less vertical deflection distortion can be obtained.

[Brief explanation of drawings]

FIG. 1 is an exploded perspective view showing an example of an image display element used in an image display device according to an embodiment of the present invention, FIG. 2 is an enlarged view of the fluorescent surface of the image display element, and FIG. 3 is an image of the image display device. Block diagrams of drive circuits for driving display elements, FIGS. 4, 5, 6,
FIG. 7 is a waveform diagram of each part for explaining the operation of the drive circuit, and FIG. 8a is a circuit diagram showing the configuration of a conventional example of the line cathode drive circuit of the drive circuit.
8b and 8c are waveform diagrams and electrode configuration diagrams for explaining the operation of FIG. 8a, FIG. 9 is a circuit diagram of a main part of an image display device according to an embodiment of the present invention, and FIG. FIG. 7 is a circuit diagram of a main part of another embodiment of the device. 2, 2 I to 2 Y... Line cathode, 4... Vertical deflection electrode, 5... Beam flow control electrode, 7... Horizontal deflection electrode, 9... Screen, 10... Slit, 20
... Fluorescent body, 23 ... Input terminal, 24 ... Synchronization separation circuit, 25 ... Vertical deflection counter, 26 ...
...Line cathode drive circuit, 27...Memory, 28...Horizontal deflection counter, 29...Memory, 30...
Color demodulation circuit, 31a to 31n...Sample hold circuit, 32a to 32n...Memory, 33...Reference clock oscillator, 34...Sampling pulse generation circuit, 35a to 35n...Switching circuit, 36...Switching pulse generation circuit, 37
a to 37n...PWM circuit, 38...D/A converter, 39...D/A converter, 40...Vertical deflection drive circuit, 41...Horizontal deflection drive circuit, 42...Deflection pulse generation circuit .

Claims (1)

[Claims] 1. A line cathode that is a thermionic emission source and the line cathode are time-divisionally alternated into a heating period in which the line cathode is kept at a high potential and an electron emission period in which it is kept at a low potential. a first switching element for connecting a heating power source and a second power source for applying a low potential during an electron emission period to one end of the line cathode; connect the second switching elements for each,
A first diode for flowing a heating current is connected to the other end of the line cathode, and a third switching element is connected to the other end for connecting a second power source that provides a low potential during electron emission. or a second diode is connected in parallel with the line cathode so that one end of the line cathode serves as the cathode.