JPH0433147U - - Google Patents

Description

[Brief explanation of the drawing]

Fig. 1 is a connection block diagram of a clock-synchronized serial I/O of a serial transmitting/receiving device that is an embodiment of this invention, and Fig. 2 shows the timing of 8-bit data transmission/reception operations in the serial I/O of Fig. 1. Waveform diagram, Figure 3 is a connection block diagram during full-duplex data communication operation in serial I/O of a conventional serial transmitting/receiving device, Figure 4 is a connection block diagram for serial I/O in Figure 3.
FIG. 4 is a timing waveform diagram during full-duplex data communication operation of bit data. In the figure, 1 is microcomputer A, 2 is microcomputer B
shows. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Scope of utility model registration request] A clock having an SRDY terminal that outputs an SRDY signal indicating a state in which transmission and reception are possible, a serial data input/output terminal for transmitting and receiving serial data, and an SCLK terminal for outputting or inputting a clock signal to indicate the valid period of serial data. In a synchronous serial transmitter/receiver circuit, the input/output direction of the data input/output terminal is switched every cycle in synchronization with the first clock signal during one transmission or reception, so that serial data transmission and reception can be performed at the data input/output terminal 1. A serial transmitter/receiver that is characterized by being realized in a book.