JPH04332884A - programmable logic device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable logic device (PLD), which is a semiconductor device whose logic operation can be programmed, and particularly to a test mechanism for pass transistors for signal transmission.

0002

2. Description of the Related Art With the rapid progress of digital processing technology and semiconductor technology in recent years, digital processing has been adopted for various types of processing, and its logic circuits have come to be constructed using semiconductor devices. However, when using semiconductor devices, it is necessary to mass produce them in consideration of production efficiency, and it is important to make one device highly versatile. Therefore, according to user requirements,
Programmable logic devices (PLDs) whose operations can be configured have been proposed and are becoming widely used.

[0003] In this PLD, by initializing the same intermediate product (for example, processing such as burning a program), it is possible to set the logic in that product. In order to improve the versatility and design efficiency of such PLDs, a large number of unit cells with the same structure are provided, the logic within these unit cells is set, and the signals to each unit cell are set. Switches provided on the input/output paths of the PLD are set to predetermined values to achieve desired signal processing of the entire PLD.

[0004] Here, pass transistors are often arranged on the input/output paths of signals to each unit. That is, as shown in FIG. 4, a pass transistor 70 is provided on a signal line that is an input/output path of the unit cell, and this pass transistor 70 controls the transmission of signals to the unit cell.

[0005] In such a PLD as well, as with normal semiconductor devices, it is necessary to test whether the product functions normally. This test is performed based on whether the state of the input signal and the state of the output signal are in a predetermined relationship.

A typical circuit in a PLD has a plurality of transistors connected in series between a power source and ground, and the intermediate portion serves as an output. Therefore, most of the failures are caused by the signal line being fixed at H or L. For this reason, the circuit is tested by examining the state of the output signal relative to the state of the control signal to the transistor.

[0007]

However, as shown in the failure table of FIG. 5, failures in the pass transistor 70 could not be sufficiently detected by such tests.

That is, when the signal Q supplied to the gate of the pass transistor 70 is L, the pass transistor 70 is in an off state, and the output signal line Y must be in high impedance (Hi-Z). . Therefore, it is necessary to test whether the signal line is in a high impedance state. In order to detect this high impedance state, the potential on the output signal line must be detected immediately after the pass transistor 70 is turned off.

On the other hand, the time required for testing is required to be as short as possible. Therefore, a large number of pass transistors 7
0 can be turned on and off at the same time, and the state of the output signal line can be captured immediately after turning off.

However, in the conventional setting of data to the configuration memory for setting the on/off of the pass transistor 70, the control section sequentially reads the on/off setting data for all the configuration memories stored in the ROM, and then transmits the serial signal. This is done by sending the data to all configuration memories and storing it there, and it takes about several tens of milliseconds to set the data to the configuration memory once. Therefore, the data in each configuration memory is changed at different timings, and the states of the output signal lines are required to be captured at different timings.

However, the number of signal input terminals is limited;
It has been difficult to capture the states of a large number of output signal lines all at different timings. Therefore, with conventional methods, it is not possible to reliably test whether the signal line is in a high impedance state, and it is not possible to sufficiently test the switch that connects the unit cell and the signal line. There was a problem.

The present invention has been made to solve the above problems, and provides a PLD that uses a logic circuit instead of a pass transistor and can easily test a signal non-transmission state. The purpose is to

[0013]

[Means for Solving the Problem] The present invention selects a plurality of unit cells, each of which performs a predetermined unit logic operation, and a plurality of input signal lines specified by selection information, and each unit cell A programmable logic device comprising: a plurality of switch means connected to the
The switch means includes a plurality of main signal AND circuits to which one input signal line and a selection information input line that transmits selection information about the input signal line are respectively input, and outputs of the plurality of AND circuits to which the outputs of the plurality of AND circuits are input. An OR circuit for the main signal, an OR circuit for selection information into which the selection information input line input to all the multiple AND circuits is input, and an OR circuit for selection information that is provided corresponding to the input signal line and connected to the signal line. A first auxiliary signal line is inputted with an auxiliary signal line indicating whether data is being transmitted in the preceding switch means.
The present invention is characterized in that it includes an AND circuit, and a second AND circuit for auxiliary signals into which the outputs of the OR circuit for selection information and the OR circuit for auxiliary signals are input.

[0014]

[Operation] As described above, according to the programmable logic device of the present invention, the switch for controlling the transmission/non-transmission of a signal is configured with a logic circuit, and selection information is sent to an OR gate for selection information to determine whether or not a signal has been selected. can be obtained as the output of Therefore, the signal non-selection state can be recognized, and it is possible to test whether the off state of the switch is normal based on the state of the output signal at this time. especially,
Since the output regarding the selection information is transmitted in pairs with the output signal line, by setting all the selection information to non-selection, it is possible to perform an output L test in which all the input signals are set to H. Therefore, tests on multi-stage switches can be easily performed.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A programmable logic device according to the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the overall configuration, which consists of a wiring block 10 and a plurality of unit cells 12.

The wiring block 10 has signal lines X and signal lines Y, of which only a desired signal line is selected and connected to each unit cell 12.

In order to select this signal line, a large number of unit switches 22 are provided in the wiring block 10 as crossbar switch means corresponding to each unit cell 12, respectively.

As shown in FIG. 2, this unit switch 22 has four AND gates 3 on the path to the signal line Y.
0, 32, 34, and 36, and one OR gate 40, and an AND gate 42, an OR gate 44, and an AND gate 46 on the path to the signal line Y'. and,
The input signal lines consist of four main signal lines X0 to X3 and their respective auxiliary signal lines X'0 to X'3, and the output signal lines consist of the main signal line Y0 and the auxiliary signal line Y'0. There is. Further, selection information signal lines Q0 to Q3 regarding which of the input signal lines X0 to X3 to select are inputted.

The signals X0 and Q0 are input to the AND gate 30, and the signals X1 and Q1 are input to the AND gate 32.
X2 and Q2 are input to the AND gate 34, X3 and Q3 are input to the AND gate 36,
The outputs of the AND gates 30 to 36 are connected to an output signal line Y0 via an OR gate 40.

On the other hand, the auxiliary signal lines X'0 to X'3 are input to the AND gate 42, and the selection information signal lines Q0 to Q3 are input to the AND gate 42.
is input to the OR gate 44. The outputs of the AND gate 42 and the OR gate 44 are connected to the auxiliary signal line Y'0 via an AND gate 46.

Therefore, if any one of the auxiliary signal lines X'0 to X'3 is L, the OR gate 42 outputs L,
If any of the selection information signal lines Q0 to Q3 is set to H, the OR gate 44 outputs H. And gate 46 outputs H only when the two inputs are H. Therefore, if even one of the auxiliary signal lines X'0 to X'3 is L, the signal line Y'0 becomes L, and if all the selection information lines are L, the signal line Y' becomes L. It becomes L. Therefore, even if one of the switches in the signal transmission path selects the selection information lines Q0 to Q3,
are all L, this is transmitted through the auxiliary signal line Y', and the auxiliary signal line Y' is always at L.

In this way, in the auxiliary signal line Y'0,
It is possible to determine whether signal transmission in this switch has occurred (recognition that the switch is on). Therefore, the state in which no signal is selected (the switch is turned off) can be recognized by the fact that the auxiliary signal line Y'0 is L, and by checking the state of the output signal line Y0 in this state, it is possible to determine whether the switch is turned off. You can check whether or not. Therefore, like a conventional pass transistor,
There is no need to test high impedance,
The switch-off state can be easily inspected.

Furthermore, if the signal of this auxiliary signal line Y'0 is taken out separately for each pass transistor, the number of signal lines will increase, which is not practical. Therefore, in this embodiment, this auxiliary signal line Y'0 and the main signal line Y0 are connected to the same member as a pair. Therefore, even when a plurality of switches, unit cells, etc. are broken, by checking the states of these two signal lines, it is possible to obtain the output of the test result in the final IO cell.

That is, as shown in FIG. 3, the four input signal lines X0 to X3 are connected to the four unit switches 22a to 22.
2d, and output signal lines Y0 to Y3 from each
, and input these Y0 to Y3 to unit switches 22e to 22h, respectively, and output signal lines Z0 to Z3.
Consider the case where we obtain . In this case as well, it is assumed that the input signal line and the output signal line consist of a pair of a main signal line and an auxiliary signal line. Then, switch 22a turns off this switch and changes the state of the output signal line to switch 22a.
The test is performed on the output signal line Z0 from e. In this case, in the switch 22e, Q0 is set to H, and the signal Y0 is outputted to Z0. In this way, when the switch 22a is in the OFF state, both of its output signal lines Y0 and Y'0 become L. Then, this signal is input to the switch 22e, and Z0,
Z'0 becomes L, L.

In this way, L and L signals can be obtained on the output signal line of the switch 22e. Therefore, if this Z0 signal is transmitted through a plurality of switches, unit cells, etc., L will be obtained as an auxiliary signal line, and the switch OFF state of the switch 22a can be tested by checking the H and L states of the signal lines. be able to.

As described above, according to this embodiment, it is possible to determine whether the switch is off or not based on the L of the auxiliary signal line. Therefore, the selection information can be easily inspected.

[0028]

[Effects of the Invention] As explained above, according to the present invention,
Since the OFF state of the switch that transmits the signal can be tested using the H and L output signal lines, there is no need to detect the high impedance state as in the past, and the switch can be easily tested. .

[Brief explanation of drawings]

FIG. 1 is an overall configuration diagram of a PLD according to the present invention.

FIG. 2 is a configuration diagram of a unit switch 22.

FIG. 3 is a configuration diagram showing the connection state of the unit switch 22.

FIG. 4 is a diagram showing the configuration of a conventional switch.

FIG. 5 is an explanatory diagram showing an inspection method.

[Explanation of symbols]

10 Wiring block 12 Unit cell 20 Switch part 22 Unit switch 30-36 And Gate 40, 42 Or Gate X0 ~ X3 Input signal line X'0 to X'3 Auxiliary signal line Q0 ~ Q3 Selection information signal line Y0 ~ Y3 Output signal line

Claims (1)

[Claims] 1. A plurality of unit cells, each of which performs a predetermined unit logical operation, and a plurality of switch means for selecting one specified by selection information from among a plurality of input signal lines and connecting it to each unit cell. In the programmable logic device, the switch means includes a plurality of main signal AND circuits each receiving one input signal line and a selection information input line that transmits selection information about the input signal line; An OR circuit for the main signal into which the output of the AND circuit is input, an OR circuit for selection information into which the selection information input line of which is input to all the multiple AND circuits, and an OR circuit for selection information into which the output of the AND circuit of a first AND circuit for auxiliary signals, into which is input an auxiliary signal line indicating whether data is transmitted in the preceding switch means connected to the signal line, an OR circuit for selection information, and an auxiliary signal; A programmable logic device comprising: a second AND circuit for auxiliary signals into which the output of the OR circuit for auxiliary signals is input.