JPH0434008U - - Google Patents
Info
- Publication number
- JPH0434008U JPH0434008U JP7518890U JP7518890U JPH0434008U JP H0434008 U JPH0434008 U JP H0434008U JP 7518890 U JP7518890 U JP 7518890U JP 7518890 U JP7518890 U JP 7518890U JP H0434008 U JPH0434008 U JP H0434008U
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- output
- gain amplifier
- input
- variable gain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 108010007666 IMP cyclohydrolase Proteins 0.000 claims 1
- 102100020796 Inosine 5'-monophosphate cyclohydrolase Human genes 0.000 claims 1
- 239000000284 extract Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 6
Landscapes
- Manipulation Of Pulses (AREA)
Description
第１図及び第２図はこの考案に係る周波数逓倍
装置の実施例を示し、第１図は構成ブロツク図、
第２図は他の応用例を示す部分回路図であり、第
２図Ａは逓倍効率向上のアイドラ回路を付加した
部分回路図、第２図Ｂは出力レベル設定用減衰器
を設けた部分回路図、第２図ＣはＡＬＣ増幅器の
出力に可変抵抗器を介して外部信号を加え振幅変
調を掛けた例を示す部分回路図である。第３図は
従来例を示す構成ブロツク図である。
主な符号の説明、１……入力側可変利得増幅器
、２……周波数逓倍器、３……可変バンドパスフ
イルタ、４……出力側可変利得増幅器、５……出
力レベル検出器、６……ＡＬＣ増幅器、７……周
波数カウンタ、８……周波数制御器、９……逓倍
次数設定器。
1 and 2 show an embodiment of the frequency multiplier according to this invention, and FIG. 1 is a configuration block diagram,
Figure 2 is a partial circuit diagram showing another application example, Figure 2A is a partial circuit diagram with an idler circuit added to improve multiplication efficiency, and Figure 2B is a partial circuit diagram with an attenuator for setting the output level. FIG. 2C is a partial circuit diagram showing an example in which an external signal is applied to the output of an ALC amplifier via a variable resistor to perform amplitude modulation. FIG. 3 is a block diagram showing a conventional example. Explanation of main symbols: 1... Input side variable gain amplifier, 2... Frequency multiplier, 3... Variable band pass filter, 4... Output side variable gain amplifier, 5... Output level detector, 6... ALC amplifier, 7...frequency counter, 8...frequency controller, 9...multiplication order setter.
Claims (1)
した高周波信号の高調波成分を取出す周波数逓倍
器において、 前記周波数逓倍器の入力側には可変利得増幅器
と、出力側には可変バンドパスフイルタと、可変
利得増幅器と、前記出力側の可変利得増幅器から
の出力信号を検出する出力レベル検出器と、出力
レベル検出器からの信号によつて前記入出力２つ
の可変利得増幅器を制御するＡＬＣ（ＡＵＴＯＭ
ＡＴＩＣ ＬＥＶＥＬ ＣＯＮＴＲＯＬ）増幅器
と、入力側可変利得増幅器に加えられる高周波信
号を入力して周波数をカウントする周波数カウン
タと、逓倍次数を設定する逓倍次数設定器と、こ
の逓倍次数設定器によつて設定したデータと周波
数カウンタの出力とにより可変バンドパスフイル
タを制御する周波数制御器とを設け、入力周波数
の逓倍次数が可変可能で出力レベルを一定に得ら
れるように構成したことを特徴とする周波数逓倍
装置。[Claims for Utility Model Registration] A frequency multiplier that includes a nonlinear element and a frequency tuning circuit and extracts harmonic components of an input high frequency signal, the frequency multiplier having a variable gain amplifier and an output on the input side of the frequency multiplier. On the side, there is a variable band pass filter, a variable gain amplifier, an output level detector for detecting the output signal from the variable gain amplifier on the output side, and a signal from the output level detector to control the input and output voltages. ALC (AUTOM) that controls the gain amplifier
ATIC LEVEL CONTROL) amplifier, a frequency counter that counts the frequency by inputting the high frequency signal applied to the input side variable gain amplifier, a multiplication order setter that sets the multiplication order, and the multiplication order setter that sets the multiplication order. A frequency multiplier comprising a frequency controller that controls a variable bandpass filter based on data and the output of a frequency counter, and configured so that the multiplication order of the input frequency can be varied and a constant output level can be obtained. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990075188U JP2572455Y2 (en) | 1990-07-17 | 1990-07-17 | Frequency multiplier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990075188U JP2572455Y2 (en) | 1990-07-17 | 1990-07-17 | Frequency multiplier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0434008U true JPH0434008U (en) | 1992-03-19 |
| JP2572455Y2 JP2572455Y2 (en) | 1998-05-25 |
Family
ID=31615547
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1990075188U Expired - Lifetime JP2572455Y2 (en) | 1990-07-17 | 1990-07-17 | Frequency multiplier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2572455Y2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2017017546A (en) * | 2015-07-01 | 2017-01-19 | パナソニックＩｐマネジメント株式会社 | High frequency output control circuit |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57186806A (en) * | 1981-05-12 | 1982-11-17 | Mitsubishi Electric Corp | Higher harmonic cenerating circuit |
| JPS6352502A (en) * | 1986-08-22 | 1988-03-05 | Matsushita Electric Ind Co Ltd | multiplier |
-
1990
- 1990-07-17 JP JP1990075188U patent/JP2572455Y2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57186806A (en) * | 1981-05-12 | 1982-11-17 | Mitsubishi Electric Corp | Higher harmonic cenerating circuit |
| JPS6352502A (en) * | 1986-08-22 | 1988-03-05 | Matsushita Electric Ind Co Ltd | multiplier |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2017017546A (en) * | 2015-07-01 | 2017-01-19 | パナソニックＩｐマネジメント株式会社 | High frequency output control circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2572455Y2 (en) | 1998-05-25 |
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