JPH04340199A - Signal processor - Google Patents

Abstract

PURPOSE:To receive respective digital signals by the same filter without distinguishing abnormal communication of a transmitter from its normal one and to allow a receiver to distinguish respective communication states in a signal processor constituted of the transmitter and the receiver. CONSTITUTION:Physical quantity to be measured by a sensor is converted into an electric signal, which is sent as a current signal by signal processing. In the signal processor consisting of the transmitter for superposing a digital signal to the current signal when necessary and transmitting the superposed signal to a load through two transmission lines and the receiver connected to the transmitter and executing communication at least through the above digital signal, the receiver is provided with an input filter part 22 for inputting an abnormal code caused by transmitter abnormality transmitted from the transistor by the superposition to the current signal and a decoding part 23 for decoding whether the abnormal code coincides with a prescribed abnormal code or not, and at the time of judging abnormality, outputting an abnormality signal.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention converts a physical quantity to be measured by a sensor into an electrical signal, processes this signal, sends it out as a current signal, and superimposes a digital signal on this current signal as necessary. Regarding a signal processing device consisting of a transmitter that transmits data to a load via a main transmission line and a receiver that is connected to the transmission line and communicates at least via the digital signal, in particular, an abnormal situation has occurred in the transmitter. The present invention relates to a signal processing device that has been improved to be able to rationally receive abnormality codes that are sometimes sent out.

0002

2. Description of the Related Art FIG. 11 is a block diagram showing the configuration of a conventional signal processing device. Reference numeral 10 denotes a two-wire transmitter that converts physical quantities such as process variables into electrical signals and transmits them, and is supplied with power from a DC power supply 11 via a load 12 . The electrical signal is transmitted as a current signal by the transmission lines L1 and L2, and the process variable is known at the receiver 15 by detecting the voltage change occurring across the load 12.

The current signal is converted into a unified current IL of 4 to 20 mA and transmitted by a transmitter 10 set to a range corresponding to the pressure in the pipe, for example. In this case, it would be convenient if the transmitter 10 could be operated from outside, for example, when changing or monitoring the pressure range. For this reason, a handheld terminal 1 that functions as a communication device is used.
3 to the transmission lines L1 and L2 using connection lines L1' and L2' as necessary, and the transmitter 10 is provided with a dedicated data communication function with the handheld terminal 13. Digital data such as parameter changes is transmitted from the terminal 13 to the transmitter 10. In addition, load 12
A receiver 15 including an interface 14 is connected to both ends of the receiver.

Next, each component configured as described above will be explained in detail. Of these, the transmitter 10 is configured as follows. SNR is a sensor that detects pressure/differential pressure, etc. and converts it into an electrical signal.The converted analog signal is converted into a digital signal by an analog/digital converter A/D, and then sent to the memory MEM via the microprocessor μP1. is stored in the random access memory portion of. Using this stored digital signal, the microprocessor μP1 executes a predetermined operation such as linearization according to the operation procedure written in the read-only memory part of the memory MEM, and converts the digital signal to the digital/analog converter D.
/A to the output circuit OPC. On the other hand, the results of predetermined calculations by the microprocessor μP1 are digitally displayed with the necessary number of digits on the built-in monitor LCD.

[0005] The output circuit OPC outputs the voltage signal converted into an analog signal by the digital/analog converter D/A.
Convert it to a unified current signal IL of 0mA and connect it to the transmission line L.
1, transmitted to the load 12 via L2. Further, the output circuit OPC generates a power source for the internal circuit of the transmitter 10 using a part of the current signal IL. The IFC is an interface for data communication with the handheld terminal 13, and is connected between the transmission lines L1 and L2 and the microprocessor μP1, and converts the digital signals from the transmission lines L1 and L2 into parallel data. It has a function of transmitting data to the microprocessor μP1 as a serial signal, and conversely transmitting data from the microprocessor μP1 as a serial signal to the transmission lines L1 and L2.

Next, the handheld terminal 13 is constructed as follows. The SER is a setting device operated by an operator and has a built-in monitor. Various settings or requests can be made, such as requesting a model of the transmitter 10, changing the display cycle, changing the range, detecting an abnormality, or displaying the value of the current signal IL.

[0007] μP' is a microprocessor to which, for example, data from a setting device SER is input, and a memory MEM
A digital signal is sent to the transmitter 10 via the interface IFC' in accordance with the processing procedure stored in '. Further, the microprocessor μP' takes the response data from the transmitter 10 into the memory MEM' via the interface IFC', decodes it according to the processing procedure stored in the memory MEM', and inputs the response data from the setting device SER. Display on monitor.

Next, the receiver 15 including the interface 14 connected to the load 12 will be explained. Transmitter 1
From 0, the digital signal as well as the current signal IL is applied to the load 12.
transmitted to. These mixed signals of analog and digital signals are separated by the signal conditioner SC of the interface 14, and the analog signals as PV values, which require high-speed real-time performance, are processed under the control of the microprocessor μP2. Analog input/output card I/
The digital signals are collected via the communication card CMN under the control of the microprocessor μP2. Then, it is output to a higher-level system, etc., as necessary.

[0009] Conversely, from the upper system, the receiver 15
A digital signal is sent to the transmitter 10 via the communication card CMN, the signal conditioner SC, the load 12, and the transmission lines L1 and L2, thereby realizing two-way communication.

However, the above signal transmission device has a receiver 1 including a transmitter 10 and an interface 14.
5 or the handheld terminal 13 side, the content of the communication is determined by the request from the receiver 15 side or the handheld terminal 13 side. Therefore, the state of the transmitter 10 cannot be determined unless the receiver side asks whether it is normal or abnormal, and even if the transmitter 10 detects an abnormality, it cannot be communicated to the receiver 15 side. For this reason, especially when the transmitter 10 is incorporated in a control loop, even if an abnormal situation occurs in the transmitter 10, this cannot be instantly notified to the receiver 15. The problem is that it increases the number of accidents.

[0011] Therefore, the present applicant proposed a solution to this problem in Japanese Patent Application No. 2-189234 (title of invention: 2-wire transmitter) on July 17, 1990. The outline of this application will be explained below with reference to FIG. 12. Reference numeral 16 is a transmitter, and physical quantities such as differential pressure detected by the sensor SNR of this transmitter 16 and converted into an electric signal are transferred to the analog/digital converter A/ The signal is converted into a digital signal at D, taken into the microprocessor μP3, and stored as data in the memory MEM.

The microprocessor μP3 has a memory MEM
Using the data stored in , necessary calculations such as linearity correction are performed based on a predetermined calculation program stored here, and the data is sent to the output circuit OPC via the digital/analog converter D/A. Output. Microprocessor μP3
The predetermined calculation result is digitally displayed with the necessary number of digits on the built-in monitor LCD. The output circuit OPC converts the voltage signal converted into an analog signal by the digital/analog converter D/A into a unified current signal IL of 4 to 20 mA, and transmits it to the load 12 via transmission lines L1 and L2.

[0013] MDM1 connects load 1 via output circuit OPC.
Digital communication is performed with a controller 17 which also serves as a receiver connected to the controller 2. This modem MDM1 is connected between the transmission lines L1 and L2 and the microprocessor μP3, and demodulates the digital signals from the transmission lines L1 and L2 and transmits them as parallel data to the microprocessor μP3, and vice versa. The frequency band of the digital signal output from this modem MDM1 and used for normal communication is, for example, fCL to fCH.
It's inside.

MDU1 is a modulator, and this modulator MD
U1 is connected to an output circuit OPC via a switch SW1, and outputs an abnormality diagnosis signal S1 having a frequency f0. This frequency f0 is set outside the frequency band (fCL to fCH) used in normal digital communication of the modem MDM1. The microprocessor μP3 diagnoses the operation of the transmitter 15 according to the diagnostic program stored in the memory MEM1, and when it is determined that there is an abnormality based on the diagnosis result, the diagnostic signal S2 is sent to the switch SW1.
The abnormality diagnosis signal S1 of the modulator MDU1 is outputted to the output circuit OPC by turning it on. The output circuit OPC transmits this abnormality diagnosis signal S1 to the transmission lines L1 and L2 as a current signal I.
It is superimposed on L and transmitted to the load 12.

A controller 17 is connected to the load 12. This controller 16 interface IN
F is analog signal from sensor SNR and modem MDM1
The control unit C separates the digital signal transmitted through the
Output to NT. The interface INF has a built-in bandpass filter having a bandwidth (fCL to fCH) used for normal digital communication in order to remove noise mixed in as disturbance. Further, a bandpass filter BPF1 connected to the load 12 and passing the frequency f0 checks whether the input signal includes the abnormality diagnosis signal S1. If this abnormality diagnosis signal S1 exists, it is sent to the control unit CNT, and the transmitter 15 notifies that an abnormality has occurred.

[0016] Upon learning of this abnormality, the control unit CNT goes to the transmitter 15 via the interface INF to check the details of the abnormality. In this way, with the configuration shown in FIG. 12, abnormalities in the transmitter 15 can be instantly known. Therefore, in the signal processing device shown in FIG. 12, when an abnormal situation occurs in the transmitter 16, the transmitter 16 automatically detects the abnormality without issuing a transmission request from the load 12 side, and immediately sends the abnormal signal. Since the signal is sent to the load side via the transmission line, even when the transmitter 16 is incorporated in the control loop, abnormalities can be instantly detected and the spread of accidents can be prevented.

[0017]

However, the controller 17 that functions as a receiver of the signal processing device shown in FIG. 12 has a bandwidth (fCL to fCH)
The bandpass filter and the bandwidth for detecting the abnormality diagnosis signal S1 having the frequency f0 are (fCL to fCH).
Bandpass filter BPF1 and 2 set outside the range of
A different type of bandpass filter is required, which is disadvantageous in terms of cost and current consumption.

[0018]

[Means for Solving the Problems] In order to solve the above problems, the present invention converts a physical quantity to be measured by a sensor into an electric signal, processes the signal, sends it as a current signal, and also converts the physical quantity to be measured by a sensor into an electric signal. Signal processing consisting of a transmitter that superimposes a digital signal on this current signal and transmits it to the load via two transmission lines, and a receiver that is connected to the first transmission line and communicates at least via the first digital signal. Regarding the device, the first receiver has an input filter section that takes in an abnormality code caused by an abnormality in the first transmitter, which is superimposed on the current signal and transmitted from the first transmitter, and a filter section that takes in an abnormality code caused by an abnormality in the first transmitter. The decoding unit is provided with a decoding section which decodes whether or not the code matches the abnormality code of the code and outputs an abnormality signal if an abnormality occurs.

[0019]

[Operation] The transmitter and receiver normally communicate with each other using predetermined digital signals, but if an error occurs in the transmitter, the transmitter automatically sends an error code to the receiver side. . On the receiver side, an input filter unit takes in an abnormality code that indicates an abnormality in the transmitter and is transmitted from the transmitter superimposed on the current signal. Then, the decoding section decodes whether or not this abnormal code matches a predetermined abnormal code, and if it is abnormal, it outputs an abnormal signal, and if it is not abnormal, it is processed as normal digital communication. . In this way, the receiver according to the present invention can perform normal digital communication through one filter, and can also detect an abnormal code and output an abnormal signal.

[0020]

[Embodiments] Hereinafter, embodiments of the present invention will be explained with reference to the drawings. FIG. 1 is a block diagram showing the overall configuration of one embodiment of the present invention. The transmitter 18 connects the load 1 from the DC power supply 11.
2, a sensor built into the transmitter 18 converts the physical quantity into an electrical signal, performs predetermined signal processing, and transmits it to the load 12 as an analog current signal IL. Furthermore, the transmitter 18 superimposes a digital signal for communicating with the load 12 side on this current signal IL and transmits it to the load 12 side via the transmission lines L1 and L2.

This transmitter 18 normally performs bidirectional communication with the load 12 in a predetermined frequency band, and when the transmitter 18 malfunctions, it automatically switches to the same frequency band as this frequency band. It is configured to be switched to output an abnormality code having a specific code, and to repeatedly output this abnormality code as long as the abnormal operation continues.

A receiver 19 is connected to the load 12, and the signal voltage Vi converted by the load 12 is input to the receiver 19, and the voltage Eb supplied from the DC power supply 11 is input to the receiver 19.
The signal processing unit 20 processes the signal and transmits the contents to a higher-level controller as necessary. Furthermore, the receiver 19 has a built-in signal discriminator 21, and the transmitter 1
It is configured to determine whether the digital signal transmitted from 8 is a digital signal during normal operation or an abnormal code of a specific code sent in an abnormal state, and to notify the signal processing unit 20 of the result. ing.

The contents of this signal discriminator 21 will be explained in detail below. FIG. 2 is a block diagram showing the overall configuration of the signal discriminator 21. As shown in FIG. The signal discriminator 21 includes an input filter section 22, a decode section 23, a clock generator 24, a contact control section 25, a contact output section 26, a power supply section 27, and the like.

The signal voltage Vi is filtered by an input filter section 22 having a bandpass filter to cut the DC component and further to discriminate noise, and then sent to a decoding section 23.
is output to. The decoding section 23 is supplied with the clock signal CLK from the clock generating section 24 and determines whether the input signal voltage Vi has an abnormal code or not, and then outputs the signal via the next contact control section 25. It is output to the contact output section 26. The contact output section 26 outputs a contact signal when an abnormality is detected.

The internal voltage Vcc and reference voltage Vs used inside the signal discrimination section 21 are generated by the power supply section 27 using the voltage Eb supplied from the DC power supply 11. Next, Figure 3 shows the internal circuit of each block configured as described above.
~Explained using FIG. 10. FIG. 3 shows the input filter section 22
The circuit is shown below. The inverting input terminal (-) of the operational amplifier Q1, whose non-inverting input terminal (+) is connected to the reference potential Vs, is connected to the resistor R.
A parallel circuit in which R1 and capacitor C1 are connected in parallel is connected between the output terminal and a resistor R2 and capacitor C2.
input voltage Vi through a series circuit connected in series with
is applied.

The input voltage V is set by the resistor R2 and the capacitor C2.
The low frequency component included in i is cut, and the high frequency component is cut by resistor R1 and capacitor C1, thereby forming a bandpass filter. Therefore, only the input voltage Vi in a predetermined frequency band is filtered, that is, noise is cut, and output as the output voltage Vf at the output terminal. This situation is shown in FIG. Figure 4 (
4A shows the input voltage Vi, and FIG. 4B shows the output voltage Vf. Since the whisker-like noise N included in FIG. 4(a) is outside the frequency band used for predetermined communication, it is cut and output as shown in FIG. 4(b). Note that the input voltage Vi is as shown in FIG. 4(b).
For example, “1” indicates when a strike wave exists, and “1” indicates that there is no strike wave.
0". Also, the waveform of the burst wave in this case is made so that the number of positive and negative pulses is the same,
The analog signal detected by the signal processing section 20 is kept unchanged.

FIG. 5 shows a circuit of the decoding section 23. Q1
, Q2 is a comparator energized by the power supply voltage Vcc, and the inverting input terminal (-) of the comparator Q1 and the comparator
The reference voltage Es is connected to the non-inverting input terminal (+) of the transistor Q2 through the resistor R.
3, the divided voltages V1 and V2 divided by R4, R5, and R6 are applied, and the non-inverting input terminal (+
) and the inverting input terminal (-) of the comparator Q2 are respectively applied with an output voltage Vf.

The comparison outputs V3 and V4 outputted to the output terminals of the comparators Q1 and Q2 are logically summed by an OR gate Q4 and sent to a buffer gate Q via a filter F1.
The signal is output as a decoded signal V5 to the output terminal of V5. Decode signal V5 is retriggerable multivibrator Q6
The retriggerable multivibrator Q6 receives a predetermined pulse as long as the decode signal V5 is input to its output terminal <Q>(<Q> indicates the inversion of Q). The width is, for example, 5T (T is one cycle of the burst wave) and the low
A pulse signal V6 having the same level is output.

On the other hand, the clock signal CLK is output from the clock generator 24 to the clock terminal CL of the frequency divider Q7.
The frequency divider Q7 is controlled by the pulse signal V6 inputted to the control terminal R, and outputs a pulse signal V7 having a predetermined pulse width to its output terminal Q. The decode signal V5 and the pulse signal V7 are input to the input terminal of the exclusive OR gate Q8, the exclusive OR of these is calculated, and the output is outputted as the pulse signal V8 via the inverter Q9. Ru.

This pulse signal V8 is applied to the AND gate Q10.
is inputted to one input terminal of , and the other input terminal via inverter Q11 and filter F2, and the AND is calculated, and a pulse is generated as pulse signal V9 at the output terminal by the rise of pulse signal V8. . This pulse signal V9 is input to the input terminal A of the one-shot multivibrator Q12, and at the rising edge of the pulse signal V9, the pulse width becomes 2TX5.
A pulse signal V10 is generated.

Q13 is a NAND gate, to which a pulse signal V6 is applied via an inverter Q14, and to which pulse signals V8 and V10 are applied, respectively, and a contact signal S1 is generated at its output terminal. let Next, the operation of the decoding section 23 configured as described above will be explained using the waveform diagram shown in FIG.

Output voltage Vf of input filter section 22 (FIG. 6
a comparator Q2 in which (a)) has different comparison levels;
When input to Q3, these output terminals each have a
As shown in FIG. 6(b) and FIG. 6(c), comparison outputs V3 and V4 having binary levels of "high" and "low" are output. Therefore, when the logical sum of these is calculated by the OR gate Q4 and outputted via the filter F1 and the buffer gate Q5, the output voltage Vf is decoded at the output terminal as shown in FIG. 6(d). Decoded signal V with digital values of 1 and 0
Obtained as 5.

The retriggerable multivibrator Q6 has a decoder having the digital values of 1 and 0 at its input terminal A.
When the code signal V5 is input, for example, a low-level pulse signal V6 (FIG. 6(e)) having a pulse width of 5T is outputted to the output terminal <Q>. When this low-level pulse signal V6 is applied to the control terminal R of the frequency divider Q7, the output terminal Q of the frequency divider Q7 receives a pulse signal V7 as shown in FIG. is output.

[0034] Exclusive or gate Q8 is a deco
The exclusive OR of the code signal V5 and the pulse signal V7 is calculated, and a pulse signal V8 as shown in FIG. 6(g) is outputted from its output terminal via an inverter Q9. This pulse signal V8 becomes high level when the decode signal V5 and pulse signal V7 match, and becomes low level when they do not match.

FIG. 6 (h
), a pulse signal V9 is output as a trigger pulse in synchronization with the rise of the pulse signal V8 shown in FIG. 6(g), and this pulse signal V9 causes the output terminal of the one-shot multivibrator Q12 to As shown in (i), a pulse signal V10 having a pulse width of 2TX5 is output.

Therefore, when the decode signal V5 and the pulse signal V7 match during the 2TX5 period, the output terminal of the NAND gate Q13 indicates an abnormal code after the 2TX5 period has elapsed. When the pulse arrives, the contact signal S1 becomes low level as shown in FIG. 6(j). However, here, as the abnormal code, 1, as shown in Fig. 6(d),
A code consisting of 5 bits: 0, 1, 0, 1 is assumed. That is, when the contact signal S1 is at a low level, it is determined that an abnormal code has arrived, and when it is at a high level, it is determined that a normal digital communication signal has arrived.

FIG. 7 is a circuit diagram showing details of the contact output control section 25 shown in FIG. 2, and FIG. 8 is a waveform diagram illustrating the operation of this circuit. The contact signal S1 is inputted to the input terminal CL of the flip-flop Q16 via the inverter Q15, and the power supply voltage Vcc is applied to the data terminal D, and the contact signal is output from the output terminal Q via the inverter Q17. S2 is output. The contact signal S1 shown in FIG. 8(a) outputted from the decoding section 23 remains at a high level in a normal communication state, and is inverted to a low level when an abnormality code is input. Therefore, the flip-flop Q16 detects the low level of this contact signal S1 and detects this abnormal state in FIG. 8(b).
), it is latched and output to the contact output unit 26 as a low-level contact output S2.

FIG. 9 is a circuit diagram showing the configuration of the contact output section 26, and FIG. 10 is a waveform diagram illustrating the operation of this circuit. The contact signal S2 (FIG. 10(a)) output from the contact output control section 25 is inverted by an inverter Q18, and the base and emitter are connected by a resistor R8 to the collector via a resistor R7. A predetermined voltage +E is applied to the base of the transistor Q19, and a contact signal S3 (FIG. 10(b)) is output from the collector as an on/off contact output. As shown in FIG. 10(b), this contact signal S3 outputs a contact signal having a predetermined rating corresponding to +E, such as driving a transistor, as an abnormality code.

In the above explanation, the waveform of the communication signal has been explained as being based on a burst wave, but the communication signal may have a waveform different from this. In addition, although 1, 0, 1, 0, 1 was used as an example of the abnormal code, any code that is not used as a normal communication signal can be used. It's okay. Contact output control
The loop portion 25 is not necessarily necessary. When not in use, an abnormality can be detected at a low level only when an abnormal signal is output. Further, the abnormality signal may be an on/off signal of a predetermined cycle when an abnormality occurs.

Furthermore, the input terminal of the signal discriminator 21 is connected to the load 1.
2 and the DC power supply 11 may be connected to both ends of a series circuit in which they are connected in series. The receiver may be connected to a transmission line as required, similar to the handheld terminal 13 shown in FIG. 11.

[0041]

[Effects of the Invention] As specifically explained below with the embodiments, according to the present invention, the digital signal for communication transmitted from the transmitter and the abnormality output when the transmitter is in an abnormal state. code through the same filter,
Since the received digital signal is determined by the signal discrimination unit to determine whether it is a communication signal or an abnormal code, it is possible to share the filter, which occupies an important position in the receiver, and this reduces costs. In addition to reducing current consumption, it is possible to detect abnormalities in the transmitter at an early stage.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the overall configuration of an embodiment of the present invention.

FIG. 2 is a longitudinal cross-sectional view showing the configuration of the signal discriminator shown in FIG. 1;

FIG. 3 is a circuit diagram showing the configuration of the input filter section shown in FIG. 2;

FIG. 4 is a waveform diagram illustrating the operation of the input filter section shown in FIG. 3;

FIG. 5 is a block diagram showing the configuration of the decoding section shown in FIG. 2;

6 is a waveform diagram illustrating the operation of the decoding section shown in FIG. 5. FIG.

7 is a circuit diagram showing the configuration of the contact output control section shown in FIG. 2. FIG.

8 is a waveform diagram illustrating the operation of the contact output control section shown in FIG. 6. FIG.

9 is a circuit diagram showing the configuration of the contact output section shown in FIG. 2. FIG.

10 is a waveform diagram illustrating the operation of the contact output section shown in FIG. 9. FIG.

FIG. 11 is a block diagram showing the configuration of a first conventional signal processing device.

FIG. 12 is a block diagram showing the configuration of a second conventional signal processing device.

[Explanation of symbols]

10, 16, 18 Transmitter 12 Load 13. Handheld terminal 14 Interface 15, 19 Receiver 17 Controller 20 Signal processing section 21 Signal discrimination section 22 Input filter section 23 Decoding section 24 Clock generation section 25 Contact output control section 26 Contact output section

Claims (1)

[Claims] Claim 1: Converts a physical quantity to be measured by a sensor into an electrical signal, processes the signal, sends it out as a current signal, and superimposes a digital signal on this current signal as necessary.
In a signal processing device that includes a transmitter that transmits to a load via a real transmission line and a receiver that is connected to the transmission line and communicates at least via the digital signal, the receiver receives a current signal from the transmitter. an input filter section that takes in an abnormality code caused by an abnormality in the transmitter that is transmitted superimposed on the transmitter; 1. A signal processing device comprising a decoding section that sometimes outputs an abnormal signal.